)]}'
{
  "commit": "ebd16fd5dd23b2809705e3e6fcaf549f2ac0b8ae",
  "tree": "83581881f58d95a57128d83710f0c8ab0279ce08",
  "parents": [
    "3689529ec63897d83a059d0ba48126633f7b2250"
  ],
  "author": {
    "name": "Kalen Brunham",
    "email": "kalen.brunham@intel.com",
    "time": "Fri Dec 12 01:31:42 2025 +0000"
  },
  "committer": {
    "name": "Kalen Brunham",
    "email": "kalen.brunham@intel.com",
    "time": "Fri Dec 12 01:31:42 2025 +0000"
  },
  "message": "Added test which fails for this case\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ba5180254ee179def5934f36c6b394bd733e1a34",
      "old_mode": 33188,
      "old_path": "verible/verilog/formatting/formatter_test.cc",
      "new_id": "b3915f1391ae73c846290e6d6fc1710ea530181c",
      "new_mode": 33188,
      "new_path": "verible/verilog/formatting/formatter_test.cc"
    }
  ]
}