diff --git a/README.md b/README.md
index 047fb20..c8fd785 100644
--- a/README.md
+++ b/README.md
@@ -192,14 +192,29 @@
 Moreover, if you need statically linked executables that don't depend on your
 shared libraries, you can use custom config
 `create_static_linked_executables` (with this setting `bfd` linker will be used,
-instead of default `gold` linker).
+instead of default `gold` linker). This is the same approach used by CI to
+produce the Linux static release tarballs, and is useful when you build on a
+newer distribution (for example Ubuntu 24.04) but need binaries that run on
+older systems whose glibc is too old for a dynamically linked build.
 
 ```bash
 # Generate statically linked executables.
-# Uses bfd linker and needs static system libs available.
+# Uses bfd linker and needs static system libs available
+# (e.g. libc.a / libstdc++.a from your C/C++ development packages).
 bazel build -c opt --config=create_static_linked_executables //...
+
+# Or build only the tools you need, e.g. the formatter:
+bazel build -c opt --config=create_static_linked_executables \
+  //verible/verilog/tools/formatter:verible-verilog-format
+
+# Same flag works with the install target:
+bazel build -c opt --config=create_static_linked_executables :install-binaries
+.github/bin/simple-install.sh ~/bin
 ```
 
+Confirm a binary is fully static with `ldd path/to/binary` (it should report
+that it is not a dynamic executable) or with `file path/to/binary`.
+
 See [Installation](#installation-1) for install.
 
 ### Optionally using local flex/bison for build
diff --git a/TODO.md b/TODO.md
new file mode 100644
index 0000000..d3bd744
--- /dev/null
+++ b/TODO.md
@@ -0,0 +1,61 @@
+# Kalen's TODO File
+
+This is Kalen's private TODO file. Don't attempt to upstream this.
+
+## Formatter issues to volunteer
+
+These are the next three issues to take after the current formatter PRs land
+([#2545](https://github.com/chipsalliance/verible/pull/2545),
+[#2543](https://github.com/chipsalliance/verible/pull/2543),
+[#2546](https://github.com/chipsalliance/verible/pull/2546),
+[#2548](https://github.com/chipsalliance/verible/pull/2548)).
+
+Samples were re-run on `origin/master` (`1ea007ec`, `v0.0-4148-g1ea007ec`).
+
+### 1. Crash on `wire signed` — [#2008](https://github.com/chipsalliance/verible/issues/2008)
+
+Also covers [#2474](https://github.com/chipsalliance/verible/issues/2474) and
+likely [#2063](https://github.com/chipsalliance/verible/issues/2063).
+
+The formatter **aborts** on `input wire signed [...]`. Five-line sample, same
+`tree-unwrapper.cc` CHECK. Highest new-issue value: crash, tiny repro, one family.
+
+Claim **#2008** and mark #2474 / #2063 as duplicates once they share the same abort.
+
+### 2. Long function header drops code — [#886](https://github.com/chipsalliance/verible/issues/886)
+
+Wrapping a long function header **drops the function parameters**. Still happens
+on current master: the formatted output is not even valid SystemVerilog. Worse
+than a style bug.
+
+Draft PR: [#2578](https://github.com/chipsalliance/verible/pull/2578)
+(`kbrunham-intel/fix/886`).
+
+### 3. Spaces inserted in `*nix` paths — [#2352](https://github.com/chipsalliance/verible/issues/2352)
+
+Turns `` `PATH_MY_MODULE/src/config_class.sv `` into
+`` `PATH_MY_MODULE / src / config_class.sv ``, which **does not compile**.
+Small, well-scoped.
+
+Draft PR: [#2577](https://github.com/chipsalliance/verible/pull/2577)
+(`kbrunham-intel/fix/2352`).
+
+## Issues I created
+
+### `formatter_test.cc` is too large — [#2579](https://github.com/chipsalliance/verible/issues/2579)
+
+`verible/verilog/formatting/formatter_test.cc` is ~21k lines. Split by concern
+(macros, alignment, wrapping, …) so formatter PRs stop colliding at the end of
+one file.
+
+### `run-format.sh` should be a no-op on master — [#2580](https://github.com/chipsalliance/verible/issues/2580)
+
+Running `.github/bin/run-format.sh` currently rewrites files that were already
+on master. Land a format-only cleanup so the tree matches CI style.
+
+### Other open formatter issues
+
+- [#2539](https://github.com/chipsalliance/verible/issues/2539) — CHECK abort on line-continuation before aligned ports. PR [#2546](https://github.com/chipsalliance/verible/pull/2546).
+- [#2542](https://github.com/chipsalliance/verible/issues/2542) — non-convergence with continuation EOL comments. PR [#2543](https://github.com/chipsalliance/verible/pull/2543).
+- [#2544](https://github.com/chipsalliance/verible/issues/2544) — MacroIdentifier vs MacroIdItem at EOL. PR [#2545](https://github.com/chipsalliance/verible/pull/2545).
+- [#2547](https://github.com/chipsalliance/verible/issues/2547) — non-convergence wrapping multi-line macro sums. PR [#2548](https://github.com/chipsalliance/verible/pull/2548).