This is Kalen‘s private TODO file. Don’t attempt to upstream this.
These are the next three issues to take after the current formatter PRs land (#2545, #2543, #2546, #2548).
Samples were re-run on origin/master (1ea007ec, v0.0-4148-g1ea007ec).
wire signed — #2008Also covers #2474 and likely #2063.
The formatter aborts on input wire signed [...]. Five-line sample, same tree-unwrapper.cc CHECK. Highest new-issue value: crash, tiny repro, one family.
Claim #2008 and mark #2474 / #2063 as duplicates once they share the same abort.
Wrapping a long function header drops the function parameters. Still happens on current master: the formatted output is not even valid SystemVerilog. Worse than a style bug.
Draft PR: #2578 (kbrunham-intel/fix/886).
*nix paths — #2352Turns `PATH_MY_MODULE/src/config_class.sv into `PATH_MY_MODULE / src / config_class.sv, which does not compile. Small, well-scoped.
Draft PR: #2577 (kbrunham-intel/fix/2352).
formatter_test.cc is too large — #2579verible/verilog/formatting/formatter_test.cc is ~21k lines. Split by concern (macros, alignment, wrapping, …) so formatter PRs stop colliding at the end of one file.
run-format.sh should be a no-op on master — #2580Running .github/bin/run-format.sh currently rewrites files that were already on master. Land a format-only cleanup so the tree matches CI style.