)]}'
{
  "id": "487cc596b00369fe0fb7d7f218ad491ab7a55dc5",
  "repo": "third_party/verible",
  "revision": "ee8d306975ffa331d0601bb2b4803f58a18e8328",
  "path": "verilog/analysis/checkers/plusarg_assignment_rule.cc"
}