)]}'
{
  "commit": "fef7c9429e4116818a4a31ad7eaa0a80a4137eef",
  "tree": "424ad1b25a4f6945baa6f73da73e2754f2e92135",
  "parents": [
    "b33cc90019824a8a157f2d5a042912a4b7d67391"
  ],
  "author": {
    "name": "Kalen Brunham",
    "email": "kalen.brunham@intel.com",
    "time": "Fri Jul 17 22:01:05 2026 +0000"
  },
  "committer": {
    "name": "Kalen Brunham",
    "email": "kalen.brunham@intel.com",
    "time": "Fri Jul 17 22:01:05 2026 +0000"
  },
  "message": "Fix formatter lexical mismatch for macros at end of line\n\nTreat spelling-equal MacroIdentifier and MacroIdItem as\nformat-equivalent so wrapping that leaves a bare `MACRO` at EOL\nno longer fails verification (issue #2544).\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f8a47d066ba719e4cffb4e943ebcf3d8bdb71874",
      "old_mode": 33188,
      "old_path": "verible/verilog/analysis/verilog-equivalence.cc",
      "new_id": "026c197cf257c99b38b77c5c88cf4d81cbcc2fed",
      "new_mode": 33188,
      "new_path": "verible/verilog/analysis/verilog-equivalence.cc"
    },
    {
      "type": "modify",
      "old_id": "90b0ee11bff460afaaf25c1dcfdcf1dca9b446a8",
      "old_mode": 33188,
      "old_path": "verible/verilog/analysis/verilog-equivalence_test.cc",
      "new_id": "1cb943646dfc57153df37dbbf223a5d88e912537",
      "new_mode": 33188,
      "new_path": "verible/verilog/analysis/verilog-equivalence_test.cc"
    },
    {
      "type": "modify",
      "old_id": "e885d742715a044ccf77fdc91791a1d2626e103e",
      "old_mode": 33188,
      "old_path": "verible/verilog/formatting/formatter_test.cc",
      "new_id": "654cc0aa374bc452c9c1a9c75a0c173ed478f0c0",
      "new_mode": 33188,
      "new_path": "verible/verilog/formatting/formatter_test.cc"
    }
  ]
}