| -------------------------------------------------------------------------------- | |
| name: lexer/parser issue about: Lexer and parser bugs title: '' labels: | |
| rejects-valid syntax assignees: '' | |
| -------------------------------------------------------------------------------- | |
| **Describe the bug** | |
| Short summary. | |
| **To Reproduce** | |
| ```systemverilog | |
| // Test case (preferably reduced) that illustrates the problem. | |
| ``` | |
| Include any options used. | |
| **Actual behavior:** | |
| Did it reject valid code? or crash? | |
| **Expected behavior** | |
| A clear and concise description of what you expected to happen. Citations to the | |
| [SystemVerilog-2017 Standard (LRM)](https://ieeexplore.ieee.org/document/8299595) | |
| would help. |