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foss-fpga-tools
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third_party
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verible
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7ef4fe45b18f3999c48af7db0b868d6fca18f025
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.
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verilog
/
tools
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syntax
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export_json_examples
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README.md
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Some
Python
examples
using
the json
export
of verible
-
verilog
-
syntax
to
do
interesting things
.
The
BUILD
.
example might be a starting point
in
case
you want to
use
this
in
a bazel project
.
Not
officially supported
.