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foss-fpga-tools
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third_party
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verible
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9c113b4bb8f7ee4712c206c94a2995ed900513c4
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.
/
verilog
/
tools
/
syntax
/
export_json_examples
/
README.md
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Some
Python
examples
using
the json
export
of verible
-
verilog
-
syntax
to
do
interesting things
.
The
BUILD
.
example might be a starting point
in
case
you want to
use
this
in
a bazel project
.
Not
officially supported
.