| -------------------------------------------------------------------------------- |
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| name: lexer/parser issue about: Lexer and parser bugs title: '' labels: |
| rejects-valid syntax assignees: '' |
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| -------------------------------------------------------------------------------- |
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| **Describe the bug** |
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| Short summary. |
| |
| **To Reproduce** |
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| ```systemverilog |
| // Test case (preferably reduced) that illustrates the problem. |
| ``` |
| |
| Include any options used. |
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| **Actual behavior:** |
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| Did it reject valid code? or crash? |
| |
| **Expected behavior** |
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| A clear and concise description of what you expected to happen. Citations to the |
| [SystemVerilog-2017 Standard (LRM)](https://ieeexplore.ieee.org/document/8299595) |
| would help. |
