)]}'
{
  "name": "third_party/verible",
  "clone_url": "https://foss-fpga-tools.googlesource.com/third_party/verible",
  "description": "Verible provides a SystemVerilog parser, style-linter, and formatter.",
  "mirrored_from_url": "https://github.com/google/verible.git"
}