Forgot to modify input to output golden result
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_multiclock/config/golden_results.txt
index eea1975..9ba3228 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_multiclock/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_multiclock/config/golden_results.txt
@@ -1,2 +1,2 @@
arch circuit crit_path_delay_(mcw) clk_to_clk clk_to_clk2 clk_to_input clk_to_output clk2_to_clk2 clk2_to_clk clk2_to_input clk2_to_output input_to_input input_to_clk input_to_clk2 input_to_output output_to_output output_to_clk output_to_clk2 output_to_input
-k6_frac_N10_mem32K_40nm.xml multiclock.blif 1.39742 0.545 0.790697 -1 2.15225 0.545 0.790697 -1 1.39742 -1 1.04641 -1 1.70501 -1 -1 -1 -1
+k6_frac_N10_mem32K_40nm.xml multiclock.blif 1.39742 0.545 0.790697 -1 2.15225 0.545 0.790697 -1 1.39742 -1 1.04641 -1 2.15225 -1 -1 -1 -1
