)]}'
{
  "id": "0e09f4092dbdfef9ab160a624493d4892570f3f5",
  "repo": "third_party/vtr-verilog-to-routing",
  "revision": "10967502edb0124a0d8f058fb42d1acde8a76d8b",
  "path": "vpr/src/base/clock_modeling.cpp"
}