.model top
.inputs bbtas_in_0_ bbtas_in_1_ clock
.outputs bbtas_out_1_ bbtas_out_0_
.latch    n_n16 n_n38 re clock 2
.latch    n_n17 n_n39 re clock 2
.latch    n_n18 n_n40 re clock 2
.names bbtas_in_1_ [14] bbtas_out_1_
11 1
.names bbtas_in_0_ [14] bbtas_out_0_
11 1
.names [25] [78] n_n16
1- 1
-1 1
.names [20] [79] n_n17
1- 1
-1 1
.names [11] [12] n_n18
1- 1
-1 1
.names bbtas_in_0_ bbtas_in_1_ [10]
1- 1
-1 1
.names n_n38 n_n39 [13]
11 1
.names n_n39 n_n40 [14]
01 1
.names n_n38 [23] [15]
1- 1
-1 1
.names n_n39 [10] [16]
01 1
10 1
.names n_n40 [18] [17]
1- 1
-1 1
.names [10] [17] [11]
11 1
.names [10] [13] [12]
01 1
.names n_n38 n_n39 [18]
01 1
.names [10] [15] [20]
11 1
.names [10] [14] [21]
01 1
.names n_n39 n_n40 [23]
11 1
.names [16] [77] [25]
11 1
.names [10] [14] [26]
01 1
.names [10] [13] [27]
11 1
.names n_n40 n_n38 [77]
00 1
.names [27] [26] [78]
1- 1
-1 1
.names [21] [13] [79]
1- 1
-1 1
.end