.model top
.inputs mc_in_2_ mc_in_0_ mc_in_1_ clock
.outputs mc_out_4_ mc_out_3_ mc_out_2_ mc_out_1_ mc_out_0_
.latch    n_n20 n_n33 re clock 2
.latch    n_n21 mc_out_3_ re clock 2
.names [17] [48] mc_out_4_
1- 1
-1 1
.names mc_out_3_ n_n33 mc_out_2_
01 1
.names mc_out_3_ mc_out_1_
0 1
.names mc_out_3_ n_n33 mc_out_0_
11 1
.names mc_out_4_ n_n33 n_n20
01 1
10 1
.names [12] [13] n_n21
1- 1
-1 1
.names mc_in_0_ n_n33 [11]
0- 1
-0 1
.names mc_out_3_ [11] [12]
11 1
.names mc_in_0_ mc_out_2_ [13]
11 1
.names n_n33 [46] [16]
01 1
.names n_n33 [47] [17]
01 1
.names mc_out_3_ mc_in_2_ [46]
10 1
.names mc_in_1_ mc_in_2_ [47]
11 1
.names [16] [11] [48]
1- 1
-0 1
.end