.model top
.inputs s27_in_2_ s27_in_1_ s27_in_3_ s27_in_0_ clock
.outputs s27_out
.latch    n_n17 n_n40 re clock 2
.latch    n_n18 n_n41 re clock 2
.latch    n_n19 n_n42 re clock 2
.names n_n41 n_n19 s27_out
1- 1
-0 1
.names s27_in_1_ n_n18 [11] n_n17
11- 1
-10 1
001 1
.names s27_in_3_ [10] [50] n_n18
11- 1
1-1 1
.names [10] [9] [50] n_n19
-1- 1
0-0 1
.names s27_in_2_ n_n40 n_n41 [11]
1-- 1
-01 1
-10 1
.names n_n40 n_n41 [10]
1- 1
-1 1
.names s27_in_3_ n_n42 [9]
01 1
.names s27_in_0_ s27_in_2_ [50]
0- 1
-1 1
.end