.model top
.inputs mc_in_2_ mc_in_0_ mc_in_1_ clock
.outputs mc_out_4_ mc_out_3_ mc_out_2_ mc_out_1_ mc_out_0_
.latch    n_n20 n_n33 re clock 2
.latch    n_n21 mc_out_3_ re clock 2
.names mc_in_2_ mc_in_1_ n_n33 [48] mc_out_4_
---1 1
110- 1
.names mc_out_3_ n_n33 mc_out_2_
01 1
.names mc_out_3_ mc_out_1_
0 1
.names mc_out_3_ n_n33 mc_out_0_
11 1
.names mc_in_2_ mc_in_1_ n_n33 [48] n_n20
--01 1
--10 1
110- 1
.names mc_in_0_ mc_out_3_ n_n33 n_n21
01- 1
-10 1
101 1
.names mc_in_2_ mc_in_0_ mc_out_3_ n_n33 [48]
-1-1 1
0-10 1
.end