tree 1d1291efb67698748b19a9eba9782ce7fa920ccd
parent 502be5a4c669e5b6083d1d3d75ea0b57d2e3ae5c
author kmurray <k.murray@utoronto.ca> 1572293876 -0400
committer kmurray <k.murray@utoronto.ca> 1572293876 -0400

vpr: Improve control over clock tracing

We now trace through black boxes only to input clock ports (instead of
all combinationally connected data ports). This allows users to specify
via the architecture file which pins are clock related.

For instance consider a clock buffer with an enable:

    .subckt clkbufce \
        in=clk3 \
        enable=clk3_enable \
        out=clk3_buf

Which would have a corresponding model:

    <model name="clkbufce">
      <input_ports>
        <port name="in" combinational_sink_ports="out" is_clock="1"/>
        <port name="enable" combinational_sink_ports="out"/>
      </input_ports>
      <output_ports>
        <port name="out"/>
      </output_ports>
    </model>

and pb_type:

    <pb_type name="clkbufce" blif_model="clkbufce" num_pb="1">
      <clock name="in" num_pins="1"/>
      <input name="enable" num_pins="1"/>
      <output name="out" num_pins="1"/>
      <delay_constant max="10e-12" in_port="clkbufce.in" out_port="clkbufce.out"/>
      <delay_constant max="5e-12" in_port="clkbufce.enable" out_port="clkbufce.out"/>
    </pb_type>

When tracing back the clock net 'clk3_buf', VPR will now look at the
upstream clock port ('in') and correctly identify the net 'clk3' as
being the same logical clock. Previously (when <clock>/is_clock were not
considered for this purpose) 'clk3_enable' would have also been (incorrectly)
detected as an upstream clock net.