<architecture>
  <models>
    <!-- LAB Primitives -->
    <model name="stratixiv_lcell_comb">
      <!-- Note that timing edges are derived from the 'specify' statements in
             the quartus device primitive verilog model (quartus/eda/sim_lib/stratixiv_atoms.v),
             which appear to be consistent with the Stratix IV Handbook.
             -->
      <input_ports>
        <port name="dataa" combinational_sink_ports="sumout combout cout shareout"/>
        <port name="datab" combinational_sink_ports="sumout combout cout shareout"/>
        <port name="datac" combinational_sink_ports="sumout combout cout shareout"/>
        <port name="datad" combinational_sink_ports="sumout combout cout shareout"/>
        <port name="datae" combinational_sink_ports="combout"/>
        <port name="dataf" combinational_sink_ports="sumout combout cout"/>
        <port name="datag" combinational_sink_ports="combout"/>
        <port name="cin" combinational_sink_ports="sumout cout"/>
        <port name="sharein" combinational_sink_ports="sumout cout"/>
      </input_ports>
      <output_ports>
        <port name="combout"/>
        <port name="sumout"/>
        <port name="cout"/>
        <port name="shareout"/>
      </output_ports>
    </model>
    <model name="dffeas">
      <input_ports>
        <port name="clk" is_clock="1"/>
        <port name="ena" clock="clk"/>
        <port name="prn" clock="clk"/>
        <port name="clrn" clock="clk"/>
        <port name="asdata" clock="clk"/>
        <port name="aload" clock="clk"/>
        <port name="sload" clock="clk"/>
        <port name="sclr" clock="clk"/>
        <port name="d" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="q" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mlab_cell">
      <input_ports>
        <port name="clk0" is_clock="1"/>
        <port name="ena0" clock="clk0"/>
        <port name="portaaddr" clock="clk0"/>
        <port name="portabyteenamasks" clock="clk0"/>
        <port name="portadatain" clock="clk0"/>
        <port name="portbaddr" clock="clk0"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout" clock="clk0"/>
      </output_ports>
    </model>
    <model name="stratixiv_mlab_cell.opmode{ROM}">
      <input_ports>
        <port name="clk0" is_clock="1"/>
        <port name="ena0" combinational_sink_ports="portbdataout"/>
        <port name="portaaddr" combinational_sink_ports="portbdataout"/>
        <port name="portabyteenamasks" combinational_sink_ports="portbdataout"/>
        <port name="portadatain" combinational_sink_ports="portbdataout"/>
        <port name="portbaddr" combinational_sink_ports="portbdataout"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout"/>
      </output_ports>
    </model>
    <!-- RAM (M9K, M144K) Primitives -->
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{10}.port_b_address_width{10}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{10}.port_b_address_width{10}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{9}.port_b_address_width{9}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{9}.port_b_address_width{9}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{8}.port_b_address_width{8}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{8}.port_b_address_width{8}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{13}.port_b_address_width{13}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{13}.port_b_address_width{13}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{12}.port_b_address_width{12}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{12}.port_b_address_width{12}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{11}.port_b_address_width{11}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{11}.port_b_address_width{11}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{7}.port_b_address_width{7}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{7}.port_b_address_width{7}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{6}.port_b_address_width{6}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{6}.port_b_address_width{6}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{5}.port_b_address_width{5}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{5}.port_b_address_width{5}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{4}.port_b_address_width{4}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{4}.port_b_address_width{4}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{3}.port_b_address_width{3}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{3}.port_b_address_width{3}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{2}.port_b_address_width{2}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{2}.port_b_address_width{2}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{1}.port_b_address_width{1}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{1}.port_b_address_width{1}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{0}.port_b_address_width{0}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{0}.port_b_address_width{0}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{10}.port_b_address_width{10}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{10}.port_b_address_width{10}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{9}.port_b_address_width{9}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{9}.port_b_address_width{9}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{13}.port_b_address_width{13}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{13}.port_b_address_width{13}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{12}.port_b_address_width{12}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{12}.port_b_address_width{12}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{11}.port_b_address_width{11}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{11}.port_b_address_width{11}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{8}.port_b_address_width{8}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{8}.port_b_address_width{8}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{7}.port_b_address_width{7}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{7}.port_b_address_width{7}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{6}.port_b_address_width{6}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{6}.port_b_address_width{6}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{5}.port_b_address_width{5}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{5}.port_b_address_width{5}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{4}.port_b_address_width{4}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{4}.port_b_address_width{4}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{3}.port_b_address_width{3}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{3}.port_b_address_width{3}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{2}.port_b_address_width{2}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{2}.port_b_address_width{2}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{1}.port_b_address_width{1}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{1}.port_b_address_width{1}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{0}.port_b_address_width{0}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{0}.port_b_address_width{0}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{10}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{10}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{9}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{9}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{8}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{8}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{13}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{13}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{12}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{12}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{11}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{11}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{7}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{7}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{6}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{6}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{5}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{5}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{4}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{4}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{3}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{3}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{2}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{2}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{1}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{1}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{0}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{0}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{10}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{10}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{9}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{9}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{8}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{8}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{13}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{13}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{12}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{12}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{11}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{11}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{7}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{7}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{6}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{6}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{5}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{5}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{4}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{4}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{3}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{3}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{2}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{2}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{1}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{1}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{0}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{0}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{reg}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{comb}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{14}.port_b_address_width{14}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{14}.port_b_address_width{14}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{14}.port_b_address_width{14}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
        <port name="portbdataout" clock="clk_portbout"/>
        <port name="eccstatus" clock="clk_portbout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{14}.port_b_address_width{14}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portbout"/>
        <port is_clock="1" name="clk_portbin"/>
        <port name="portbaddr" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbre" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="clr1" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbbyteenamasks" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbwe" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena2" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena3" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbaddrstall" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout portbdataout eccstatus"/>
        <port name="portbdatain" clock="clk_portbin" combinational_sink_ports="portadataout portbdataout eccstatus"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
        <port name="portbdataout"/>
        <port name="eccstatus"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{14}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{14}">
      <input_ports>
        <port name="portadatain" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portabyteenamasks" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
        <port name="portawe" clock="clk_portain" combinational_sink_ports="portadataout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{14}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout" clock="clk_portaout"/>
      </output_ports>
    </model>
    <model name="stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{14}">
      <input_ports>
        <port name="clr1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="clr0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portare" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena2" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena3" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena0" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="ena1" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddrstall" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port name="portaaddr" clock="clk_portain" combinational_sink_ports="portadataout"/>
        <port is_clock="1" name="clk_portain"/>
        <port is_clock="1" name="clk_portaout"/>
      </input_ports>
      <output_ports>
        <port name="portadataout"/>
      </output_ports>
    </model>
    <!-- DSP Primitives -->
    <model name="stratixiv_mac_mult.input_type{comb}">
      <input_ports>
        <port name="dataa" combinational_sink_ports="scanouta dataout"/>
        <port name="datab" combinational_sink_ports="dataout"/>
        <port name="signa" combinational_sink_ports="dataout"/>
        <port name="signb" combinational_sink_ports="dataout"/>
        <port name="ena" combinational_sink_ports="dataout"/>
        <port name="aclr" combinational_sink_ports="dataout"/>
        <port name="devclrn" combinational_sink_ports="dataout"/>
        <port name="devpor" combinational_sink_ports="dataout"/>
      </input_ports>
      <output_ports>
        <port name="scanouta"/>
        <port name="dataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_mult.input_type{reg}">
      <input_ports>
        <port name="dataa" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datab" clock="clk" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk" combinational_sink_ports="dataout"/>
        <port name="signb" clock="clk" combinational_sink_ports="dataout"/>
        <port name="ena" clock="clk" combinational_sink_ports="dataout"/>
        <port name="aclr" clock="clk" combinational_sink_ports="dataout"/>
        <port name="devclrn" clock="clk" combinational_sink_ports="dataout"/>
        <port name="devpor" clock="clk" combinational_sink_ports="dataout"/>
        <port name="clk" is_clock="1"/>
      </input_ports>
      <output_ports>
        <port name="scanouta" clock="clk"/>
        <port name="dataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{output_only}.input_type{comb}.output_type{comb}">
      <input_ports>
        <port name="dataa" combinational_sink_ports="dftout dataout"/>
        <port name="round" combinational_sink_ports="dftout dataout"/>
        <port name="saturate" combinational_sink_ports="dftout dataout"/>
        <port name="ena" combinational_sink_ports="dftout dataout"/>
        <port name="aclr" combinational_sink_ports="dftout"/>
        <port name="devclrn" combinational_sink_ports="dftout dataout"/>
        <port name="devpor" combinational_sink_ports="dftout dataout"/>
      </input_ports>
      <output_ports>
        <port name="dataout"/>
        <port name="dftout"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{output_only}.input_type{reg}.output_type{comb}">
      <input_ports>
        <port name="dataa" clock="clk" combinational_sink_ports="dataout"/>
        <port name="round" clock="clk"/>
        <port name="saturate" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="aclr" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{output_only}.input_type{comb}.output_type{reg}">
      <input_ports>
        <port name="dataa" combinational_sink_ports="dataout"/>
        <port name="round" clock="clk"/>
        <port name="saturate" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="aclr" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{output_only}.input_type{reg}.output_type{reg}">
      <input_ports>
        <port name="dataa" clock="clk" combinational_sink_ports="dataout"/>
        <port name="round" clock="clk"/>
        <port name="saturate" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="aclr" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{36_bit_multiply}.input_type{comb}.output_type{comb}">
      <input_ports>
        <port name="dataa" combinational_sink_ports="dftout dataout"/>
        <port name="datab" combinational_sink_ports="dftout dataout"/>
        <port name="datac" combinational_sink_ports="dftout dataout"/>
        <port name="datad" combinational_sink_ports="dftout dataout"/>
        <port name="signa" combinational_sink_ports="dftout dataout"/>
        <port name="signb" combinational_sink_ports="dftout dataout"/>
        <port name="ena" combinational_sink_ports="dftout dataout"/>
        <port name="aclr" combinational_sink_ports="dataout"/>
        <port name="devclrn" combinational_sink_ports="dftout dataout"/>
        <port name="devpor" combinational_sink_ports="dftout dataout"/>
      </input_ports>
      <output_ports>
        <port name="dataout"/>
        <port name="dftout"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{36_bit_multiply}.input_type{reg}.output_type{comb}">
      <input_ports>
        <port name="dataa" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datab" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datac" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datad" clock="clk" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk" combinational_sink_ports="dataout"/>
        <port name="signb" clock="clk" combinational_sink_ports="dataout"/>
        <port name="ena" clock="clk" combinational_sink_ports="dataout"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk" combinational_sink_ports="dataout"/>
        <port name="devpor" clock="clk" combinational_sink_ports="dataout"/>
      </input_ports>
      <output_ports>
        <port name="dataout"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{36_bit_multiply}.input_type{comb}.output_type{reg}">
      <input_ports>
        <port name="dataa" combinational_sink_ports="dataout"/>
        <port name="datab" combinational_sink_ports="dataout"/>
        <port name="datac" combinational_sink_ports="dataout"/>
        <port name="datad" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{36_bit_multiply}.input_type{reg}.output_type{reg}">
      <input_ports>
        <port name="dataa" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datab" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datac" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datad" clock="clk" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{one_level_adder}.input_type{comb}.output_type{comb}">
      <input_ports>
        <port name="dataa" combinational_sink_ports="dftout dataout"/>
        <port name="datab" combinational_sink_ports="dftout dataout"/>
        <port name="signa" combinational_sink_ports="dftout dataout"/>
        <port name="signb" combinational_sink_ports="dftout dataout"/>
        <port name="round" combinational_sink_ports="dftout dataout"/>
        <port name="saturate" combinational_sink_ports="dftout dataout"/>
        <port name="ena" combinational_sink_ports="dftout dataout"/>
        <port name="aclr" combinational_sink_ports="dataout"/>
        <port name="devclrn" combinational_sink_ports="dftout dataout"/>
        <port name="devpor" combinational_sink_ports="dftout dataout"/>
      </input_ports>
      <output_ports>
        <port name="dataout"/>
        <port name="dftout"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{one_level_adder}.input_type{reg}.output_type{comb}">
      <input_ports>
        <port name="dataa" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datab" clock="clk" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="round" clock="clk"/>
        <port name="saturate" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{one_level_adder}.input_type{comb}.output_type{reg}">
      <input_ports>
        <port name="dataa" combinational_sink_ports="dataout"/>
        <port name="datab" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="round" clock="clk"/>
        <port name="saturate" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{one_level_adder}.input_type{reg}.output_type{reg}">
      <input_ports>
        <port name="dataa" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datab" clock="clk" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="round" clock="clk"/>
        <port name="saturate" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{double}.input_type{comb}.output_type{comb}">
      <input_ports>
        <port name="dataa" combinational_sink_ports="dftout dataout"/>
        <port name="datab" combinational_sink_ports="dftout dataout"/>
        <port name="datac" combinational_sink_ports="dftout dataout"/>
        <port name="datad" combinational_sink_ports="dftout dataout"/>
        <port name="signa" combinational_sink_ports="dftout dataout"/>
        <port name="signb" combinational_sink_ports="dftout dataout"/>
        <port name="ena" combinational_sink_ports="dftout dataout"/>
        <port name="aclr" combinational_sink_ports="dataout"/>
        <port name="devclrn" combinational_sink_ports="dftout dataout"/>
        <port name="devpor" combinational_sink_ports="dftout dataout"/>
      </input_ports>
      <output_ports>
        <port name="dataout"/>
        <port name="dftout"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{double}.input_type{reg}.output_type{comb}">
      <input_ports>
        <port name="dataa" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datab" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datac" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datad" clock="clk" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{double}.input_type{comb}.output_type{reg}">
      <input_ports>
        <port name="dataa" combinational_sink_ports="dataout"/>
        <port name="datab" combinational_sink_ports="dataout"/>
        <port name="datac" combinational_sink_ports="dataout"/>
        <port name="datad" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{double}.input_type{reg}.output_type{reg}">
      <input_ports>
        <port name="dataa" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datab" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datac" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datad" clock="clk" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{two_level_adder}.input_type{comb}.output_type{comb}">
      <input_ports>
        <port name="dataa" combinational_sink_ports="dftout overflow dataout"/>
        <port name="datab" combinational_sink_ports="dftout overflow dataout"/>
        <port name="datac" combinational_sink_ports="dftout overflow dataout"/>
        <port name="datad" combinational_sink_ports="dftout overflow dataout"/>
        <port name="signa" combinational_sink_ports="dftout overflow dataout"/>
        <port name="signb" combinational_sink_ports="dftout overflow dataout"/>
        <port name="round" combinational_sink_ports="dftout overflow dataout"/>
        <port name="saturate" combinational_sink_ports="dftout overflow dataout"/>
        <port name="ena" combinational_sink_ports="dftout overflow dataout"/>
        <port name="aclr" combinational_sink_ports="dataout"/>
        <port name="devclrn" combinational_sink_ports="dftout overflow dataout"/>
        <port name="devpor" combinational_sink_ports="dftout overflow dataout"/>
      </input_ports>
      <output_ports>
        <port name="dataout"/>
        <port name="overflow"/>
        <port name="dftout"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{two_level_adder}.input_type{reg}.output_type{comb}">
      <input_ports>
        <port name="dataa" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datab" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datac" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datad" clock="clk" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="round" clock="clk"/>
        <port name="saturate" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout"/>
        <port name="overflow" clock="clk"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{two_level_adder}.input_type{comb}.output_type{reg}">
      <input_ports>
        <port name="dataa" combinational_sink_ports="dataout"/>
        <port name="datab" combinational_sink_ports="dataout"/>
        <port name="datac" combinational_sink_ports="dataout"/>
        <port name="datad" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="round" clock="clk"/>
        <port name="saturate" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
        <port name="overflow" clock="clk"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{two_level_adder}.input_type{reg}.output_type{reg}">
      <input_ports>
        <port name="dataa" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datab" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datac" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datad" clock="clk" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="round" clock="clk"/>
        <port name="saturate" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
        <port name="overflow" clock="clk"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{two_level_adder_chain_out}.input_type{comb}.output_type{comb}">
      <input_ports>
        <port name="dataa" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="datab" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="datac" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="datad" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="signa" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="signb" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="chainin" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="round" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="saturate" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="roundchainout" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="saturatechainout" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="zerochainout" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="ena" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="aclr" combinational_sink_ports="dataout"/>
        <port name="devclrn" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="devpor" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
      </input_ports>
      <output_ports>
        <port name="dataout"/>
        <port name="overflow"/>
        <port name="saturatechainoutoverflow"/>
        <port name="dftout"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{two_level_adder_chain_out}.input_type{reg}.output_type{comb}">
      <input_ports>
        <port name="dataa" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datab" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datac" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datad" clock="clk" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="chainin" clock="clk"/>
        <port name="round" clock="clk"/>
        <port name="saturate" clock="clk"/>
        <port name="roundchainout" clock="clk"/>
        <port name="saturatechainout" clock="clk"/>
        <port name="zerochainout" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout"/>
        <port name="overflow" clock="clk"/>
        <port name="saturatechainoutoverflow" clock="clk"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{two_level_adder_chain_out}.input_type{comb}.output_type{reg}">
      <input_ports>
        <port name="dataa" combinational_sink_ports="dataout"/>
        <port name="datab" combinational_sink_ports="dataout"/>
        <port name="datac" combinational_sink_ports="dataout"/>
        <port name="datad" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="chainin" clock="clk"/>
        <port name="round" clock="clk"/>
        <port name="saturate" clock="clk"/>
        <port name="roundchainout" clock="clk"/>
        <port name="saturatechainout" clock="clk"/>
        <port name="zerochainout" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
        <port name="overflow" clock="clk"/>
        <port name="saturatechainoutoverflow" clock="clk"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{two_level_adder_chain_out}.input_type{reg}.output_type{reg}">
      <input_ports>
        <port name="dataa" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datab" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datac" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datad" clock="clk" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="chainin" clock="clk"/>
        <port name="round" clock="clk"/>
        <port name="saturate" clock="clk"/>
        <port name="roundchainout" clock="clk"/>
        <port name="saturatechainout" clock="clk"/>
        <port name="zerochainout" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
        <port name="overflow" clock="clk"/>
        <port name="saturatechainoutoverflow" clock="clk"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{accumulator}.input_type{comb}.output_type{comb}">
      <input_ports>
        <port name="dataa" combinational_sink_ports="dftout overflow dataout"/>
        <port name="datab" combinational_sink_ports="dftout overflow dataout"/>
        <port name="datac" combinational_sink_ports="dftout overflow dataout"/>
        <port name="datad" combinational_sink_ports="dftout overflow dataout"/>
        <port name="signa" combinational_sink_ports="dftout overflow dataout"/>
        <port name="signb" combinational_sink_ports="dftout overflow dataout"/>
        <port name="round" combinational_sink_ports="dftout overflow dataout"/>
        <port name="saturate" combinational_sink_ports="dftout overflow dataout"/>
        <port name="zeroacc" combinational_sink_ports="dftout overflow dataout"/>
        <port name="ena" combinational_sink_ports="dftout overflow dataout"/>
        <port name="aclr" combinational_sink_ports="dataout"/>
        <port name="devclrn" combinational_sink_ports="dftout overflow dataout"/>
        <port name="devpor" combinational_sink_ports="dftout overflow dataout"/>
      </input_ports>
      <output_ports>
        <port name="dataout"/>
        <port name="overflow"/>
        <port name="dftout"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{accumulator}.input_type{reg}.output_type{comb}">
      <input_ports>
        <port name="dataa" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datab" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datac" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datad" clock="clk" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="round" clock="clk"/>
        <port name="saturate" clock="clk"/>
        <port name="zeroacc" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout"/>
        <port name="overflow" clock="clk"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{accumulator}.input_type{comb}.output_type{reg}">
      <input_ports>
        <port name="dataa" combinational_sink_ports="dataout"/>
        <port name="datab" combinational_sink_ports="dataout"/>
        <port name="datac" combinational_sink_ports="dataout"/>
        <port name="datad" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="round" clock="clk"/>
        <port name="saturate" clock="clk"/>
        <port name="zeroacc" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
        <port name="overflow" clock="clk"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{accumulator}.input_type{reg}.output_type{reg}">
      <input_ports>
        <port name="dataa" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datab" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datac" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datad" clock="clk" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="round" clock="clk"/>
        <port name="saturate" clock="clk"/>
        <port name="zeroacc" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
        <port name="overflow" clock="clk"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{accumulator_chain_out}.input_type{comb}.output_type{comb}">
      <input_ports>
        <port name="dataa" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="datab" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="datac" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="datad" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="signa" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="signb" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="chainin" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="round" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="saturate" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="zeroacc" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="roundchainout" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="saturatechainout" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="zerochainout" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="ena" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="aclr" combinational_sink_ports="dataout"/>
        <port name="devclrn" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
        <port name="devpor" combinational_sink_ports="dftout overflow dataout saturatechainoutoverflow"/>
      </input_ports>
      <output_ports>
        <port name="dataout"/>
        <port name="overflow"/>
        <port name="saturatechainoutoverflow"/>
        <port name="dftout"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{accumulator_chain_out}.input_type{reg}.output_type{comb}">
      <input_ports>
        <port name="dataa" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datab" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datac" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datad" clock="clk" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="chainin" clock="clk"/>
        <port name="round" clock="clk"/>
        <port name="saturate" clock="clk"/>
        <port name="zeroacc" clock="clk"/>
        <port name="roundchainout" clock="clk"/>
        <port name="saturatechainout" clock="clk"/>
        <port name="zerochainout" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout"/>
        <port name="overflow" clock="clk"/>
        <port name="saturatechainoutoverflow" clock="clk"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{accumulator_chain_out}.input_type{comb}.output_type{reg}">
      <input_ports>
        <port name="dataa" combinational_sink_ports="dataout"/>
        <port name="datab" combinational_sink_ports="dataout"/>
        <port name="datac" combinational_sink_ports="dataout"/>
        <port name="datad" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="chainin" clock="clk"/>
        <port name="round" clock="clk"/>
        <port name="saturate" clock="clk"/>
        <port name="zeroacc" clock="clk"/>
        <port name="roundchainout" clock="clk"/>
        <port name="saturatechainout" clock="clk"/>
        <port name="zerochainout" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
        <port name="overflow" clock="clk"/>
        <port name="saturatechainoutoverflow" clock="clk"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{accumulator_chain_out}.input_type{reg}.output_type{reg}">
      <input_ports>
        <port name="dataa" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datab" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datac" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datad" clock="clk" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="chainin" clock="clk"/>
        <port name="round" clock="clk"/>
        <port name="saturate" clock="clk"/>
        <port name="zeroacc" clock="clk"/>
        <port name="roundchainout" clock="clk"/>
        <port name="saturatechainout" clock="clk"/>
        <port name="zerochainout" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
        <port name="overflow" clock="clk"/>
        <port name="saturatechainoutoverflow" clock="clk"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{shift}.input_type{comb}.output_type{comb}">
      <input_ports>
        <port name="dataa" combinational_sink_ports="dftout dataout"/>
        <port name="datab" combinational_sink_ports="dftout dataout"/>
        <port name="datac" combinational_sink_ports="dftout dataout"/>
        <port name="datad" combinational_sink_ports="dftout dataout"/>
        <port name="signa" combinational_sink_ports="dftout dataout"/>
        <port name="signb" combinational_sink_ports="dftout dataout"/>
        <port name="rotate" combinational_sink_ports="dftout dataout"/>
        <port name="shiftright" combinational_sink_ports="dftout dataout"/>
        <port name="ena" combinational_sink_ports="dftout dataout"/>
        <port name="aclr" combinational_sink_ports="dataout"/>
        <port name="devclrn" combinational_sink_ports="dftout dataout"/>
        <port name="devpor" combinational_sink_ports="dftout dataout"/>
      </input_ports>
      <output_ports>
        <port name="dataout"/>
        <port name="dftout"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{shift}.input_type{reg}.output_type{comb}">
      <input_ports>
        <port name="dataa" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datab" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datac" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datad" clock="clk" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="rotate" clock="clk"/>
        <port name="shiftright" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{shift}.input_type{comb}.output_type{reg}">
      <input_ports>
        <port name="dataa" combinational_sink_ports="dataout"/>
        <port name="datab" combinational_sink_ports="dataout"/>
        <port name="datac" combinational_sink_ports="dataout"/>
        <port name="datad" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="rotate" clock="clk"/>
        <port name="shiftright" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{shift}.input_type{reg}.output_type{reg}">
      <input_ports>
        <port name="dataa" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datab" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datac" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datad" clock="clk" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="rotate" clock="clk"/>
        <port name="shiftright" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{loopback}.input_type{comb}.output_type{comb}">
      <input_ports>
        <port name="dataa" combinational_sink_ports="dftout dataout loopbackout"/>
        <port name="datab" combinational_sink_ports="dftout dataout loopbackout"/>
        <port name="signa" combinational_sink_ports="dftout dataout loopbackout"/>
        <port name="signb" combinational_sink_ports="dftout dataout loopbackout"/>
        <port name="round" combinational_sink_ports="dftout dataout loopbackout"/>
        <port name="saturate" combinational_sink_ports="dftout dataout loopbackout"/>
        <port name="zeroloopback" combinational_sink_ports="dftout dataout loopbackout"/>
        <port name="ena" combinational_sink_ports="dftout dataout loopbackout"/>
        <port name="aclr" combinational_sink_ports="dataout"/>
        <port name="devclrn" combinational_sink_ports="dftout dataout loopbackout"/>
        <port name="devpor" combinational_sink_ports="dftout dataout loopbackout"/>
      </input_ports>
      <output_ports>
        <port name="loopbackout"/>
        <port name="dataout"/>
        <port name="dftout"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{loopback}.input_type{reg}.output_type{comb}">
      <input_ports>
        <port name="dataa" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datab" clock="clk" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="round" clock="clk"/>
        <port name="saturate" clock="clk"/>
        <port name="zeroloopback" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="loopbackout" clock="clk"/>
        <port name="dataout"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{loopback}.input_type{comb}.output_type{reg}">
      <input_ports>
        <port name="dataa" combinational_sink_ports="dataout"/>
        <port name="datab" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="round" clock="clk"/>
        <port name="saturate" clock="clk"/>
        <port name="zeroloopback" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="loopbackout" clock="clk"/>
        <port name="dataout" clock="clk"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_mac_out.opmode{loopback}.input_type{reg}.output_type{reg}">
      <input_ports>
        <port name="dataa" clock="clk" combinational_sink_ports="dataout"/>
        <port name="datab" clock="clk" combinational_sink_ports="dataout"/>
        <port name="signa" clock="clk"/>
        <port name="signb" clock="clk"/>
        <port name="round" clock="clk"/>
        <port name="saturate" clock="clk"/>
        <port name="zeroloopback" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="aclr" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="loopbackout" clock="clk"/>
        <port name="dataout" clock="clk"/>
        <port name="dftout" clock="clk"/>
      </output_ports>
    </model>
    <!-- I/O and misc. primitives -->
    <model name="stratixiv_io_obuf">
      <input_ports>
        <port name="i" combinational_sink_ports="obar o"/>
        <port name="oe" combinational_sink_ports="obar o"/>
        <port name="dynamicterminationcontrol" combinational_sink_ports="obar o"/>
        <port name="seriesterminationcontrol" combinational_sink_ports="obar o"/>
        <port name="parallelterminationcontrol" combinational_sink_ports="obar o"/>
      </input_ports>
      <output_ports>
        <port name="o"/>
        <port name="obar"/>
      </output_ports>
    </model>
    <model name="stratixiv_io_ibuf">
      <input_ports>
        <port name="i" combinational_sink_ports="o"/>
        <port name="ibar" combinational_sink_ports="o"/>
      </input_ports>
      <output_ports>
        <port name="o"/>
      </output_ports>
    </model>
    <model name="stratixiv_ddio_out">
      <input_ports>
        <port name="datainlo" clock="clkhi"/>
        <port name="datainhi" clock="clkhi"/>
        <port name="clk" clock="clkhi"/>
        <port name="clkhi" is_clock="1"/>
        <port name="clklo" clock="clkhi"/>
        <port name="muxsel" clock="clkhi"/>
        <port name="ena" clock="clkhi"/>
        <port name="areset" clock="clkhi"/>
        <port name="sreset" clock="clkhi"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clkhi"/>
      </output_ports>
    </model>
    <model name="stratixiv_ddio_oe">
      <input_ports>
        <port name="oe" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="ena" clock="clk"/>
        <port name="areset" clock="clk"/>
        <port name="sreset" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_ddio_in">
      <input_ports>
        <port name="datain" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="clkn" clock="clk"/>
        <port name="ena" clock="clk"/>
        <port name="areset" clock="clk"/>
        <port name="sreset" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="regoutlo" clock="clk"/>
        <port name="regouthi" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_delay_chain">
      <input_ports>
        <port name="datain" combinational_sink_ports="dataout"/>
        <port name="delayctrlin" combinational_sink_ports="dataout"/>
        <port name="finedelayctrlin" combinational_sink_ports="dataout"/>
        <port name="devclrn" combinational_sink_ports="dataout"/>
        <port name="devpor" combinational_sink_ports="dataout"/>
      </input_ports>
      <output_ports>
        <port name="dataout"/>
      </output_ports>
    </model>
    <model name="stratixiv_dll">
      <input_ports>
        <port name="clk" is_clock="1"/>
        <port name="aload" clock="clk"/>
        <port name="upndnin" clock="clk"/>
        <port name="upndninclkena" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="offsetdelayctrlout" clock="clk"/>
        <port name="offsetdelayctrlclkout" clock="clk"/>
        <port name="delayctrlout" clock="clk"/>
        <port name="dqsupdate" clock="clk"/>
        <port name="upndnout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_dqs_config">
      <input_ports>
        <port name="datain" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="ena" clock="clk"/>
        <port name="update" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dqsbusoutdelaysetting" clock="clk"/>
        <port name="dqsinputphasesetting" clock="clk"/>
        <port name="dqsenablectrlphasesetting" clock="clk"/>
        <port name="dqsoutputphasesetting" clock="clk"/>
        <port name="dqoutputphasesetting" clock="clk"/>
        <port name="resyncinputphasesetting" clock="clk"/>
        <port name="dividerphasesetting" clock="clk"/>
        <port name="enaoctcycledelaysetting" clock="clk"/>
        <port name="enainputcycledelaysetting" clock="clk"/>
        <port name="enaoutputcycledelaysetting" clock="clk"/>
        <port name="dqsenabledelaysetting" clock="clk"/>
        <port name="octdelaysetting1" clock="clk"/>
        <port name="octdelaysetting2" clock="clk"/>
        <port name="enadataoutbypass" clock="clk"/>
        <port name="enadqsenablephasetransferreg" clock="clk"/>
        <port name="enaoctphasetransferreg" clock="clk"/>
        <port name="enaoutputphasetransferreg" clock="clk"/>
        <port name="enainputphasetransferreg" clock="clk"/>
        <port name="resyncinputphaseinvert" clock="clk"/>
        <port name="dqsenablectrlphaseinvert" clock="clk"/>
        <port name="dqoutputphaseinvert" clock="clk"/>
        <port name="dqsoutputphaseinvert" clock="clk"/>
        <port name="dqsbusoutfinedelaysetting" clock="clk"/>
        <port name="dqsenablefinedelaysetting" clock="clk"/>
        <port name="dataout" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_dqs_delay_chain">
      <input_ports>
        <port name="dqsin" combinational_sink_ports="dffin dqsbusout"/>
        <port name="delayctrlin" combinational_sink_ports="dffin dqsbusout"/>
        <port name="offsetctrlin" combinational_sink_ports="dffin dqsbusout"/>
        <port name="dqsupdateen" combinational_sink_ports="dffin dqsbusout"/>
        <port name="phasectrlin" combinational_sink_ports="dffin dqsbusout"/>
        <port name="devclrn" combinational_sink_ports="dffin dqsbusout"/>
        <port name="devpor" combinational_sink_ports="dffin dqsbusout"/>
      </input_ports>
      <output_ports>
        <port name="dqsbusout"/>
        <port name="dffin"/>
      </output_ports>
    </model>
    <model name="stratixiv_dqs_enable">
      <input_ports>
        <port name="dqsin" combinational_sink_ports="dqsbusout"/>
        <port name="dqsenable" combinational_sink_ports="dqsbusout"/>
        <port name="devclrn" combinational_sink_ports="dqsbusout"/>
        <port name="devpor" combinational_sink_ports="dqsbusout"/>
      </input_ports>
      <output_ports>
        <port name="dqsbusout"/>
      </output_ports>
    </model>
    <model name="stratixiv_dqs_enable_ctrl">
      <input_ports>
        <port name="dqsenablein" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="delayctrlin" clock="clk"/>
        <port name="phasectrlin" clock="clk"/>
        <port name="enaphasetransferreg" clock="clk"/>
        <port name="phaseinvertctrl" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dqsenableout" clock="clk"/>
        <port name="dffin" clock="clk"/>
        <port name="dffextenddqsenable" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_io_config">
      <input_ports>
        <port name="datain" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="ena" clock="clk"/>
        <port name="update" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="padtoinputregisterdelaysetting" clock="clk"/>
        <port name="outputdelaysetting1" clock="clk"/>
        <port name="outputdelaysetting2" clock="clk"/>
        <port name="dataout" clock="clk"/>
        <port name="dutycycledelaymode" clock="clk"/>
        <port name="dutycycledelaysettings" clock="clk"/>
        <port name="outputfinedelaysetting1" clock="clk"/>
        <port name="outputfinedelaysetting2" clock="clk"/>
        <port name="outputonlydelaysetting2" clock="clk"/>
        <port name="outputonlyfinedelaysetting2" clock="clk"/>
        <port name="padtoinputregisterfinedelaysetting" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_pseudo_diff_out">
      <input_ports>
        <port name="i" combinational_sink_ports="obar o"/>
      </input_ports>
      <output_ports>
        <port name="o"/>
        <port name="obar"/>
      </output_ports>
    </model>
    <model name="stratixiv_termination">
      <input_ports>
        <port name="otherserializerenable" combinational_sink_ports="terminationcontrolprobe incrup scanout incrdn terminationcontrol serializerenableout shiftregisterprobe"/>
        <port name="rdn" combinational_sink_ports="terminationcontrolprobe incrup scanout incrdn terminationcontrol serializerenableout shiftregisterprobe"/>
        <port name="rup" combinational_sink_ports="terminationcontrolprobe incrup scanout incrdn terminationcontrol serializerenableout shiftregisterprobe"/>
        <port name="scanen" combinational_sink_ports="terminationcontrolprobe incrup scanout incrdn terminationcontrol serializerenableout shiftregisterprobe"/>
        <port name="scanin" combinational_sink_ports="terminationcontrolprobe incrup scanout incrdn terminationcontrol serializerenableout shiftregisterprobe"/>
        <port name="serializerenable" combinational_sink_ports="terminationcontrolprobe incrup scanout incrdn terminationcontrol serializerenableout shiftregisterprobe"/>
        <port name="terminationclear" combinational_sink_ports="terminationcontrolprobe incrup scanout incrdn terminationcontrol serializerenableout shiftregisterprobe"/>
        <port name="terminationclock" combinational_sink_ports="terminationcontrolprobe incrup scanout incrdn terminationcontrol serializerenableout shiftregisterprobe"/>
        <port name="terminationcontrolin" combinational_sink_ports="terminationcontrolprobe incrup scanout incrdn terminationcontrol serializerenableout shiftregisterprobe"/>
        <port name="terminationenable" combinational_sink_ports="terminationcontrolprobe incrup scanout incrdn terminationcontrol serializerenableout shiftregisterprobe"/>
        <port name="devpor" combinational_sink_ports="terminationcontrolprobe incrup scanout incrdn terminationcontrol serializerenableout shiftregisterprobe"/>
        <port name="devclrn" combinational_sink_ports="terminationcontrolprobe incrup scanout incrdn terminationcontrol serializerenableout shiftregisterprobe"/>
      </input_ports>
      <output_ports>
        <port name="incrdn"/>
        <port name="incrup"/>
        <port name="scanout"/>
        <port name="serializerenableout"/>
        <port name="shiftregisterprobe"/>
        <port name="terminationcontrol"/>
        <port name="terminationcontrolprobe"/>
      </output_ports>
    </model>
    <model name="stratixiv_termination_logic">
      <input_ports>
        <port name="serialloadenable" combinational_sink_ports="parallelterminationcontrol seriesterminationcontrol"/>
        <port name="terminationclock" combinational_sink_ports="parallelterminationcontrol seriesterminationcontrol"/>
        <port name="parallelloadenable" combinational_sink_ports="parallelterminationcontrol seriesterminationcontrol"/>
        <port name="terminationdata" combinational_sink_ports="parallelterminationcontrol seriesterminationcontrol"/>
        <port name="devpor" combinational_sink_ports="parallelterminationcontrol seriesterminationcontrol"/>
        <port name="devclrn" combinational_sink_ports="parallelterminationcontrol seriesterminationcontrol"/>
      </input_ports>
      <output_ports>
        <port name="seriesterminationcontrol"/>
        <port name="parallelterminationcontrol"/>
      </output_ports>
    </model>
    <model name="stratixiv_input_phase_alignment">
      <input_ports>
        <port name="datain" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="delayctrlin" clock="clk"/>
        <port name="phasectrlin" clock="clk"/>
        <port name="areset" clock="clk"/>
        <port name="enainputcycledelay" clock="clk"/>
        <port name="enaphasetransferreg" clock="clk"/>
        <port name="phaseinvertctrl" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
        <port name="dffin" clock="clk"/>
        <port name="dff1t" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_output_phase_alignment">
      <input_ports>
        <port name="datain" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="delayctrlin" clock="clk"/>
        <port name="phasectrlin" clock="clk"/>
        <port name="areset" clock="clk"/>
        <port name="enaoutputcycledelay" clock="clk"/>
        <port name="enaphasetransferreg" clock="clk"/>
        <port name="phaseinvertctrl" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
        <port name="dffin" clock="clk"/>
        <port name="dff1t" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_output_phase_alignment.opmode{ddio_out}">
      <input_ports>
        <port name="datain" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="delayctrlin" clock="clk"/>
        <port name="phasectrlin" clock="clk"/>
        <port name="areset" clock="clk"/>
        <port name="enaoutputcycledelay" clock="clk"/>
        <port name="enaphasetransferreg" clock="clk"/>
        <port name="phaseinvertctrl" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
        <port name="dffin" clock="clk"/>
        <port name="dff1t" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_output_phase_alignment.opmode{ddio_in}">
      <input_ports>
        <port name="datain" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="delayctrlin" clock="clk"/>
        <port name="phasectrlin" clock="clk"/>
        <port name="areset" clock="clk"/>
        <port name="enaoutputcycledelay" clock="clk"/>
        <port name="enaphasetransferreg" clock="clk"/>
        <port name="phaseinvertctrl" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
        <port name="dffin" clock="clk"/>
        <port name="dff1t" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_output_phase_alignment.opmode{oe}">
      <input_ports>
        <port name="datain" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="delayctrlin" clock="clk"/>
        <port name="phasectrlin" clock="clk"/>
        <port name="areset" clock="clk"/>
        <port name="enaoutputcycledelay" clock="clk"/>
        <port name="enaphasetransferreg" clock="clk"/>
        <port name="phaseinvertctrl" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
        <port name="dffin" clock="clk"/>
        <port name="dff1t" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_output_phase_alignment.opmode{rtena}">
      <input_ports>
        <port name="datain" clock="clk"/>
        <port name="clk" is_clock="1"/>
        <port name="delayctrlin" clock="clk"/>
        <port name="phasectrlin" clock="clk"/>
        <port name="areset" clock="clk"/>
        <port name="enaoutputcycledelay" clock="clk"/>
        <port name="enaphasetransferreg" clock="clk"/>
        <port name="phaseinvertctrl" clock="clk"/>
        <port name="devclrn" clock="clk"/>
        <port name="devpor" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="dataout" clock="clk"/>
        <port name="dffin" clock="clk"/>
        <port name="dff1t" clock="clk"/>
      </output_ports>
    </model>
    <model name="stratixiv_tsdblock">
      <input_ports>
        <port name="clk" is_clock="1"/>
        <port name="ce" clock="clk"/>
        <port name="clr" clock="clk"/>
        <port name="fdbkctrlfromcore" clock="clk"/>
        <port name="compouttest" clock="clk"/>
        <port name="offset" clock="clk"/>
        <port name="testin" clock="clk"/>
      </input_ports>
      <output_ports>
        <port name="tsdcaldone" clock="clk"/>
        <port name="tsdcompout" clock="clk"/>
        <port name="tsdcalo" clock="clk"/>
        <port name="offsettout" clock="clk"/>
      </output_ports>
    </model>
    <!-- PLL primitives -->
    <model name="stratixiv_pll">
      <input_ports>
        <port name="areset" clock="inclk"/>
        <port name="clkswitch" clock="inclk"/>
        <port name="configupdate" clock="inclk"/>
        <port name="fbin" clock="inclk"/>
        <port name="inclk" is_clock="1"/>
        <port name="pfdena" clock="inclk"/>
        <port name="phasecounterselect" clock="inclk"/>
        <port name="phasestep" clock="inclk"/>
        <port name="phaseupdown" clock="inclk"/>
        <port name="scanclk" clock="inclk"/>
        <port name="scanclkena" clock="inclk"/>
        <port name="scandata" clock="inclk"/>
      </input_ports>
      <output_ports>
        <port name="activeclock" clock="inclk"/>
        <port name="clk" is_clock="1"/>
        <port name="clkbad" clock="inclk"/>
        <port name="fbout" clock="inclk"/>
        <port name="locked" clock="inclk"/>
        <port name="phasedone" clock="inclk"/>
        <port name="scandataout" clock="inclk"/>
        <port name="scandone" clock="inclk"/>
        <port name="vcooverrange" clock="inclk"/>
        <port name="vcounderrange" clock="inclk"/>
      </output_ports>
    </model>
    <model name="stratixiv_pll.opmode{normal}">
      <input_ports>
        <port name="areset" clock="inclk"/>
        <port name="clkswitch" clock="inclk"/>
        <port name="configupdate" clock="inclk"/>
        <port name="fbin" clock="inclk"/>
        <port name="inclk" is_clock="1"/>
        <port name="pfdena" clock="inclk"/>
        <port name="phasecounterselect" clock="inclk"/>
        <port name="phasestep" clock="inclk"/>
        <port name="phaseupdown" clock="inclk"/>
        <port name="scanclk" clock="inclk"/>
        <port name="scanclkena" clock="inclk"/>
        <port name="scandata" clock="inclk"/>
      </input_ports>
      <output_ports>
        <port name="activeclock" clock="inclk"/>
        <port name="clk" is_clock="1"/>
        <port name="clkbad" clock="inclk"/>
        <port name="fbout" clock="inclk"/>
        <port name="locked" clock="inclk"/>
        <port name="phasedone" clock="inclk"/>
        <port name="scandataout" clock="inclk"/>
        <port name="scandone" clock="inclk"/>
        <port name="vcooverrange" clock="inclk"/>
        <port name="vcounderrange" clock="inclk"/>
      </output_ports>
    </model>
    <model name="stratixiv_pll.opmode{no_compensation}">
      <input_ports>
        <port name="areset" clock="inclk"/>
        <port name="clkswitch" clock="inclk"/>
        <port name="configupdate" clock="inclk"/>
        <port name="fbin" clock="inclk"/>
        <port name="inclk" is_clock="1"/>
        <port name="pfdena" clock="inclk"/>
        <port name="phasecounterselect" clock="inclk"/>
        <port name="phasestep" clock="inclk"/>
        <port name="phaseupdown" clock="inclk"/>
        <port name="scanclk" clock="inclk"/>
        <port name="scanclkena" clock="inclk"/>
        <port name="scandata" clock="inclk"/>
      </input_ports>
      <output_ports>
        <port name="activeclock" clock="inclk"/>
        <port name="clk" is_clock="1"/>
        <port name="clkbad" clock="inclk"/>
        <port name="fbout" clock="inclk"/>
        <port name="locked" clock="inclk"/>
        <port name="phasedone" clock="inclk"/>
        <port name="scandataout" clock="inclk"/>
        <port name="scandone" clock="inclk"/>
        <port name="vcooverrange" clock="inclk"/>
        <port name="vcounderrange" clock="inclk"/>
      </output_ports>
    </model>
  </models>
  <tiles>
    <tile capacity="2" name="io">
      <equivalent_sites>
        <site pb_type="io"/>
      </equivalent_sites>
      <input name="core_in" num_pins="50" equivalent="none"/>
      <output name="core_out" num_pins="40" equivalent="none"/>
      <clock name="clk" num_pins="5"/>
      <fc in_type="frac" in_val="0.0275" out_type="frac" out_val="0.0375"/>
      <pinlocations pattern="custom">
        <!-- In Stratix IV the IO pins connect to the adjacent vertical and one 
             horizontal channel. However, since we use a single IO primitive we
             need to specify pin locations which work for all locations (e.g. top,
             bottom, left, right edges of the device). As a result we ensure the 
             pin setup is symmetric on all sides, with half of the pins connecting
             to each side of the IO block. This means that each pin is accessible
             from one vertical and one horizontal channel. Like the LAB below the
             Fc values have been adjusted to account for this. -->
        <loc side="left">  io.core_in[0:24]  io.core_out[0:19]  io.clk[0:2]</loc>
        <loc side="right"> io.core_in[24:49] io.core_out[20:39] io.clk[3:4]</loc>
        <loc side="top">   io.core_in[0:24]  io.core_out[0:19]  io.clk[0:2]</loc>
        <loc side="bottom">io.core_in[24:49] io.core_out[20:39] io.clk[3:4]</loc>
      </pinlocations>
    </tile>
    <tile height="1" name="PLL">
      <equivalent_sites>
        <site pb_type="PLL"/>
      </equivalent_sites>
      <input name="in_signal" num_pins="14"/>
      <clock name="in_clock" num_pins="2"/>
      <output name="out_clock" num_pins="10"/>
      <output name="out_signal" num_pins="10"/>
      <fc in_type="frac" in_val="0.055" out_type="frac" out_val="0.075"/>
      <pinlocations pattern="custom">
        <loc side="left">PLL.in_signal PLL.in_clock PLL.out_clock PLL.out_signal</loc>
        <loc side="right">PLL.in_signal PLL.in_clock PLL.out_clock PLL.out_signal</loc>
        <loc side="top">PLL.in_signal PLL.in_clock PLL.out_clock PLL.out_signal</loc>
        <loc side="bottom">PLL.in_signal PLL.in_clock PLL.out_clock PLL.out_signal</loc>
      </pinlocations>
    </tile>
    <tile name="LAB">
      <equivalent_sites>
        <site pb_type="LAB"/>
      </equivalent_sites>
      <input name="data_in" num_pins="80" equivalent="full"/>
      <input name="control_in" num_pins="7" equivalent="full"/>
      <input name="cin" num_pins="1" equivalent="none"/>
      <input name="sharein" num_pins="1" equivalent="none"/>
      <output name="data_out" num_pins="40" equivalent="instance"/>
      <output name="cout" num_pins="1" equivalent="none"/>
      <output name="shareout" num_pins="1" equivalent="none"/>
      <clock name="clk" num_pins="2"/>
      <fc in_type="frac" in_val="0.0275" out_type="frac" out_val="0.0375">
        <!-- Based on mux size info Startix IV has approximately the following effective Fc values:
                   Fc_in: 0.055
                   Fc_out: 0.075

               However, we allow half the pins to connect to the left side, the other half to the right side
               and all pins to connect to the top side of the LAB (3-sided architecture).

               As a result we divide the effective Fc values by 2 (since each pin can connect to two sides)
               to keep roughly the same number of switches, yielding:

                    Fc_in: 0.0275
                    Fc_out: 0.0375
               -->
        <!--Chains do not connect to general global routing-->
        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
        <!--Note: We do not list the LAB Share chain ports as having zero fc. 
              VPR uses this (along with a pack pattern and direct link) to identify 
              carry chain like structures which must be treated as placement macros.  

              However VPR currently does not support multiple chains/placement 
              macros per primitive. We DO hook-up the share ports with directlink
              but do NOT set fc to zero to avoid this issue. -->
      </fc>
      <pinlocations pattern="custom">
        <!-- Stratix IV is a 3 sided architecture, the LABs can connect to routing on their 
               left, top, and right.  To model this we spread the various ports around the three sides.

               The exceptions to the above are the LAB chain ports, which propogate downward between blocks.

               We model that half the pins can connect to each vertical channel (left/right),
               and all can connect to the horizontal channel (top). This models the fact that 
               each block pin can connect to some Vertical and some Horizontal wires in Stratix IV.
               Note that Fc_in/Fc_out have been scaled to account for this.
             -->
        <loc side="left">  LAB.data_in[0:39]  LAB.control_in[0:3] LAB.data_out[0:19]  LAB.clk[0]</loc>
        <loc side="right"> LAB.data_in[40:79] LAB.control_in[4:6] LAB.data_out[20:39] LAB.clk[1]</loc>
        <loc side="top">   LAB.data_in        LAB.control_in      LAB.data_out        LAB.clk    LAB.cin LAB.sharein</loc>
        <loc side="bottom">LAB.cout LAB.shareout</loc>
      </pinlocations>
    </tile>
    <tile name="DSP" height="4">
      <equivalent_sites>
        <site pb_type="DSP"/>
      </equivalent_sites>
      <input name="data_in" num_pins="288"/>
      <input name="chain_in" num_pins="44"/>
      <input name="control_in" num_pins="21"/>
      <input name="scan_a_in" num_pins="18"/>
      <clock name="clk" num_pins="4"/>
      <output name="data_out_top" num_pins="72"/>
      <output name="data_out_bot" num_pins="72"/>
      <output name="chain_out" num_pins="44"/>
      <output name="scan_a_out" num_pins="18"/>
      <output name="signal_out" num_pins="6"/>
      <fc in_type="frac" in_val="0.0275" out_type="frac" out_val="0.0375">
        <!-- Based on mux size info Startix IV has approximately the following effective Fc values:
                   Fc_in: 0.055
                   Fc_out: 0.075

               However, we allow half the pins to connect to the left side, the other half to the right side;
               and one quarter of pins to connect to the internal and top sides of the DSP (3-sided architecture).

               As a result we divide the effective Fc values by 2 (since each pin can connect to two sides)
               to keep roughly the same number of switches, yielding:

                    Fc_in: 0.0275
                    Fc_out: 0.0375
               -->
      </fc>
      <pinlocations pattern="custom">
        <!-- Stratix IV is a 3 sided architecture, each 'block' can connect to routing on their 
               left, top, and right.  To model this we spread the various ports around the three sides.
               The exceptions to the above are the chain ports, which propogate downward between blocks.

               Since the DSP block has height > 1, we split the pins accordingly and spread the pins around
               the sides and 'top' edges of each grid location within the block.

               More specifically, the DSP has 4 left sides, 4 right sides, and 4 top sides where pins can
               connect. Since the DSP actually consists of 2-halves we place the pins for each half at the 
               appropriate y-offsets.

               This means for instance that the top-half input pins (DSP.data_in[143:0]) are connected with
               1/4 of them on each left/right side at y-offsets 2 and 3, and 1/2 at each top side at 
               y-offsets 2 and 3. With the exception that the very top edge ('top' yoffset=3) has fewer pins
               (to account for the chain_in and scan_a_in connections) in order to keep a unifrom pin density
               per side.

               This models the fact that each block pin can connect to some Vertical and some Horizontal 
               wires in Stratix IV. Note that Fc_in/Fc_out have been scaled to account for this.
             -->
        <!-- The 'top' half of the DSP has pins connected at yoffsets 2 and 3 -->
        <!-- 
            In total there are:
                data_in     : 288
                chain_in    :  44
                control_in  :  21
                scan_a_in   :  18
                clk         :   4
                data_out_top:  72
                data_out_bot:  72
                signal_out  :   6
                ==================
                TOTAL       : 525 general data pins

            Spread accross 4+4+4 = 12 sides this corresponds to:

                525/12 = ~44 pins per side

            We generally aim to distribute the pins evenly accross the sides to avoid
            routing hot-spots.
        -->
        <!-- The 'top' half of the DSP has pins connected at yoffsets 2 and 3 -->
        <loc yoffset="3" side="left">DSP.data_in[35:0]    DSP.control_in[2:0] DSP.scan_a_in[1:0] DSP.clk[0] DSP.data_out_top[17:0]  DSP.scan_a_out[1:0]                     </loc>
        <loc yoffset="2" side="left">DSP.data_in[71:36]   DSP.control_in[4:3] DSP.scan_a_in[4:2]            DSP.data_out_top[35:18] DSP.scan_a_out[3:2] DSP.signal_out[0:0] </loc>
        <loc yoffset="3" side="right">DSP.data_in[107:72]  DSP.control_in[6:5] DSP.scan_a_in[6:5] DSP.clk[1] DSP.data_out_top[53:36] DSP.scan_a_out[5:4] DSP.signal_out[1:1] </loc>
        <loc yoffset="2" side="right">DSP.data_in[144:108] DSP.control_in[8:6] DSP.scan_a_in[8:7]            DSP.data_out_top[71:54] DSP.scan_a_out[7:6] DSP.signal_out[2:2] </loc>
        <loc yoffset="3" side="top">DSP.data_in[143:72]  DSP.control_in[3:0] DSP.scan_a_in[3:0] DSP.clk[0] DSP.data_out_top[35:0]  DSP.scan_a_out[3:0] DSP.signal_out[0:0] DSP.chain_in</loc>
        <loc yoffset="2" side="top">DSP.data_in[71:0]    DSP.control_in[8:4] DSP.scan_a_in[8:4] DSP.clk[1] DSP.data_out_top[71:36] DSP.scan_a_out[9:4] DSP.signal_out[2:1] </loc>
        <loc yoffset="3" side="bottom"/>
        <loc yoffset="2" side="bottom"/>
        <!-- The 'bottom' half of the DSP has pins connected at yoffsets 0 and 1 -->
        <loc yoffset="1" side="left">DSP.data_in[179:145] DSP.control_in[11:9]  DSP.scan_a_in[10:9]  DSP.clk[2] DSP.data_out_bot[17:0]  DSP.scan_a_out[9:8]                      </loc>
        <loc yoffset="0" side="left">DSP.data_in[215:180] DSP.control_in[13:12] DSP.scan_a_in[12:11]            DSP.data_out_bot[35:18] DSP.scan_a_out[11:10] DSP.signal_out[3:3]</loc>
        <loc yoffset="1" side="right">DSP.data_in[251:216] DSP.control_in[15:14] DSP.scan_a_in[14:13]            DSP.data_out_bot[53:36] DSP.scan_a_out[13:12] DSP.signal_out[4:4]</loc>
        <loc yoffset="0" side="right">DSP.data_in[287:252] DSP.control_in[20:16] DSP.scan_a_in[17:15] DSP.clk[3] DSP.data_out_bot[71:54] DSP.scan_a_out[15:14] DSP.signal_out[5:5]</loc>
        <loc yoffset="1" side="top">DSP.data_in[287:215] DSP.control_in[13:9]  DSP.scan_a_in[13:9]  DSP.clk[2] DSP.data_out_bot[35:0]  DSP.scan_a_out[12:10] DSP.signal_out[3:3]</loc>
        <loc yoffset="0" side="top">DSP.data_in[214:144] DSP.control_in[20:16] DSP.scan_a_in[17:14] DSP.clk[3] DSP.data_out_bot[71:36] DSP.scan_a_out[17:13] DSP.signal_out[5:4]</loc>
        <loc yoffset="1" side="bottom"/>
        <loc yoffset="0" side="bottom">DSP.chain_out</loc>
      </pinlocations>
    </tile>
    <tile height="1" name="M9K">
      <equivalent_sites>
        <site pb_type="M9K"/>
      </equivalent_sites>
      <input name="data_addr_control_in" num_pins="104"/>
      <output name="data_out" num_pins="36"/>
      <output name="control_out" num_pins="3"/>
      <clock name="clk_in" num_pins="2"/>
      <fc in_type="frac" in_val="0.0275" out_type="frac" out_val="0.0375">
        <!-- Based on mux size info Startix IV has approximately the following effective Fc values:
                   Fc_in: 0.055
                   Fc_out: 0.075

               However, we allow half the pins to connect to the left side, the other half to the right side
               and all pins to connect to the top side of the M9K (3-sided architecture).

               As a result we divide the effective Fc values by 2 (since each pin can connect to two sides)
               to keep roughly the same number of switches, yielding:

                    Fc_in: 0.0275
                    Fc_out: 0.0375
               -->
      </fc>
      <pinlocations pattern="custom">
        <!-- Stratix IV is a 3 sided architecture, the blocks can connect to routing on their 
               left, top, and right.  To model this we spread the various ports around the three sides.

               We model that half the pins can connect to each vertical channel (left/right),
               and all can connect to the horizontal channel (top). This models the fact that 
               each block pin can connect to some Vertical and some Horizontal wires in Stratix IV.
               Note that Fc_in/Fc_out have been scaled to account for this.
             -->
        <loc side="left">M9K.data_addr_control_in[51:0]   M9K.data_out[17:0]  M9K.control_out[1:0] M9K.clk_in[0]</loc>
        <loc side="right">M9K.data_addr_control_in[103:52] M9K.data_out[35:18] M9K.control_out[2:2] M9K.clk_in[1]</loc>
        <loc side="top">M9K.data_addr_control_in         M9K.data_out        M9K.control_out      M9K.clk_in   </loc>
        <loc side="bottom"/>
      </pinlocations>
    </tile>
    <tile height="8" name="M144K">
      <equivalent_sites>
        <site pb_type="M144K"/>
      </equivalent_sites>
      <input name="data_addr_control_in" num_pins="416"/>
      <output name="data_out" num_pins="120"/>
      <output name="control_out" num_pins="3"/>
      <clock name="clk_in" num_pins="2"/>
      <fc in_type="frac" in_val="0.0275" out_type="frac" out_val="0.0375">
        <!-- Based on mux size info Startix IV has approximately the following effective Fc values:
                   Fc_in: 0.055
                   Fc_out: 0.075

               However, we allow half the pins to connect to the left side, the other half to the right side
               and all pins to connect to the top side of the LAB (3-sided architecture).

               As a result we divide the effective Fc values by 2 (since each pin can connect to two sides)
               to keep roughly the same number of switches, yielding:

                    Fc_in: 0.0275
                    Fc_out: 0.0375
               -->
      </fc>
      <pinlocations pattern="custom">
        <!-- Stratix IV is a 3 sided architecture, the blocks can connect to routing on their 
               left, top, and right.  To model this we spread the various ports around the three sides.

               We model that half the pins can connect to each adjacent vertical channel (left/right),
               and all can connect to the horizontal channels (tops). This models the fact that 
               each block pin can connect to some Vertical and some Horizontal wires in Stratix IV.
               Note that Fc_in/Fc_out have been scaled to account for this.
             -->
        <loc yoffset="7" side="left">M144K.data_addr_control_in[24:0]    M144K.data_out[7:0]                                     </loc>
        <loc yoffset="6" side="left">M144K.data_addr_control_in[50:25]   M144K.data_out[15:8]                                    </loc>
        <loc yoffset="5" side="left">M144K.data_addr_control_in[76:51]   M144K.data_out[22:16]                                   </loc>
        <loc yoffset="4" side="left">M144K.data_addr_control_in[102:77]  M144K.data_out[29:23]                                   </loc>
        <loc yoffset="3" side="left">M144K.data_addr_control_in[128:103] M144K.data_out[36:30]   M144K.control_out[0] M144K.clk_in[0]</loc>
        <loc yoffset="2" side="left">M144K.data_addr_control_in[154:129] M144K.data_out[43:37]   M144K.control_out[1]              </loc>
        <loc yoffset="1" side="left">M144K.data_addr_control_in[180:155] M144K.data_out[51:44]                                   </loc>
        <loc yoffset="0" side="left">M144K.data_addr_control_in[206:181] M144K.data_out[59:52]                                   </loc>
        <loc yoffset="7" side="right">M144K.data_addr_control_in[232:207] M144K.data_out[67:60]                                   </loc>
        <loc yoffset="6" side="right">M144K.data_addr_control_in[258:233] M144K.data_out[75:68]                                   </loc>
        <loc yoffset="5" side="right">M144K.data_addr_control_in[284:259] M144K.data_out[82:76]                                   </loc>
        <loc yoffset="4" side="right">M144K.data_addr_control_in[310:285] M144K.data_out[89:83]   M144K.control_out[2]              </loc>
        <loc yoffset="3" side="right">M144K.data_addr_control_in[336:311] M144K.data_out[96:90]                      M144K.clk_in[1]</loc>
        <loc yoffset="2" side="right">M144K.data_addr_control_in[362:337] M144K.data_out[103:97]                                  </loc>
        <loc yoffset="1" side="right">M144K.data_addr_control_in[388:363] M144K.data_out[111:104]                                 </loc>
        <loc yoffset="0" side="right">M144K.data_addr_control_in[415:389] M144K.data_out[119:112]                                 </loc>
        <loc yoffset="7" side="top">M144K.data_addr_control_in[51:0]    M144K.data_out[14:0]                                    </loc>
        <loc yoffset="6" side="top">M144K.data_addr_control_in[103:52]  M144K.data_out[29:15]                                   </loc>
        <loc yoffset="5" side="top">M144K.data_addr_control_in[155:104] M144K.data_out[44:30]   M144K.control_out[0]              </loc>
        <loc yoffset="4" side="top">M144K.data_addr_control_in[207:156] M144K.data_out[59:45]   M144K.control_out[1] M144K.clk_in[0]</loc>
        <loc yoffset="3" side="top">M144K.data_addr_control_in[259:208] M144K.data_out[74:60]   M144K.control_out[2] M144K.clk_in[1]</loc>
        <loc yoffset="2" side="top">M144K.data_addr_control_in[311:260] M144K.data_out[89:75]                                   </loc>
        <loc yoffset="1" side="top">M144K.data_addr_control_in[363:312] M144K.data_out[104:90]                                  </loc>
        <loc yoffset="0" side="top">M144K.data_addr_control_in[415:364] M144K.data_out[119:105]                                 </loc>
        <loc yoffset="7" side="bottom"/>
        <loc yoffset="6" side="bottom"/>
        <loc yoffset="5" side="bottom"/>
        <loc yoffset="4" side="bottom"/>
        <loc yoffset="3" side="bottom"/>
        <loc yoffset="2" side="bottom"/>
        <loc yoffset="1" side="bottom"/>
        <loc yoffset="0" side="bottom"/>
      </pinlocations>
    </tile>
  </tiles>
  <layout>
    <auto_layout aspect_ratio="1.35">
      <!-- Stratix IV IO blocks connect to both horizontal and vertical
             routing channels. We approximate this by placing them one unit
             'in' from the true perimeter (which is left empty). This means
             that they are fully surrounded by routing channels, allowing them
             to connect to both horizontal and vertical channels. This is a
             minor approximation since on real Stratix IV devices there is no 
             perimeter-side vertical routing channel -->
      <perimeter type="EMPTY" priority="5000"/>
      <col type="io" startx="1" priority="1001"/>
      <!-- Left side -->
      <col type="io" startx="W-2" priority="1001"/>
      <!-- Right side -->
      <row type="io" starty="1" priority="1000"/>
      <!-- Bottom side -->
      <row type="io" starty="H-2" priority="1000"/>
      <!-- Top side -->
      <!-- Stratix IV devices support up to 12 PLLs located around the device perimeter 
             as indicated in Figure 5-1 of Chapter 5 of the Stratix IV handbook

             Note the use of different priorities to avoid ambiguity on small devices -->
      <single type="PLL" x="1" y="H-2" priority="1997"/>
      <!-- L1 -->
      <single type="PLL" x="1" y="H/2" priority="2000"/>
      <!-- L2 -->
      <single type="PLL" x="1" y="H/2 - 1" priority="1999"/>
      <!-- L3 -->
      <single type="PLL" x="1" y="1" priority="1998"/>
      <!-- L4 -->
      <single type="PLL" x="W - 2" y="H-2" priority="1997"/>
      <!-- R1 -->
      <single type="PLL" x="W - 2" y="H/2" priority="2000"/>
      <!-- R2 -->
      <single type="PLL" x="W - 2" y="H/2 - 1" priority="1999"/>
      <!-- R3 -->
      <single type="PLL" x="W - 2" y="1" priority="1998"/>
      <!-- R4 -->
      <single type="PLL" x="W/2" y="H-2" priority="1996"/>
      <!-- T1 -->
      <single type="PLL" x="W/2 + 1" y="H-2" priority="1995"/>
      <!-- T2 -->
      <single type="PLL" x="W/2" y="1" priority="1994"/>
      <!-- B1 -->
      <single type="PLL" x="W/2 + 1" y="1" priority="1993"/>
      <!-- B2 -->
      <!--Fill with 'LAB'-->
      <fill type="LAB" priority="10"/>
      <!--Column of 'DSP' with 'EMPTY' blocks wherever a 'DSP' does not fit. Vertical offset by 1 for perimeter.-->
      <col type="DSP" startx="6" starty="2" repeatx="40" priority="150"/>
      <col type="EMPTY" startx="6" repeatx="40" starty="1" priority="149"/>
      <!--Column of 'M9K' with 'EMPTY' blocks wherever a 'M9K' does not fit. Vertical offset by 1 for perimeter.-->
      <col type="M9K" startx="5" starty="2" repeatx="26" priority="50"/>
      <col type="EMPTY" startx="5" repeatx="26" starty="1" priority="49"/>
      <!--Column of 'M144K' with 'EMPTY' blocks wherever a 'M144K' does not fit. Vertical offset by 1 for perimeter.-->
      <col type="M144K" startx="33" starty="2" repeatx="43" priority="100"/>
      <col type="EMPTY" startx="33" repeatx="43" starty="1" priority="99"/>
    </auto_layout>
    <fixed_layout name="EP4SGX110" width="82" height="66">
      <!-- Stratix IV IO blocks connect to both horizontal and vertical
             routing channels. We approximate this by placing them one unit
             'in' from the true perimeter (which is left empty). This means
             that they are fully surrounded by routing channels, allowing them
             to connect to both horizontal and vertical channels. This is a
             minor approximation since on real Stratix IV devices there is no 
             perimeter-side vertical routing channel -->
      <perimeter type="EMPTY" priority="5000"/>
      <col type="io" startx="1" priority="1001"/>
      <!-- Left side -->
      <col type="io" startx="W-2" priority="1001"/>
      <!-- Right side -->
      <row type="io" starty="1" priority="1000"/>
      <!-- Bottom side -->
      <row type="io" starty="H-2" priority="1000"/>
      <!-- Top side -->
      <!-- Stratix IV devices support up to 12 PLLs located around the device perimeter 
             as indicated in Figure 5-1 of Chapter 5 of the Stratix IV handbook

             Note the use of different priorities to avoid ambiguity on small devices -->
      <single type="PLL" x="1" y="H-2" priority="1997"/>
      <!-- L1 -->
      <single type="PLL" x="1" y="H/2" priority="2000"/>
      <!-- L2 -->
      <single type="PLL" x="1" y="H/2 - 1" priority="1999"/>
      <!-- L3 -->
      <single type="PLL" x="1" y="1" priority="1998"/>
      <!-- L4 -->
      <single type="PLL" x="W - 2" y="H-2" priority="1997"/>
      <!-- R1 -->
      <single type="PLL" x="W - 2" y="H/2" priority="2000"/>
      <!-- R2 -->
      <single type="PLL" x="W - 2" y="H/2 - 1" priority="1999"/>
      <!-- R3 -->
      <single type="PLL" x="W - 2" y="1" priority="1998"/>
      <!-- R4 -->
      <single type="PLL" x="W/2" y="H-2" priority="1996"/>
      <!-- T1 -->
      <single type="PLL" x="W/2 + 1" y="H-2" priority="1995"/>
      <!-- T2 -->
      <single type="PLL" x="W/2" y="1" priority="1994"/>
      <!-- B1 -->
      <single type="PLL" x="W/2 + 1" y="1" priority="1993"/>
      <!-- B2 -->
      <!--Fill with 'LAB'-->
      <fill type="LAB" priority="10"/>
      <!--Column of 'DSP' with 'EMPTY' blocks wherever a 'DSP' does not fit. Vertical offset by 1 for perimeter.-->
      <col type="DSP" startx="6" starty="2" repeatx="40" priority="150"/>
      <col type="EMPTY" startx="6" repeatx="40" starty="1" priority="149"/>
      <!--Column of 'M9K' with 'EMPTY' blocks wherever a 'M9K' does not fit. Vertical offset by 1 for perimeter.-->
      <col type="M9K" startx="5" starty="2" repeatx="26" priority="50"/>
      <col type="EMPTY" startx="5" repeatx="26" starty="1" priority="49"/>
      <!--Column of 'M144K' with 'EMPTY' blocks wherever a 'M144K' does not fit. Vertical offset by 1 for perimeter.-->
      <col type="M144K" startx="33" starty="2" repeatx="43" priority="100"/>
      <col type="EMPTY" startx="33" repeatx="43" starty="1" priority="99"/>
    </fixed_layout>
    <!--
        Stratix IV has only 4 unique device dies. 
        Some devices are 'virtual': based off another die, with utilization limits controlled by Quartus

        Equivalent Devices:
           EP4SGX110: EP4SGX70
           EP4SGX230: EP4SGX180
           EP4SGX530: EP4SGX360 EP4SGX290
           EP4SGX830:
       -->
    <!--<fixed_layout name="EP4SGX110" width="82" height="66"/>-->
    <!--<fixed_layout name="EP4SGX230" width="120" height="97"/>-->
    <!--<fixed_layout name="EP4SGX530" width="186" height="129"/>-->
    <!--<fixed_layout name="EP4SE820" width="220" height="162"/>-->
  </layout>
  <device>
    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
    <!-- KEM: Oct 15, 2013
         Place no timing delay on the input pin of complex blocks.
         We model this directly inside the block, rather than in the
         global routing delay. This matches the behaviour of
         Quartus II. -->
    <area grid_logic_tile_area="0.0"/>
    <chan_width_distr>
      <x distr="uniform" peak="1.000000"/>
      <y distr="uniform" peak="1.000000"/>
    </chan_width_distr>
    <switch_block type="custom"/>
    <connection_block input_switch_name="ipin_cblock"/>
  </device>
  <switchlist>
    <!-- KEM: Oct 15, 2013
         We define two types of drivers, one for each of the segment types (see comment in <segmentlist> section)

         VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
	       book area formula. This means the mux transistors are about 5x minimum drive strength.
	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
	       (diff of second stage).

         KEM: Based on the above and scaling the PTM model from 45nm to 40nm yields the capacitance values listed for the
              'seg4_driver'.  The values for 'seg16_driver' are simply 3x those of the 'seg4_driver', since it has 3x the
              drive strength.  This is very close to the actual values (within 5%) found by performing the look-up procedure
              described above.

              seg4_driver first stage (Both 3x min):
                Cg_Nmos: 3.9967e-16 F
                Cg_Pmos: 2.7652e-16 F

                Cin_45 = Cg_Nmos + Cg_Pmos = 0.676e-15 F
                Cin_40 = (40/45)(Cin_45) = 0.601e-15 F

              seg4_driver second stage (Nmos 16.2x min, Pmos 29.2x min):
                Cd_Nmos: 1.4459e-15
                Cd_Pmos: 3.9751e-15

                Cout_45 = Cd_Nmos + Cd_Pmos = 5.42e-15 F
                Cout_40 = (40 nm/45 nm)(Cout_45) = 4.82e-15 F

              The R values and Tdel (intrinsic switch delay) were choosen to correlate the overall wire delay with Quartus II,
              while keeping the switch delay a reasonable (see comment in <segmentlist>) portion of the overall delay.
       -->
    <switch type="mux" name="seg4_driver" R="450" Cin="0.60e-15" Cout="4.82e-15" Tdel="59e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
    <!-- KEM: Since the L16 wires are 4x as long as the L4s, it is not unreasonable to have the L16 drivers be at least 3x as
         powerful. -->
    <switch type="mux" name="seg16_driver" R="150" Cin="1.80e-15" Cout="14.5e-15" Tdel="87e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="0e0" mux_trans_size="1.222260" buf_size="auto"/>
  </switchlist>
  <segmentlist>
    <!-- KEM: Oct 15, 2013

           Wire distribution:
             In stratix IV there are four types of wires: R4, R20, C4, C12
             R wires are row wires running horizontally accross the chip
             C wires are column wires running vertically accross the chip

             The wire counts for Stratix IV channels are:
                R4 : 272
                C4 : 160
                R20:  40
                C12:  24

             This corresponds to roughly 13% long wires in each horizontal or vertical channel.

             Since VPR can not model non-unifrom channels (both in terms of wire types and channel
             widths), we model the routing network as follows:
                - A channel width of 300 wires (provided on the command line)
                - 13% of wires are long wires of length 16 (average of 20 and 12)
                - The remainder (87%) of wires are length 4


           Metal data:
             For intermediate wires (from ITRS 2007 for the 2008 year [M1 1/2 pitch of 59nm]):
                 Resistivity (uohm*cm): 3.63
                 Capacitance (pF/cm)  : 2.0

             Assuming a (square) Stratix IV LAB is 90um per side.

             Then, for L4 wires assuming:
              - Intermediate wire half-pitch of 90nm
              - Wire height is 2x wire width

                 Resistance_L4/meter = (3.63 uOhm*cm)(10^-2 m/cm)(10^-6 ohm/uOhm)/[2*(90e-9 m)^2]
                 Resistance_L4/meter = 2.25e6 ohm/m

                 Resistance_L4/LAB = (2.25e6 ohm/m)(90e-6 m/LAB) = 201.7 ohm/LAB

                 Capacitance_L4/LAB = (2.0 pF/cm)(10^2 cm/m)(10^-12 F/pF)(90e-6 m/LAB) = 18.0e-15 F/LAB

             L16 wires in contrast, are implemented in the top layers of the metal stack
             which are significantly less resistive (assuming ~2x vs L4) and are also not implemented
             at minumum width (assuming ~2x further decrease in resistance).  Therefore, the
             L16 wires are ~4x less resistive than L4 wires.

                 Resistance_L16/LAB = Resistance_L4/LAB / 4 = 201.7 / 4 = 50.42 ohm/LAB

             Further, according to ITRS global wires are ~15% more capactivie than intermediate
             wires.

                 Capacitance_L16/LAB = Capacitance_L4/LAB * 1.15 = 18.0e-15 * 1.15 = 20.7e-15 F/LAB


           Wire delays:

             Measuring maximum and minimum delays of actual wires using Quartus II resulted in the following average
             delays:
                R4:    max: 116 ps  min: 105 ps
                C4:    max: 245 ps  min: 185 ps
                R20:   max: 305 ps  min: 269 ps
                C12:   max: 273 ps  min: 231 ps

             Averaging accross wires of the same type we attempted to make the wires (including
             drivers) correlate to the following values:
                L4:    max: 181 ps  min: 145 ps
                L16:   min: 289 ps  min: 250 ps

             Currently VPR only models the maximum capacitance of the wire. When VPR models the minimum capacitances, 
             the minimum wire delays should correspond to VPR's result.

             With the maximum capacitance used, current parameters we achieve the following:
                L4:    131 ps
                L16:   293 ps
             which are close to the target maximum values.

             Delay breakdown for each wire type is as follows:
                L4:
                  Switch R & Downstream C: 37.8 ps
                  Intrinsic Switch Delay : 59.0 ps
                  Wire R & Downstream C  : 33.8 ps

                L16:
                  Switch R & Downstream C:  55.9 ps
                  Intrinsic Switch Delay :  87.0 ps
                  Wire R & Downstream C  : 150.0 ps

                For L4 the intrinsic switch delay is ~45% of the total wire delay.
                For L16 the intrinsic switch delay is ~30% of the total wire delay.
                Both of these values are reasonable.
          -->
    <segment name="L4" freq="260" length="4" type="unidir" Rmetal="201.7" Cmetal="18.0e-15">
      <mux name="seg4_driver"/>
      <!-- L4 connect to connection block L4 and L4prime -->
      <sb type="pattern">1 1 1 1 1</sb>
      <cb type="pattern">1 1 1 1</cb>
    </segment>
    <segment name="L16" freq="40" length="16" type="unidir" Rmetal="50.42" Cmetal="20.7e-15">
      <mux name="seg16_driver"/>
      <!-- L16 connect to L16 and L4 -->
      <!-- Vias from the top of the metal stack (global layers, where the long wires are 
           implemented) down to the middle/bottom of the metal stack (semi-global layers, 
           where the short wires are implemented) are expensive and restrictive.
           
           As a result Startix IV only places long wire switch blocks every 4 LABs -->
      <sb type="pattern">1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1</sb>
      <!-- For the same reasons, long wires do not connect to block pins in Stratix IV -->
      <cb type="pattern">0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0</cb>
    </segment>
  </segmentlist>
  <directlist>
    <!--Carry chain propogates downward between LAB blocks-->
    <direct name="LAB_carry_chain" from_pin="LAB.cout" to_pin="LAB.cin" x_offset="0" y_offset="-1" z_offset="0"/>
    <direct name="LAB_share_chain" from_pin="LAB.shareout" to_pin="LAB.sharein" x_offset="0" y_offset="-1" z_offset="0"/>
    <!-- LAB direct-link interconnect. 20-bits go each way to the horizontally adjacent blocks.  
           The actual indexes used are choosen to align with which bits are on each side of 
           the LAB (see LAB & block pinlocations) -->
    <direct name="LAB-LAB_directlink_drive_right" from_pin="LAB.data_out[39:20]" from_side="right" to_pin="LAB.data_in[19:0]" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="LAB-LAB_directlink_drive_left" from_pin="LAB.data_out[19:0]" from_side="left" to_pin="LAB.data_in[79:60]" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="LAB-M9K_directlink_drive_right" from_pin="LAB.data_out[39:20]" from_side="right" to_pin="M9K.data_addr_control_in[19:0]" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="LAB-M9K_directlink_drive_left" from_pin="LAB.data_out[19:0]" from_side="left" to_pin="M9K.data_addr_control_in[79:60]" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="LAB-M144K_directlink_drive_right_y7" from_pin="LAB.data_out[39:20]" from_side="right" to_pin="M144K.data_addr_control_in[19:0]" to_side="left" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="LAB-M144K_directlink_drive_right_y6" from_pin="LAB.data_out[39:20]" from_side="right" to_pin="M144K.data_addr_control_in[44:25]" to_side="left" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="LAB-M144K_directlink_drive_right_y5" from_pin="LAB.data_out[39:20]" from_side="right" to_pin="M144K.data_addr_control_in[70:51]" to_side="left" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="LAB-M144K_directlink_drive_right_y4" from_pin="LAB.data_out[39:20]" from_side="right" to_pin="M144K.data_addr_control_in[96:77]" to_side="left" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="LAB-M144K_directlink_drive_right_y3" from_pin="LAB.data_out[39:20]" from_side="right" to_pin="M144K.data_addr_control_in[122:103]" to_side="left" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="LAB-M144K_directlink_drive_right_y2" from_pin="LAB.data_out[39:20]" from_side="right" to_pin="M144K.data_addr_control_in[148:129]" to_side="left" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="LAB-M144K_directlink_drive_right_y1" from_pin="LAB.data_out[39:20]" from_side="right" to_pin="M144K.data_addr_control_in[174:155]" to_side="left" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="LAB-M144K_directlink_drive_right_y0" from_pin="LAB.data_out[39:20]" from_side="right" to_pin="M144K.data_addr_control_in[200:181]" to_side="left" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="LAB-M144K_directlink_drive_left_y7" from_pin="LAB.data_out[19:0]" from_side="left" to_pin="M144K.data_addr_control_in[226:207]" to_side="right" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="LAB-M144K_directlink_drive_left_y6" from_pin="LAB.data_out[19:0]" from_side="left" to_pin="M144K.data_addr_control_in[252:233]" to_side="right" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="LAB-M144K_directlink_drive_left_y5" from_pin="LAB.data_out[19:0]" from_side="left" to_pin="M144K.data_addr_control_in[278:259]" to_side="right" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="LAB-M144K_directlink_drive_left_y4" from_pin="LAB.data_out[19:0]" from_side="left" to_pin="M144K.data_addr_control_in[304:285]" to_side="right" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="LAB-M144K_directlink_drive_left_y3" from_pin="LAB.data_out[19:0]" from_side="left" to_pin="M144K.data_addr_control_in[330:311]" to_side="right" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="LAB-M144K_directlink_drive_left_y2" from_pin="LAB.data_out[19:0]" from_side="left" to_pin="M144K.data_addr_control_in[356:337]" to_side="right" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="LAB-M144K_directlink_drive_left_y1" from_pin="LAB.data_out[19:0]" from_side="left" to_pin="M144K.data_addr_control_in[382:363]" to_side="right" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="LAB-M144K_directlink_drive_left_y0" from_pin="LAB.data_out[19:0]" from_side="left" to_pin="M144K.data_addr_control_in[408:389]" to_side="right" x_offset="-1" y_offset="0" z_offset="0"/>
    <!-- Note: Need to specify to_side to aoid ambiguity with multi-height blocks -->
    <direct name="LAB-DSP_directlink_drive_right_y3" from_pin="LAB.data_out[39:20]" from_side="right" to_pin="DSP.data_in[19:0]" to_side="left" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="LAB-DSP_directlink_drive_right_y2" from_pin="LAB.data_out[39:20]" from_side="right" to_pin="DSP.data_in[55:36]" to_side="left" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="LAB-DSP_directlink_drive_right_y1" from_pin="LAB.data_out[39:20]" from_side="right" to_pin="DSP.data_in[164:145]" to_side="left" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="LAB-DSP_directlink_drive_right_y0" from_pin="LAB.data_out[39:20]" from_side="right" to_pin="DSP.data_in[199:180]" to_side="left" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="LAB-DSP_directlink_drive_left_y3" from_pin="LAB.data_out[19:0]" from_side="left" to_pin="DSP.data_in[91:72]" to_side="right" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="LAB-DSP_directlink_drive_left_y2" from_pin="LAB.data_out[19:0]" from_side="left" to_pin="DSP.data_in[127:108]" to_side="right" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="LAB-DSP_directlink_drive_left_y1" from_pin="LAB.data_out[19:0]" from_side="left" to_pin="DSP.data_in[235:216]" to_side="right" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="LAB-DSP_directlink_drive_left_y0" from_pin="LAB.data_out[19:0]" from_side="left" to_pin="DSP.data_in[271:252]" to_side="right" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="LAB-IO_directlink_drive_right_z1" from_pin="LAB.data_out[39:30]" from_side="right" to_pin="io.core_in[9:0]" x_offset="1" y_offset="0" z_offset="1"/>
    <direct name="LAB-IO_directlink_drive_right_z0" from_pin="LAB.data_out[29:20]" from_side="right" to_pin="io.core_in[9:0]" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="LAB-IO_directlink_drive_left_z1" from_pin="LAB.data_out[19:10]" from_side="left" to_pin="io.core_in[33:24]" x_offset="-1" y_offset="0" z_offset="1"/>
    <direct name="LAB-IO_directlink_drive_left_z0" from_pin="LAB.data_out[9:0]" from_side="left" to_pin="io.core_in[33:24]" x_offset="-1" y_offset="0" z_offset="0"/>
    <!-- DSP direct-link interconnect. 20-bits go each way to the horizontally adjacent LABs. -->
    <direct name="DSP-LAB_directlink_drive_right_y3" from_pin="DSP.data_out_top[53:36]" from_side="right" to_pin="LAB.data_in[17:0]" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="DSP-LAB_directlink_drive_right_y2" from_pin="DSP.data_out_top[71:54]" from_side="right" to_pin="LAB.data_in[17:0]" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="DSP-LAB_directlink_drive_right_y1" from_pin="DSP.data_out_bot[53:36]" from_side="right" to_pin="LAB.data_in[17:0]" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="DSP-LAB_directlink_drive_right_y0" from_pin="DSP.data_out_bot[71:54]" from_side="right" to_pin="LAB.data_in[17:0]" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="DSP-LAB_directlink_drive_left_y3" from_pin="DSP.data_out_top[17:0]" from_side="left" to_pin="LAB.data_in[77:60]" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="DSP-LAB_directlink_drive_left_y2" from_pin="DSP.data_out_top[35:18]" from_side="left" to_pin="LAB.data_in[77:60]" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="DSP-LAB_directlink_drive_left_y1" from_pin="DSP.data_out_bot[17:0]" from_side="left" to_pin="LAB.data_in[77:60]" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="DSP-LAB_directlink_drive_left_y0" from_pin="DSP.data_out_bot[35:18]" from_side="left" to_pin="LAB.data_in[77:60]" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="DSP-M9K_directlink_drive_right_y3" from_pin="DSP.data_out_top[53:36]" from_side="right" to_pin="M9K.data_addr_control_in[17:0]" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="DSP-M9K_directlink_drive_right_y2" from_pin="DSP.data_out_top[71:54]" from_side="right" to_pin="M9K.data_addr_control_in[17:0]" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="DSP-M9K_directlink_drive_right_y1" from_pin="DSP.data_out_bot[53:36]" from_side="right" to_pin="M9K.data_addr_control_in[17:0]" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="DSP-M9K_directlink_drive_right_y0" from_pin="DSP.data_out_bot[71:54]" from_side="right" to_pin="M9K.data_addr_control_in[17:0]" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="DSP-M9K_directlink_drive_left_y3" from_pin="DSP.data_out_top[17:0]" from_side="left" to_pin="M9K.data_addr_control_in[77:60]" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="DSP-M9K_directlink_drive_left_y2" from_pin="DSP.data_out_top[35:18]" from_side="left" to_pin="M9K.data_addr_control_in[77:60]" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="DSP-M9K_directlink_drive_left_y1" from_pin="DSP.data_out_bot[17:0]" from_side="left" to_pin="M9K.data_addr_control_in[77:60]" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="DSP-M9K_directlink_drive_left_y0" from_pin="DSP.data_out_bot[35:18]" from_side="left" to_pin="M9K.data_addr_control_in[77:60]" x_offset="-1" y_offset="0" z_offset="0"/>
    <!-- M9K direct-link interconnect. 20-bits go each way to the horizontally adjacent LABs. -->
    <direct name="M9K-LAB_directlink_drive_right_data" from_pin="M9K.data_out[35:18]" from_side="right" to_pin="LAB.data_in[17:0]" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="M9K-LAB_directlink_drive_right_control" from_pin="M9K.control_out[2:2]" from_side="right" to_pin="LAB.data_in[18:18]" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="M9K-LAB_directlink_drive_left_data" from_pin="M9K.data_out[17:0]" from_side="left" to_pin="LAB.data_in[77:60]" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="M9K-LAB_directlink_drive_left_control" from_pin="M9K.control_out[1:0]" from_side="left" to_pin="LAB.data_in[79:78]" x_offset="-1" y_offset="0" z_offset="0"/>
    <!-- Note: Need to specify to_side to aoid ambiguity with multi-height blocks -->
    <direct name="M9K-DSP_directlink_drive_right_data_y3" from_pin="M9K.data_out[35:18]" from_side="right" to_pin="DSP.data_in[17:0]" to_side="left" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="M9K-DSP_directlink_drive_right_data_y2" from_pin="M9K.data_out[35:18]" from_side="right" to_pin="DSP.data_in[53:36]" to_side="left" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="M9K-DSP_directlink_drive_right_data_y1" from_pin="M9K.data_out[35:18]" from_side="right" to_pin="DSP.data_in[162:145]" to_side="left" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="M9K-DSP_directlink_drive_right_data_y0" from_pin="M9K.data_out[35:18]" from_side="right" to_pin="DSP.data_in[197:180]" to_side="left" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="M9K-DSP_directlink_drive_left_data_y3" from_pin="M9K.data_out[17:0]" from_side="left" to_pin="DSP.data_in[89:72]" to_side="right" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="M9K-DSP_directlink_drive_left_data_y2" from_pin="M9K.data_out[17:0]" from_side="left" to_pin="DSP.data_in[125:108]" to_side="right" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="M9K-DSP_directlink_drive_left_data_y1" from_pin="M9K.data_out[17:0]" from_side="left" to_pin="DSP.data_in[233:216]" to_side="right" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="M9K-DSP_directlink_drive_left_data_y0" from_pin="M9K.data_out[17:0]" from_side="left" to_pin="DSP.data_in[269:252]" to_side="right" x_offset="-1" y_offset="0" z_offset="0"/>
    <!-- M144K direct-link interconnect. 20-bits go each way at each gtid location to the horizontally adjacent LABs. -->
    <direct name="M144K-LAB_directlink_drive_right_y7" from_pin="M144K.data_out[67:60]" from_side="right" to_pin="LAB.data_in[7:0]" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="M144K-LAB_directlink_drive_right_y6" from_pin="M144K.data_out[75:68]" from_side="right" to_pin="LAB.data_in[7:0]" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="M144K-LAB_directlink_drive_right_y5" from_pin="M144K.data_out[82:76]" from_side="right" to_pin="LAB.data_in[6:0]" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="M144K-LAB_directlink_drive_right_y4" from_pin="M144K.data_out[89:83]" from_side="right" to_pin="LAB.data_in[6:0]" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="M144K-LAB_directlink_drive_right_y3" from_pin="M144K.data_out[96:90]" from_side="right" to_pin="LAB.data_in[6:0]" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="M144K-LAB_directlink_drive_right_y2" from_pin="M144K.data_out[103:97]" from_side="right" to_pin="LAB.data_in[6:0]" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="M144K-LAB_directlink_drive_right_y1" from_pin="M144K.data_out[111:104]" from_side="right" to_pin="LAB.data_in[7:0]" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="M144K-LAB_directlink_drive_right_y0" from_pin="M144K.data_out[119:112]" from_side="right" to_pin="LAB.data_in[7:0]" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="M144K-LAB_directlink_drive_left_y7" from_pin="M144K.data_out[7:0]" from_side="left" to_pin="LAB.data_in[67:60]" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="M144K-LAB_directlink_drive_left_y6" from_pin="M144K.data_out[15:8]" from_side="left" to_pin="LAB.data_in[67:60]" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="M144K-LAB_directlink_drive_left_y5" from_pin="M144K.data_out[22:16]" from_side="left" to_pin="LAB.data_in[66:60]" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="M144K-LAB_directlink_drive_left_y4" from_pin="M144K.data_out[29:23]" from_side="left" to_pin="LAB.data_in[66:60]" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="M144K-LAB_directlink_drive_left_y3" from_pin="M144K.data_out[36:30]" from_side="left" to_pin="LAB.data_in[66:60]" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="M144K-LAB_directlink_drive_left_y2" from_pin="M144K.data_out[43:37]" from_side="left" to_pin="LAB.data_in[66:60]" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="M144K-LAB_directlink_drive_left_y1" from_pin="M144K.data_out[51:44]" from_side="left" to_pin="LAB.data_in[67:60]" x_offset="-1" y_offset="0" z_offset="0"/>
    <direct name="M144K-LAB_directlink_drive_left_y0" from_pin="M144K.data_out[59:52]" from_side="left" to_pin="LAB.data_in[67:60]" x_offset="-1" y_offset="0" z_offset="0"/>
    <!-- IO direct-link interconnect. 20-bits go each way at each gtid location to the horizontally adjacent LABs. -->
    <direct name="IO-LAB_directlink_drive_right_z1" from_pin="io.core_out[29:20]" from_side="right" to_pin="LAB.data_in[19:10]" x_offset="1" y_offset="0" z_offset="-1"/>
    <direct name="IO-LAB_directlink_drive_right_z0" from_pin="io.core_out[29:20]" from_side="right" to_pin="LAB.data_in[9:0]" x_offset="1" y_offset="0" z_offset="0"/>
    <direct name="IO-LAB_directlink_drive_left_z1" from_pin="io.core_out[9:0]" from_side="left" to_pin="LAB.data_in[79:70]" x_offset="-1" y_offset="0" z_offset="-1"/>
    <direct name="IO-LAB_directlink_drive_left_z0" from_pin="io.core_out[9:0]" from_side="left" to_pin="LAB.data_in[69:60]" x_offset="-1" y_offset="0" z_offset="0"/>
  </directlist>
  <complexblocklist>
    <pb_type name="io">
      <input name="core_in" num_pins="50" equivalent="none"/>
      <output name="core_out" num_pins="40" equivalent="none"/>
      <clock name="clk" num_pins="5"/>
      <mode name="io">
        <pb_type name="pad" num_pb="1">
          <output name="recieve_off_chip" num_pins="1"/>
          <input name="drive_off_chip" num_pins="1"/>
          <mode name="inpad">
            <pb_type blif_model=".input" name="inpad" num_pb="1">
              <output name="inpad" num_pins="1"/>
            </pb_type>
            <interconnect>
              <direct input="inpad.inpad" name="inpad" output="pad.recieve_off_chip">
                <!-- KEM:  Using Quartus II with an input and output delay of 0ns recived 
							the following input buffer delays:

                         QII Models several maximum delays on inputs:
                            1) The IOIBUF: 440ps to 740ps, typical 606ps 
                            2) The TITAN_IO_IBUF: typical 776 ps [In some instances values of 3514ps are reported but these seem unreasonably large for typical usage]
                            2) The IO_DATAIN: typical 36ps 

                            We model these as a single maximum delay of: 1418ps

						QII Models several minimum delays on inputs:
                            1) The IOIBUF: typical 569ps 
                            2) The TITAN_IO_IBUF: typical 715 ps [In some instances values of 3237ps are reported but these seem unreasonably large for typical usage]
                            2) The IO_DATAIN: typical 34ps 

                            We model these as a single minimum delay of: 1318ps
                            -->
                <delay_constant max="1418e-12" min="1318e-12" in_port="inpad.inpad" out_port="pad.recieve_off_chip"/>
              </direct>
            </interconnect>
          </mode>
          <mode name="outpad">
            <pb_type blif_model=".output" name="outpad" num_pb="1">
              <input name="outpad" num_pins="1"/>
            </pb_type>
            <interconnect>
              <direct input="pad.drive_off_chip" name="outpad" output="outpad.outpad">
                <!-- KEM From Quartus II: maximum output buffer delays: 2702ps to 3016ps, typical 2922ps
 					   Minimum output buffer delays: typical 2789 -->
                <delay_constant max="2922e-12" min="2789e-12" in_port="pad.drive_off_chip" out_port="outpad.outpad"/>
              </direct>
            </interconnect>
          </mode>
        </pb_type>
        <pb_type name="io_cell" num_pb="5">
          <input name="data_in" num_pins="32"/>
          <output name="data_out" num_pins="50"/>
          <clock name="clk" num_pins="1"/>
          <mode name="stratixiv_io_ibuf">
            <pb_type blif_model=".subckt stratixiv_io_ibuf" name="stratixiv_io_ibuf" num_pb="1">
              <input name="i" num_pins="1"/>
              <input name="ibar" num_pins="1"/>
              <output name="o" num_pins="1"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_io_ibuf.i" out_port="stratixiv_io_ibuf.o"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_io_ibuf.ibar" out_port="stratixiv_io_ibuf.o"/>
            </pb_type>
            <interconnect>
              <complete input="io_cell.data_in" name="data_in" output="stratixiv_io_ibuf.i stratixiv_io_ibuf.ibar"/>
              <complete input="stratixiv_io_ibuf.o" name="data_out" output="io_cell.data_out"/>
            </interconnect>
          </mode>
          <mode name="stratixiv_io_obuf">
            <pb_type blif_model=".subckt stratixiv_io_obuf" name="stratixiv_io_obuf" num_pb="1">
              <input name="i" num_pins="1"/>
              <input name="oe" num_pins="1"/>
              <input name="dynamicterminationcontrol" num_pins="1"/>
              <input name="seriesterminationcontrol" num_pins="14"/>
              <input name="parallelterminationcontrol" num_pins="14"/>
              <output name="o" num_pins="1"/>
              <output name="obar" num_pins="1"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_io_obuf.i" out_port="stratixiv_io_obuf.o stratixiv_io_obuf.obar"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_io_obuf.oe" out_port="stratixiv_io_obuf.o stratixiv_io_obuf.obar"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_io_obuf.dynamicterminationcontrol" out_port="stratixiv_io_obuf.o stratixiv_io_obuf.obar"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_io_obuf.seriesterminationcontrol" out_port="stratixiv_io_obuf.o stratixiv_io_obuf.obar"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_io_obuf.parallelterminationcontrol" out_port="stratixiv_io_obuf.o stratixiv_io_obuf.obar"/>
            </pb_type>
            <interconnect>
              <complete input="io_cell.data_in" name="data_in" output="stratixiv_io_obuf.i stratixiv_io_obuf.oe stratixiv_io_obuf.dynamicterminationcontrol stratixiv_io_obuf.seriesterminationcontrol stratixiv_io_obuf.parallelterminationcontrol"/>
              <complete input="stratixiv_io_obuf.o stratixiv_io_obuf.obar" name="data_out" output="io_cell.data_out"/>
            </interconnect>
          </mode>
          <mode name="stratixiv_ddio_out">
            <pb_type blif_model=".subckt stratixiv_ddio_out" name="stratixiv_ddio_out" num_pb="1">
              <input name="datainlo" num_pins="1"/>
              <input name="datainhi" num_pins="1"/>
              <input name="clk" num_pins="1"/>
              <input name="clklo" num_pins="1"/>
              <input name="muxsel" num_pins="1"/>
              <input name="ena" num_pins="1"/>
              <input name="areset" num_pins="1"/>
              <input name="sreset" num_pins="1"/>
              <clock name="clkhi" num_pins="1"/>
              <output name="dataout" num_pins="1"/>
              <T_setup clock="clkhi" port="stratixiv_ddio_out.datainlo" value="0e-12"/>
              <T_setup clock="clkhi" port="stratixiv_ddio_out.datainhi" value="0e-12"/>
              <T_setup clock="clkhi" port="stratixiv_ddio_out.clk" value="0e-12"/>
              <T_setup clock="clkhi" port="stratixiv_ddio_out.clklo" value="0e-12"/>
              <T_setup clock="clkhi" port="stratixiv_ddio_out.muxsel" value="0e-12"/>
              <T_setup clock="clkhi" port="stratixiv_ddio_out.ena" value="0e-12"/>
              <T_setup clock="clkhi" port="stratixiv_ddio_out.areset" value="0e-12"/>
              <T_setup clock="clkhi" port="stratixiv_ddio_out.sreset" value="0e-12"/>
              <T_hold clock="clkhi" port="stratixiv_ddio_out.datainlo" value="0e-12"/>
              <T_hold clock="clkhi" port="stratixiv_ddio_out.datainhi" value="0e-12"/>
              <T_hold clock="clkhi" port="stratixiv_ddio_out.clk" value="0e-12"/>
              <T_hold clock="clkhi" port="stratixiv_ddio_out.clklo" value="0e-12"/>
              <T_hold clock="clkhi" port="stratixiv_ddio_out.muxsel" value="0e-12"/>
              <T_hold clock="clkhi" port="stratixiv_ddio_out.ena" value="0e-12"/>
              <T_hold clock="clkhi" port="stratixiv_ddio_out.areset" value="0e-12"/>
              <T_hold clock="clkhi" port="stratixiv_ddio_out.sreset" value="0e-12"/>
              <T_clock_to_Q clock="clkhi" port="stratixiv_ddio_out.dataout" max="0e-12" min="0e-12"/>
            </pb_type>
            <interconnect>
              <complete input="io_cell.data_in" name="data_in" output="stratixiv_ddio_out.datainlo stratixiv_ddio_out.datainhi stratixiv_ddio_out.clk stratixiv_ddio_out.clklo stratixiv_ddio_out.muxsel stratixiv_ddio_out.ena stratixiv_ddio_out.areset stratixiv_ddio_out.sreset"/>
              <complete input="stratixiv_ddio_out.dataout" name="data_out" output="io_cell.data_out"/>
              <direct input="io_cell.clk" name="clock" output="stratixiv_ddio_out.clkhi"/>
            </interconnect>
          </mode>
          <mode name="stratixiv_ddio_oe">
            <pb_type blif_model=".subckt stratixiv_ddio_oe" name="stratixiv_ddio_oe" num_pb="1">
              <input name="oe" num_pins="1"/>
              <input name="ena" num_pins="1"/>
              <input name="areset" num_pins="1"/>
              <input name="sreset" num_pins="1"/>
              <output name="dataout" num_pins="1"/>
              <clock name="clk" num_pins="1"/>
              <T_setup clock="clk" port="stratixiv_ddio_oe.oe" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_ddio_oe.ena" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_ddio_oe.areset" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_ddio_oe.sreset" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_ddio_oe.oe" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_ddio_oe.ena" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_ddio_oe.areset" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_ddio_oe.sreset" value="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_ddio_oe.dataout" max="0e-12" min="0e-12"/>
            </pb_type>
            <interconnect>
              <complete input="io_cell.data_in" name="data_in" output="stratixiv_ddio_oe.oe stratixiv_ddio_oe.ena stratixiv_ddio_oe.areset stratixiv_ddio_oe.sreset"/>
              <complete input="stratixiv_ddio_oe.dataout" name="data_out" output="io_cell.data_out"/>
              <direct input="io_cell.clk" name="clock" output="stratixiv_ddio_oe.clk"/>
            </interconnect>
          </mode>
          <mode name="stratixiv_ddio_in">
            <pb_type blif_model=".subckt stratixiv_ddio_in" name="stratixiv_ddio_in" num_pb="1">
              <input name="datain" num_pins="1"/>
              <input name="clkn" num_pins="1"/>
              <input name="ena" num_pins="1"/>
              <input name="areset" num_pins="1"/>
              <input name="sreset" num_pins="1"/>
              <clock name="clk" num_pins="1"/>
              <output name="regoutlo" num_pins="1"/>
              <output name="regouthi" num_pins="1"/>
              <T_setup clock="clk" port="stratixiv_ddio_in.datain" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_ddio_in.clkn" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_ddio_in.ena" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_ddio_in.areset" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_ddio_in.sreset" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_ddio_in.datain" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_ddio_in.clkn" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_ddio_in.ena" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_ddio_in.areset" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_ddio_in.sreset" value="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_ddio_in.regoutlo" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_ddio_in.regouthi" max="0e-12" min="0e-12"/>
            </pb_type>
            <interconnect>
              <complete input="io_cell.data_in" name="data_in" output="stratixiv_ddio_in.datain stratixiv_ddio_in.clkn stratixiv_ddio_in.ena stratixiv_ddio_in.areset stratixiv_ddio_in.sreset"/>
              <complete input="stratixiv_ddio_in.regoutlo stratixiv_ddio_in.regouthi" name="data_out" output="io_cell.data_out"/>
              <direct input="io_cell.clk" name="clock" output="stratixiv_ddio_in.clk"/>
            </interconnect>
          </mode>
          <mode name="stratixiv_delay_chain">
            <pb_type blif_model=".subckt stratixiv_delay_chain" name="stratixiv_delay_chain" num_pb="1">
              <input name="datain" num_pins="1"/>
              <input name="delayctrlin" num_pins="4"/>
              <input name="finedelayctrlin" num_pins="1"/>
              <input name="devclrn" num_pins="1"/>
              <input name="devpor" num_pins="1"/>
              <output name="dataout" num_pins="1"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_delay_chain.datain" out_port="stratixiv_delay_chain.dataout"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_delay_chain.delayctrlin" out_port="stratixiv_delay_chain.dataout"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_delay_chain.finedelayctrlin" out_port="stratixiv_delay_chain.dataout"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_delay_chain.devclrn" out_port="stratixiv_delay_chain.dataout"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_delay_chain.devpor" out_port="stratixiv_delay_chain.dataout"/>
            </pb_type>
            <interconnect>
              <complete input="io_cell.data_in" name="data_in" output="stratixiv_delay_chain.datain stratixiv_delay_chain.delayctrlin stratixiv_delay_chain.finedelayctrlin stratixiv_delay_chain.devclrn stratixiv_delay_chain.devpor"/>
              <complete input="stratixiv_delay_chain.dataout" name="data_out" output="io_cell.data_out"/>
            </interconnect>
          </mode>
          <mode name="stratixiv_dll">
            <pb_type blif_model=".subckt stratixiv_dll" name="stratixiv_dll" num_pb="1">
              <input name="aload" num_pins="1"/>
              <input name="upndnin" num_pins="1"/>
              <input name="upndninclkena" num_pins="1"/>
              <input name="devclrn" num_pins="1"/>
              <input name="devpor" num_pins="1"/>
              <clock name="clk" num_pins="1"/>
              <output name="offsetdelayctrlout" num_pins="6"/>
              <output name="offsetdelayctrlclkout" num_pins="1"/>
              <output name="delayctrlout" num_pins="6"/>
              <output name="dqsupdate" num_pins="1"/>
              <output name="upndnout" num_pins="1"/>
              <T_setup clock="clk" port="stratixiv_dll.aload" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_dll.upndnin" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_dll.upndninclkena" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_dll.devclrn" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_dll.devpor" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_dll.aload" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_dll.upndnin" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_dll.upndninclkena" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_dll.devclrn" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_dll.devpor" value="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dll.offsetdelayctrlout" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dll.offsetdelayctrlclkout" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dll.delayctrlout" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dll.dqsupdate" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dll.upndnout" max="0e-12" min="0e-12"/>
            </pb_type>
            <interconnect>
              <complete input="io_cell.data_in" name="data_in" output="stratixiv_dll.aload stratixiv_dll.upndnin stratixiv_dll.upndninclkena stratixiv_dll.devclrn stratixiv_dll.devpor"/>
              <complete input="stratixiv_dll.offsetdelayctrlout stratixiv_dll.offsetdelayctrlclkout stratixiv_dll.delayctrlout stratixiv_dll.dqsupdate stratixiv_dll.upndnout" name="data_out" output="io_cell.data_out"/>
              <direct input="io_cell.clk" name="clock" output="stratixiv_dll.clk"/>
            </interconnect>
          </mode>
          <mode name="stratixiv_dqs_config">
            <pb_type blif_model=".subckt stratixiv_dqs_config" name="stratixiv_dqs_config" num_pb="1">
              <input name="datain" num_pins="1"/>
              <input name="ena" num_pins="1"/>
              <input name="update" num_pins="1"/>
              <input name="devclrn" num_pins="1"/>
              <input name="devpor" num_pins="1"/>
              <clock name="clk" num_pins="1"/>
              <output name="dqsbusoutdelaysetting" num_pins="4"/>
              <output name="dqsinputphasesetting" num_pins="3"/>
              <output name="dqsenablectrlphasesetting" num_pins="4"/>
              <output name="dqsoutputphasesetting" num_pins="4"/>
              <output name="dqoutputphasesetting" num_pins="4"/>
              <output name="resyncinputphasesetting" num_pins="4"/>
              <output name="dividerphasesetting" num_pins="1"/>
              <output name="enaoctcycledelaysetting" num_pins="1"/>
              <output name="enainputcycledelaysetting" num_pins="1"/>
              <output name="enaoutputcycledelaysetting" num_pins="1"/>
              <output name="dqsenabledelaysetting" num_pins="3"/>
              <output name="octdelaysetting1" num_pins="4"/>
              <output name="octdelaysetting2" num_pins="3"/>
              <output name="enadataoutbypass" num_pins="1"/>
              <output name="enadqsenablephasetransferreg" num_pins="1"/>
              <output name="enaoctphasetransferreg" num_pins="1"/>
              <output name="enaoutputphasetransferreg" num_pins="1"/>
              <output name="enainputphasetransferreg" num_pins="1"/>
              <output name="resyncinputphaseinvert" num_pins="1"/>
              <output name="dqsenablectrlphaseinvert" num_pins="1"/>
              <output name="dqoutputphaseinvert" num_pins="1"/>
              <output name="dqsoutputphaseinvert" num_pins="1"/>
              <output name="dqsbusoutfinedelaysetting" num_pins="1"/>
              <output name="dqsenablefinedelaysetting" num_pins="1"/>
              <output name="dataout" num_pins="1"/>
              <T_setup clock="clk" port="stratixiv_dqs_config.datain" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_dqs_config.ena" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_dqs_config.update" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_dqs_config.devclrn" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_dqs_config.devpor" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_dqs_config.datain" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_dqs_config.ena" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_dqs_config.update" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_dqs_config.devclrn" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_dqs_config.devpor" value="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.dqsbusoutdelaysetting" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.dqsinputphasesetting" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.dqsenablectrlphasesetting" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.dqsoutputphasesetting" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.dqoutputphasesetting" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.resyncinputphasesetting" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.dividerphasesetting" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.enaoctcycledelaysetting" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.enainputcycledelaysetting" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.enaoutputcycledelaysetting" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.dqsenabledelaysetting" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.octdelaysetting1" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.octdelaysetting2" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.enadataoutbypass" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.enadqsenablephasetransferreg" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.enaoctphasetransferreg" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.enaoutputphasetransferreg" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.enainputphasetransferreg" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.resyncinputphaseinvert" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.dqsenablectrlphaseinvert" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.dqoutputphaseinvert" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.dqsoutputphaseinvert" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.dqsbusoutfinedelaysetting" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.dqsenablefinedelaysetting" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_config.dataout" max="0e-12" min="0e-12"/>
            </pb_type>
            <interconnect>
              <complete input="io_cell.data_in" name="data_in" output="stratixiv_dqs_config.datain stratixiv_dqs_config.ena stratixiv_dqs_config.update stratixiv_dqs_config.devclrn stratixiv_dqs_config.devpor"/>
              <complete input="stratixiv_dqs_config.dqsbusoutdelaysetting stratixiv_dqs_config.dqsinputphasesetting stratixiv_dqs_config.dqsenablectrlphasesetting stratixiv_dqs_config.dqsoutputphasesetting stratixiv_dqs_config.dqoutputphasesetting stratixiv_dqs_config.resyncinputphasesetting stratixiv_dqs_config.dividerphasesetting stratixiv_dqs_config.enaoctcycledelaysetting stratixiv_dqs_config.enainputcycledelaysetting stratixiv_dqs_config.enaoutputcycledelaysetting stratixiv_dqs_config.dqsenabledelaysetting stratixiv_dqs_config.octdelaysetting1 stratixiv_dqs_config.octdelaysetting2 stratixiv_dqs_config.enadataoutbypass stratixiv_dqs_config.enadqsenablephasetransferreg stratixiv_dqs_config.enaoctphasetransferreg stratixiv_dqs_config.enaoutputphasetransferreg stratixiv_dqs_config.enainputphasetransferreg stratixiv_dqs_config.resyncinputphaseinvert stratixiv_dqs_config.dqsenablectrlphaseinvert stratixiv_dqs_config.dqoutputphaseinvert stratixiv_dqs_config.dqsoutputphaseinvert stratixiv_dqs_config.dqsbusoutfinedelaysetting stratixiv_dqs_config.dqsenablefinedelaysetting stratixiv_dqs_config.dataout" name="data_out" output="io_cell.data_out"/>
              <direct input="io_cell.clk" name="clock" output="stratixiv_dqs_config.clk"/>
            </interconnect>
          </mode>
          <mode name="stratixiv_dqs_delay_chain">
            <pb_type blif_model=".subckt stratixiv_dqs_delay_chain" name="stratixiv_dqs_delay_chain" num_pb="1">
              <input name="dqsin" num_pins="1"/>
              <input name="delayctrlin" num_pins="6"/>
              <input name="offsetctrlin" num_pins="6"/>
              <input name="dqsupdateen" num_pins="1"/>
              <input name="phasectrlin" num_pins="3"/>
              <input name="devclrn" num_pins="1"/>
              <input name="devpor" num_pins="1"/>
              <output name="dqsbusout" num_pins="1"/>
              <output name="dffin" num_pins="1"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_dqs_delay_chain.dqsin" out_port="stratixiv_dqs_delay_chain.dqsbusout stratixiv_dqs_delay_chain.dffin"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_dqs_delay_chain.delayctrlin" out_port="stratixiv_dqs_delay_chain.dqsbusout stratixiv_dqs_delay_chain.dffin"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_dqs_delay_chain.offsetctrlin" out_port="stratixiv_dqs_delay_chain.dqsbusout stratixiv_dqs_delay_chain.dffin"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_dqs_delay_chain.dqsupdateen" out_port="stratixiv_dqs_delay_chain.dqsbusout stratixiv_dqs_delay_chain.dffin"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_dqs_delay_chain.phasectrlin" out_port="stratixiv_dqs_delay_chain.dqsbusout stratixiv_dqs_delay_chain.dffin"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_dqs_delay_chain.devclrn" out_port="stratixiv_dqs_delay_chain.dqsbusout stratixiv_dqs_delay_chain.dffin"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_dqs_delay_chain.devpor" out_port="stratixiv_dqs_delay_chain.dqsbusout stratixiv_dqs_delay_chain.dffin"/>
            </pb_type>
            <interconnect>
              <complete input="io_cell.data_in" name="data_in" output="stratixiv_dqs_delay_chain.dqsin stratixiv_dqs_delay_chain.delayctrlin stratixiv_dqs_delay_chain.offsetctrlin stratixiv_dqs_delay_chain.dqsupdateen stratixiv_dqs_delay_chain.phasectrlin stratixiv_dqs_delay_chain.devclrn stratixiv_dqs_delay_chain.devpor"/>
              <complete input="stratixiv_dqs_delay_chain.dqsbusout stratixiv_dqs_delay_chain.dffin" name="data_out" output="io_cell.data_out"/>
            </interconnect>
          </mode>
          <mode name="stratixiv_dqs_enable">
            <pb_type blif_model=".subckt stratixiv_dqs_enable" name="stratixiv_dqs_enable" num_pb="1">
              <input name="dqsin" num_pins="1"/>
              <input name="dqsenable" num_pins="1"/>
              <input name="devclrn" num_pins="1"/>
              <input name="devpor" num_pins="1"/>
              <output name="dqsbusout" num_pins="1"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_dqs_enable.dqsin" out_port="stratixiv_dqs_enable.dqsbusout"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_dqs_enable.dqsenable" out_port="stratixiv_dqs_enable.dqsbusout"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_dqs_enable.devclrn" out_port="stratixiv_dqs_enable.dqsbusout"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_dqs_enable.devpor" out_port="stratixiv_dqs_enable.dqsbusout"/>
            </pb_type>
            <interconnect>
              <complete input="io_cell.data_in" name="data_in" output="stratixiv_dqs_enable.dqsin stratixiv_dqs_enable.dqsenable stratixiv_dqs_enable.devclrn stratixiv_dqs_enable.devpor"/>
              <complete input="stratixiv_dqs_enable.dqsbusout" name="data_out" output="io_cell.data_out"/>
            </interconnect>
          </mode>
          <mode name="stratixiv_dqs_enable_ctrl">
            <pb_type blif_model=".subckt stratixiv_dqs_enable_ctrl" name="stratixiv_dqs_enable_ctrl" num_pb="1">
              <input name="dqsenablein" num_pins="1"/>
              <input name="delayctrlin" num_pins="6"/>
              <input name="phasectrlin" num_pins="4"/>
              <input name="enaphasetransferreg" num_pins="1"/>
              <input name="phaseinvertctrl" num_pins="1"/>
              <input name="devclrn" num_pins="1"/>
              <input name="devpor" num_pins="1"/>
              <clock name="clk" num_pins="1"/>
              <output name="dqsenableout" num_pins="1"/>
              <output name="dffin" num_pins="1"/>
              <output name="dffextenddqsenable" num_pins="1"/>
              <T_setup clock="clk" port="stratixiv_dqs_enable_ctrl.dqsenablein" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_dqs_enable_ctrl.delayctrlin" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_dqs_enable_ctrl.phasectrlin" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_dqs_enable_ctrl.enaphasetransferreg" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_dqs_enable_ctrl.phaseinvertctrl" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_dqs_enable_ctrl.devclrn" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_dqs_enable_ctrl.devpor" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_dqs_enable_ctrl.dqsenablein" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_dqs_enable_ctrl.delayctrlin" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_dqs_enable_ctrl.phasectrlin" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_dqs_enable_ctrl.enaphasetransferreg" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_dqs_enable_ctrl.phaseinvertctrl" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_dqs_enable_ctrl.devclrn" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_dqs_enable_ctrl.devpor" value="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_enable_ctrl.dqsenableout" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_enable_ctrl.dffin" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_dqs_enable_ctrl.dffextenddqsenable" max="0e-12" min="0e-12"/>
            </pb_type>
            <interconnect>
              <complete input="io_cell.data_in" name="data_in" output="stratixiv_dqs_enable_ctrl.dqsenablein stratixiv_dqs_enable_ctrl.delayctrlin stratixiv_dqs_enable_ctrl.phasectrlin stratixiv_dqs_enable_ctrl.enaphasetransferreg stratixiv_dqs_enable_ctrl.phaseinvertctrl stratixiv_dqs_enable_ctrl.devclrn stratixiv_dqs_enable_ctrl.devpor"/>
              <complete input="stratixiv_dqs_enable_ctrl.dqsenableout stratixiv_dqs_enable_ctrl.dffin stratixiv_dqs_enable_ctrl.dffextenddqsenable" name="data_out" output="io_cell.data_out"/>
              <direct input="io_cell.clk" name="clock" output="stratixiv_dqs_enable_ctrl.clk"/>
            </interconnect>
          </mode>
          <mode name="stratixiv_io_config">
            <pb_type blif_model=".subckt stratixiv_io_config" name="stratixiv_io_config" num_pb="1">
              <input name="datain" num_pins="1"/>
              <input name="ena" num_pins="1"/>
              <input name="update" num_pins="1"/>
              <input name="devclrn" num_pins="1"/>
              <input name="devpor" num_pins="1"/>
              <clock name="clk" num_pins="1"/>
              <output name="padtoinputregisterdelaysetting" num_pins="4"/>
              <output name="outputdelaysetting1" num_pins="4"/>
              <output name="outputdelaysetting2" num_pins="3"/>
              <output name="dataout" num_pins="1"/>
              <output name="dutycycledelaymode" num_pins="1"/>
              <output name="dutycycledelaysettings" num_pins="4"/>
              <output name="outputfinedelaysetting1" num_pins="1"/>
              <output name="outputfinedelaysetting2" num_pins="1"/>
              <output name="outputonlydelaysetting2" num_pins="3"/>
              <output name="outputonlyfinedelaysetting2" num_pins="1"/>
              <output name="padtoinputregisterfinedelaysetting" num_pins="1"/>
              <T_setup clock="clk" port="stratixiv_io_config.datain" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_io_config.ena" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_io_config.update" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_io_config.devclrn" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_io_config.devpor" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_io_config.datain" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_io_config.ena" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_io_config.update" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_io_config.devclrn" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_io_config.devpor" value="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_io_config.padtoinputregisterdelaysetting" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_io_config.outputdelaysetting1" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_io_config.outputdelaysetting2" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_io_config.dataout" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_io_config.dutycycledelaymode" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_io_config.dutycycledelaysettings" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_io_config.outputfinedelaysetting1" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_io_config.outputfinedelaysetting2" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_io_config.outputonlydelaysetting2" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_io_config.outputonlyfinedelaysetting2" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_io_config.padtoinputregisterfinedelaysetting" max="0e-12" min="0e-12"/>
            </pb_type>
            <interconnect>
              <complete input="io_cell.data_in" name="data_in" output="stratixiv_io_config.datain stratixiv_io_config.ena stratixiv_io_config.update stratixiv_io_config.devclrn stratixiv_io_config.devpor"/>
              <complete input="stratixiv_io_config.padtoinputregisterdelaysetting stratixiv_io_config.outputdelaysetting1 stratixiv_io_config.outputdelaysetting2 stratixiv_io_config.dataout stratixiv_io_config.dutycycledelaymode stratixiv_io_config.dutycycledelaysettings stratixiv_io_config.outputfinedelaysetting1 stratixiv_io_config.outputfinedelaysetting2 stratixiv_io_config.outputonlydelaysetting2 stratixiv_io_config.outputonlyfinedelaysetting2 stratixiv_io_config.padtoinputregisterfinedelaysetting" name="data_out" output="io_cell.data_out"/>
              <direct input="io_cell.clk" name="clock" output="stratixiv_io_config.clk"/>
            </interconnect>
          </mode>
          <mode name="stratixiv_pseudo_diff_out">
            <pb_type blif_model=".subckt stratixiv_pseudo_diff_out" name="stratixiv_pseudo_diff_out" num_pb="1">
              <input name="i" num_pins="1"/>
              <output name="o" num_pins="1"/>
              <output name="obar" num_pins="1"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_pseudo_diff_out.i" out_port="stratixiv_pseudo_diff_out.o stratixiv_pseudo_diff_out.obar"/>
            </pb_type>
            <interconnect>
              <complete input="io_cell.data_in" name="data_in" output="stratixiv_pseudo_diff_out.i"/>
              <complete input="stratixiv_pseudo_diff_out.o stratixiv_pseudo_diff_out.obar" name="data_out" output="io_cell.data_out"/>
            </interconnect>
          </mode>
          <mode name="stratixiv_termination">
            <pb_type blif_model=".subckt stratixiv_termination" name="stratixiv_termination" num_pb="1">
              <input name="otherserializerenable" num_pins="9"/>
              <input name="rdn" num_pins="1"/>
              <input name="rup" num_pins="1"/>
              <input name="scanen" num_pins="1"/>
              <input name="scanin" num_pins="1"/>
              <input name="serializerenable" num_pins="1"/>
              <input name="terminationclear" num_pins="1"/>
              <input name="terminationclock" num_pins="1"/>
              <input name="terminationcontrolin" num_pins="1"/>
              <input name="terminationenable" num_pins="1"/>
              <input name="devpor" num_pins="1"/>
              <input name="devclrn" num_pins="1"/>
              <output name="incrdn" num_pins="1"/>
              <output name="incrup" num_pins="1"/>
              <output name="scanout" num_pins="1"/>
              <output name="serializerenableout" num_pins="1"/>
              <output name="shiftregisterprobe" num_pins="1"/>
              <output name="terminationcontrol" num_pins="1"/>
              <output name="terminationcontrolprobe" num_pins="1"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_termination.otherserializerenable" out_port="stratixiv_termination.incrdn stratixiv_termination.incrup stratixiv_termination.scanout stratixiv_termination.serializerenableout stratixiv_termination.shiftregisterprobe stratixiv_termination.terminationcontrol stratixiv_termination.terminationcontrolprobe"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_termination.rdn" out_port="stratixiv_termination.incrdn stratixiv_termination.incrup stratixiv_termination.scanout stratixiv_termination.serializerenableout stratixiv_termination.shiftregisterprobe stratixiv_termination.terminationcontrol stratixiv_termination.terminationcontrolprobe"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_termination.rup" out_port="stratixiv_termination.incrdn stratixiv_termination.incrup stratixiv_termination.scanout stratixiv_termination.serializerenableout stratixiv_termination.shiftregisterprobe stratixiv_termination.terminationcontrol stratixiv_termination.terminationcontrolprobe"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_termination.scanen" out_port="stratixiv_termination.incrdn stratixiv_termination.incrup stratixiv_termination.scanout stratixiv_termination.serializerenableout stratixiv_termination.shiftregisterprobe stratixiv_termination.terminationcontrol stratixiv_termination.terminationcontrolprobe"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_termination.scanin" out_port="stratixiv_termination.incrdn stratixiv_termination.incrup stratixiv_termination.scanout stratixiv_termination.serializerenableout stratixiv_termination.shiftregisterprobe stratixiv_termination.terminationcontrol stratixiv_termination.terminationcontrolprobe"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_termination.serializerenable" out_port="stratixiv_termination.incrdn stratixiv_termination.incrup stratixiv_termination.scanout stratixiv_termination.serializerenableout stratixiv_termination.shiftregisterprobe stratixiv_termination.terminationcontrol stratixiv_termination.terminationcontrolprobe"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_termination.terminationclear" out_port="stratixiv_termination.incrdn stratixiv_termination.incrup stratixiv_termination.scanout stratixiv_termination.serializerenableout stratixiv_termination.shiftregisterprobe stratixiv_termination.terminationcontrol stratixiv_termination.terminationcontrolprobe"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_termination.terminationclock" out_port="stratixiv_termination.incrdn stratixiv_termination.incrup stratixiv_termination.scanout stratixiv_termination.serializerenableout stratixiv_termination.shiftregisterprobe stratixiv_termination.terminationcontrol stratixiv_termination.terminationcontrolprobe"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_termination.terminationcontrolin" out_port="stratixiv_termination.incrdn stratixiv_termination.incrup stratixiv_termination.scanout stratixiv_termination.serializerenableout stratixiv_termination.shiftregisterprobe stratixiv_termination.terminationcontrol stratixiv_termination.terminationcontrolprobe"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_termination.terminationenable" out_port="stratixiv_termination.incrdn stratixiv_termination.incrup stratixiv_termination.scanout stratixiv_termination.serializerenableout stratixiv_termination.shiftregisterprobe stratixiv_termination.terminationcontrol stratixiv_termination.terminationcontrolprobe"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_termination.devpor" out_port="stratixiv_termination.incrdn stratixiv_termination.incrup stratixiv_termination.scanout stratixiv_termination.serializerenableout stratixiv_termination.shiftregisterprobe stratixiv_termination.terminationcontrol stratixiv_termination.terminationcontrolprobe"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_termination.devclrn" out_port="stratixiv_termination.incrdn stratixiv_termination.incrup stratixiv_termination.scanout stratixiv_termination.serializerenableout stratixiv_termination.shiftregisterprobe stratixiv_termination.terminationcontrol stratixiv_termination.terminationcontrolprobe"/>
            </pb_type>
            <interconnect>
              <complete input="io_cell.data_in" name="data_in" output="stratixiv_termination.otherserializerenable stratixiv_termination.rdn stratixiv_termination.rup stratixiv_termination.scanen stratixiv_termination.scanin stratixiv_termination.serializerenable stratixiv_termination.terminationclear stratixiv_termination.terminationclock stratixiv_termination.terminationcontrolin stratixiv_termination.terminationenable stratixiv_termination.devpor stratixiv_termination.devclrn"/>
              <complete input="stratixiv_termination.incrdn stratixiv_termination.incrup stratixiv_termination.scanout stratixiv_termination.serializerenableout stratixiv_termination.shiftregisterprobe stratixiv_termination.terminationcontrol stratixiv_termination.terminationcontrolprobe" name="data_out" output="io_cell.data_out"/>
            </interconnect>
          </mode>
          <mode name="stratixiv_termination_logic">
            <pb_type blif_model=".subckt stratixiv_termination_logic" name="stratixiv_termination_logic" num_pb="1">
              <input name="serialloadenable" num_pins="1"/>
              <input name="terminationclock" num_pins="1"/>
              <input name="parallelloadenable" num_pins="1"/>
              <input name="terminationdata" num_pins="1"/>
              <input name="devpor" num_pins="1"/>
              <input name="devclrn" num_pins="1"/>
              <output name="seriesterminationcontrol" num_pins="14"/>
              <output name="parallelterminationcontrol" num_pins="14"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_termination_logic.serialloadenable" out_port="stratixiv_termination_logic.seriesterminationcontrol stratixiv_termination_logic.parallelterminationcontrol"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_termination_logic.terminationclock" out_port="stratixiv_termination_logic.seriesterminationcontrol stratixiv_termination_logic.parallelterminationcontrol"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_termination_logic.parallelloadenable" out_port="stratixiv_termination_logic.seriesterminationcontrol stratixiv_termination_logic.parallelterminationcontrol"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_termination_logic.terminationdata" out_port="stratixiv_termination_logic.seriesterminationcontrol stratixiv_termination_logic.parallelterminationcontrol"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_termination_logic.devpor" out_port="stratixiv_termination_logic.seriesterminationcontrol stratixiv_termination_logic.parallelterminationcontrol"/>
              <delay_constant max="0e-12" min="0e-12" in_port="stratixiv_termination_logic.devclrn" out_port="stratixiv_termination_logic.seriesterminationcontrol stratixiv_termination_logic.parallelterminationcontrol"/>
            </pb_type>
            <interconnect>
              <complete input="io_cell.data_in" name="data_in" output="stratixiv_termination_logic.serialloadenable stratixiv_termination_logic.terminationclock stratixiv_termination_logic.parallelloadenable stratixiv_termination_logic.terminationdata stratixiv_termination_logic.devpor stratixiv_termination_logic.devclrn"/>
              <complete input="stratixiv_termination_logic.seriesterminationcontrol stratixiv_termination_logic.parallelterminationcontrol" name="data_out" output="io_cell.data_out"/>
            </interconnect>
          </mode>
          <mode name="stratixiv_input_phase_alignment">
            <pb_type blif_model=".subckt stratixiv_input_phase_alignment" name="stratixiv_input_phase_alignment" num_pb="1">
              <input name="datain" num_pins="1"/>
              <input name="delayctrlin" num_pins="6"/>
              <input name="phasectrlin" num_pins="4"/>
              <input name="areset" num_pins="1"/>
              <input name="enainputcycledelay" num_pins="1"/>
              <input name="enaphasetransferreg" num_pins="1"/>
              <input name="phaseinvertctrl" num_pins="1"/>
              <input name="devclrn" num_pins="1"/>
              <input name="devpor" num_pins="1"/>
              <clock name="clk" num_pins="1"/>
              <output name="dataout" num_pins="1"/>
              <output name="dffin" num_pins="1"/>
              <output name="dff1t" num_pins="1"/>
              <T_setup clock="clk" port="stratixiv_input_phase_alignment.datain" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_input_phase_alignment.delayctrlin" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_input_phase_alignment.phasectrlin" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_input_phase_alignment.areset" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_input_phase_alignment.enainputcycledelay" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_input_phase_alignment.enaphasetransferreg" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_input_phase_alignment.phaseinvertctrl" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_input_phase_alignment.devclrn" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_input_phase_alignment.devpor" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_input_phase_alignment.datain" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_input_phase_alignment.delayctrlin" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_input_phase_alignment.phasectrlin" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_input_phase_alignment.areset" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_input_phase_alignment.enainputcycledelay" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_input_phase_alignment.enaphasetransferreg" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_input_phase_alignment.phaseinvertctrl" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_input_phase_alignment.devclrn" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_input_phase_alignment.devpor" value="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_input_phase_alignment.dataout" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_input_phase_alignment.dffin" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_input_phase_alignment.dff1t" max="0e-12" min="0e-12"/>
            </pb_type>
            <interconnect>
              <complete input="io_cell.data_in" name="data_in" output="stratixiv_input_phase_alignment.datain stratixiv_input_phase_alignment.delayctrlin stratixiv_input_phase_alignment.phasectrlin stratixiv_input_phase_alignment.areset stratixiv_input_phase_alignment.enainputcycledelay stratixiv_input_phase_alignment.enaphasetransferreg stratixiv_input_phase_alignment.phaseinvertctrl stratixiv_input_phase_alignment.devclrn stratixiv_input_phase_alignment.devpor"/>
              <complete input="stratixiv_input_phase_alignment.dataout stratixiv_input_phase_alignment.dffin stratixiv_input_phase_alignment.dff1t" name="data_out" output="io_cell.data_out"/>
              <direct input="io_cell.clk" name="clock" output="stratixiv_input_phase_alignment.clk"/>
            </interconnect>
          </mode>
          <mode name="stratixiv_output_phase_alignment">
            <pb_type blif_model=".subckt stratixiv_output_phase_alignment" name="stratixiv_output_phase_alignment" num_pb="1">
              <input name="datain" num_pins="2"/>
              <input name="delayctrlin" num_pins="6"/>
              <input name="phasectrlin" num_pins="4"/>
              <input name="areset" num_pins="1"/>
              <input name="enaoutputcycledelay" num_pins="1"/>
              <input name="enaphasetransferreg" num_pins="1"/>
              <input name="phaseinvertctrl" num_pins="1"/>
              <input name="devclrn" num_pins="1"/>
              <input name="devpor" num_pins="1"/>
              <clock name="clk" num_pins="1"/>
              <output name="dataout" num_pins="1"/>
              <output name="dffin" num_pins="1"/>
              <output name="dff1t" num_pins="1"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment.datain" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment.delayctrlin" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment.phasectrlin" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment.areset" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment.enaoutputcycledelay" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment.enaphasetransferreg" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment.phaseinvertctrl" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment.devclrn" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment.devpor" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment.datain" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment.delayctrlin" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment.phasectrlin" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment.areset" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment.enaoutputcycledelay" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment.enaphasetransferreg" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment.phaseinvertctrl" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment.devclrn" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment.devpor" value="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_output_phase_alignment.dataout" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_output_phase_alignment.dffin" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_output_phase_alignment.dff1t" max="0e-12" min="0e-12"/>
            </pb_type>
            <interconnect>
              <complete input="io_cell.data_in" name="data_in" output="stratixiv_output_phase_alignment.datain stratixiv_output_phase_alignment.delayctrlin stratixiv_output_phase_alignment.phasectrlin stratixiv_output_phase_alignment.areset stratixiv_output_phase_alignment.enaoutputcycledelay stratixiv_output_phase_alignment.enaphasetransferreg stratixiv_output_phase_alignment.phaseinvertctrl stratixiv_output_phase_alignment.devclrn stratixiv_output_phase_alignment.devpor"/>
              <complete input="stratixiv_output_phase_alignment.dataout stratixiv_output_phase_alignment.dffin stratixiv_output_phase_alignment.dff1t" name="data_out" output="io_cell.data_out"/>
              <direct input="io_cell.clk" name="clock" output="stratixiv_output_phase_alignment.clk"/>
            </interconnect>
          </mode>
          <mode name="stratixiv_output_phase_alignment_ddio_out">
            <pb_type blif_model=".subckt stratixiv_output_phase_alignment.opmode{ddio_out}" name="stratixiv_output_phase_alignment_ddio_out" num_pb="1">
              <input name="datain" num_pins="2"/>
              <input name="delayctrlin" num_pins="6"/>
              <input name="phasectrlin" num_pins="4"/>
              <input name="areset" num_pins="1"/>
              <input name="enaoutputcycledelay" num_pins="1"/>
              <input name="enaphasetransferreg" num_pins="1"/>
              <input name="phaseinvertctrl" num_pins="1"/>
              <input name="devclrn" num_pins="1"/>
              <input name="devpor" num_pins="1"/>
              <clock name="clk" num_pins="1"/>
              <output name="dataout" num_pins="1"/>
              <output name="dffin" num_pins="1"/>
              <output name="dff1t" num_pins="1"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_ddio_out.datain" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_ddio_out.delayctrlin" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_ddio_out.phasectrlin" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_ddio_out.areset" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_ddio_out.enaoutputcycledelay" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_ddio_out.enaphasetransferreg" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_ddio_out.phaseinvertctrl" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_ddio_out.devclrn" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_ddio_out.devpor" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_ddio_out.datain" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_ddio_out.delayctrlin" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_ddio_out.phasectrlin" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_ddio_out.areset" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_ddio_out.enaoutputcycledelay" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_ddio_out.enaphasetransferreg" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_ddio_out.phaseinvertctrl" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_ddio_out.devclrn" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_ddio_out.devpor" value="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_output_phase_alignment_ddio_out.dataout" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_output_phase_alignment_ddio_out.dffin" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_output_phase_alignment_ddio_out.dff1t" max="0e-12" min="0e-12"/>
            </pb_type>
            <interconnect>
              <complete input="io_cell.data_in" name="data_in" output="stratixiv_output_phase_alignment_ddio_out.datain stratixiv_output_phase_alignment_ddio_out.delayctrlin stratixiv_output_phase_alignment_ddio_out.phasectrlin stratixiv_output_phase_alignment_ddio_out.areset stratixiv_output_phase_alignment_ddio_out.enaoutputcycledelay stratixiv_output_phase_alignment_ddio_out.enaphasetransferreg stratixiv_output_phase_alignment_ddio_out.phaseinvertctrl stratixiv_output_phase_alignment_ddio_out.devclrn stratixiv_output_phase_alignment_ddio_out.devpor"/>
              <complete input="stratixiv_output_phase_alignment_ddio_out.dataout stratixiv_output_phase_alignment_ddio_out.dffin stratixiv_output_phase_alignment_ddio_out.dff1t" name="data_out" output="io_cell.data_out"/>
              <direct input="io_cell.clk" name="clock" output="stratixiv_output_phase_alignment_ddio_out.clk"/>
            </interconnect>
          </mode>
          <mode name="stratixiv_output_phase_alignment_ddio_in">
            <pb_type blif_model=".subckt stratixiv_output_phase_alignment.opmode{ddio_in}" name="stratixiv_output_phase_alignment_ddio_in" num_pb="1">
              <input name="datain" num_pins="2"/>
              <input name="delayctrlin" num_pins="6"/>
              <input name="phasectrlin" num_pins="4"/>
              <input name="areset" num_pins="1"/>
              <input name="enaoutputcycledelay" num_pins="1"/>
              <input name="enaphasetransferreg" num_pins="1"/>
              <input name="phaseinvertctrl" num_pins="1"/>
              <input name="devclrn" num_pins="1"/>
              <input name="devpor" num_pins="1"/>
              <clock name="clk" num_pins="1"/>
              <output name="dataout" num_pins="1"/>
              <output name="dffin" num_pins="1"/>
              <output name="dff1t" num_pins="1"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_ddio_in.datain" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_ddio_in.delayctrlin" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_ddio_in.phasectrlin" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_ddio_in.areset" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_ddio_in.enaoutputcycledelay" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_ddio_in.enaphasetransferreg" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_ddio_in.phaseinvertctrl" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_ddio_in.devclrn" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_ddio_in.devpor" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_ddio_in.datain" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_ddio_in.delayctrlin" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_ddio_in.phasectrlin" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_ddio_in.areset" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_ddio_in.enaoutputcycledelay" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_ddio_in.enaphasetransferreg" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_ddio_in.phaseinvertctrl" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_ddio_in.devclrn" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_ddio_in.devpor" value="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_output_phase_alignment_ddio_in.dataout" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_output_phase_alignment_ddio_in.dffin" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_output_phase_alignment_ddio_in.dff1t" max="0e-12" min="0e-12"/>
            </pb_type>
            <interconnect>
              <complete input="io_cell.data_in" name="data_in" output="stratixiv_output_phase_alignment_ddio_in.datain stratixiv_output_phase_alignment_ddio_in.delayctrlin stratixiv_output_phase_alignment_ddio_in.phasectrlin stratixiv_output_phase_alignment_ddio_in.areset stratixiv_output_phase_alignment_ddio_in.enaoutputcycledelay stratixiv_output_phase_alignment_ddio_in.enaphasetransferreg stratixiv_output_phase_alignment_ddio_in.phaseinvertctrl stratixiv_output_phase_alignment_ddio_in.devclrn stratixiv_output_phase_alignment_ddio_in.devpor"/>
              <complete input="stratixiv_output_phase_alignment_ddio_in.dataout stratixiv_output_phase_alignment_ddio_in.dffin stratixiv_output_phase_alignment_ddio_in.dff1t" name="data_out" output="io_cell.data_out"/>
              <direct input="io_cell.clk" name="clock" output="stratixiv_output_phase_alignment_ddio_in.clk"/>
            </interconnect>
          </mode>
          <mode name="stratixiv_output_phase_alignment_oe">
            <pb_type blif_model=".subckt stratixiv_output_phase_alignment.opmode{oe}" name="stratixiv_output_phase_alignment_oe" num_pb="1">
              <input name="datain" num_pins="2"/>
              <input name="delayctrlin" num_pins="6"/>
              <input name="phasectrlin" num_pins="4"/>
              <input name="areset" num_pins="1"/>
              <input name="enaoutputcycledelay" num_pins="1"/>
              <input name="enaphasetransferreg" num_pins="1"/>
              <input name="phaseinvertctrl" num_pins="1"/>
              <input name="devclrn" num_pins="1"/>
              <input name="devpor" num_pins="1"/>
              <clock name="clk" num_pins="1"/>
              <output name="dataout" num_pins="1"/>
              <output name="dffin" num_pins="1"/>
              <output name="dff1t" num_pins="1"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_oe.datain" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_oe.delayctrlin" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_oe.phasectrlin" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_oe.areset" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_oe.enaoutputcycledelay" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_oe.enaphasetransferreg" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_oe.phaseinvertctrl" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_oe.devclrn" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_oe.devpor" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_oe.datain" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_oe.delayctrlin" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_oe.phasectrlin" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_oe.areset" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_oe.enaoutputcycledelay" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_oe.enaphasetransferreg" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_oe.phaseinvertctrl" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_oe.devclrn" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_oe.devpor" value="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_output_phase_alignment_oe.dataout" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_output_phase_alignment_oe.dffin" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_output_phase_alignment_oe.dff1t" max="0e-12" min="0e-12"/>
            </pb_type>
            <interconnect>
              <complete input="io_cell.data_in" name="data_in" output="stratixiv_output_phase_alignment_oe.datain stratixiv_output_phase_alignment_oe.delayctrlin stratixiv_output_phase_alignment_oe.phasectrlin stratixiv_output_phase_alignment_oe.areset stratixiv_output_phase_alignment_oe.enaoutputcycledelay stratixiv_output_phase_alignment_oe.enaphasetransferreg stratixiv_output_phase_alignment_oe.phaseinvertctrl stratixiv_output_phase_alignment_oe.devclrn stratixiv_output_phase_alignment_oe.devpor"/>
              <complete input="stratixiv_output_phase_alignment_oe.dataout stratixiv_output_phase_alignment_oe.dffin stratixiv_output_phase_alignment_oe.dff1t" name="data_out" output="io_cell.data_out"/>
              <direct input="io_cell.clk" name="clock" output="stratixiv_output_phase_alignment_oe.clk"/>
            </interconnect>
          </mode>
          <mode name="stratixiv_output_phase_alignment_rtena">
            <pb_type blif_model=".subckt stratixiv_output_phase_alignment.opmode{rtena}" name="stratixiv_output_phase_alignment_rtena" num_pb="1">
              <input name="datain" num_pins="2"/>
              <input name="delayctrlin" num_pins="6"/>
              <input name="phasectrlin" num_pins="4"/>
              <input name="areset" num_pins="1"/>
              <input name="enaoutputcycledelay" num_pins="1"/>
              <input name="enaphasetransferreg" num_pins="1"/>
              <input name="phaseinvertctrl" num_pins="1"/>
              <input name="devclrn" num_pins="1"/>
              <input name="devpor" num_pins="1"/>
              <clock name="clk" num_pins="1"/>
              <output name="dataout" num_pins="1"/>
              <output name="dffin" num_pins="1"/>
              <output name="dff1t" num_pins="1"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_rtena.datain" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_rtena.delayctrlin" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_rtena.phasectrlin" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_rtena.areset" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_rtena.enaoutputcycledelay" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_rtena.enaphasetransferreg" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_rtena.phaseinvertctrl" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_rtena.devclrn" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_output_phase_alignment_rtena.devpor" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_rtena.datain" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_rtena.delayctrlin" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_rtena.phasectrlin" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_rtena.areset" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_rtena.enaoutputcycledelay" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_rtena.enaphasetransferreg" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_rtena.phaseinvertctrl" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_rtena.devclrn" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_output_phase_alignment_rtena.devpor" value="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_output_phase_alignment_rtena.dataout" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_output_phase_alignment_rtena.dffin" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_output_phase_alignment_rtena.dff1t" max="0e-12" min="0e-12"/>
            </pb_type>
            <interconnect>
              <complete input="io_cell.data_in" name="data_in" output="stratixiv_output_phase_alignment_rtena.datain stratixiv_output_phase_alignment_rtena.delayctrlin stratixiv_output_phase_alignment_rtena.phasectrlin stratixiv_output_phase_alignment_rtena.areset stratixiv_output_phase_alignment_rtena.enaoutputcycledelay stratixiv_output_phase_alignment_rtena.enaphasetransferreg stratixiv_output_phase_alignment_rtena.phaseinvertctrl stratixiv_output_phase_alignment_rtena.devclrn stratixiv_output_phase_alignment_rtena.devpor"/>
              <complete input="stratixiv_output_phase_alignment_rtena.dataout stratixiv_output_phase_alignment_rtena.dffin stratixiv_output_phase_alignment_rtena.dff1t" name="data_out" output="io_cell.data_out"/>
              <direct input="io_cell.clk" name="clock" output="stratixiv_output_phase_alignment_rtena.clk"/>
            </interconnect>
          </mode>
          <mode name="stratixiv_tsdblock">
            <pb_type blif_model=".subckt stratixiv_tsdblock" name="stratixiv_tsdblock" num_pb="1">
              <input name="ce" num_pins="1"/>
              <input name="clr" num_pins="1"/>
              <input name="fdbkctrlfromcore" num_pins="1"/>
              <input name="compouttest" num_pins="1"/>
              <input name="offset" num_pins="6"/>
              <input name="testin" num_pins="8"/>
              <clock name="clk" num_pins="1"/>
              <output name="tsdcaldone" num_pins="1"/>
              <output name="tsdcompout" num_pins="1"/>
              <output name="tsdcalo" num_pins="8"/>
              <output name="offsettout" num_pins="6"/>
              <T_setup clock="clk" port="stratixiv_tsdblock.ce" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_tsdblock.clr" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_tsdblock.fdbkctrlfromcore" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_tsdblock.compouttest" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_tsdblock.offset" value="0e-12"/>
              <T_setup clock="clk" port="stratixiv_tsdblock.testin" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_tsdblock.ce" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_tsdblock.clr" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_tsdblock.fdbkctrlfromcore" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_tsdblock.compouttest" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_tsdblock.offset" value="0e-12"/>
              <T_hold clock="clk" port="stratixiv_tsdblock.testin" value="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_tsdblock.tsdcaldone" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_tsdblock.tsdcompout" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_tsdblock.tsdcalo" max="0e-12" min="0e-12"/>
              <T_clock_to_Q clock="clk" port="stratixiv_tsdblock.offsettout" max="0e-12" min="0e-12"/>
            </pb_type>
            <interconnect>
              <complete input="io_cell.data_in" name="data_in" output="stratixiv_tsdblock.ce stratixiv_tsdblock.clr stratixiv_tsdblock.fdbkctrlfromcore stratixiv_tsdblock.compouttest stratixiv_tsdblock.offset stratixiv_tsdblock.testin"/>
              <complete input="stratixiv_tsdblock.tsdcaldone stratixiv_tsdblock.tsdcompout stratixiv_tsdblock.tsdcalo stratixiv_tsdblock.offsettout" name="data_out" output="io_cell.data_out"/>
              <direct input="io_cell.clk" name="clock" output="stratixiv_tsdblock.clk"/>
            </interconnect>
          </mode>
        </pb_type>
        <interconnect>
          <!-- core to IO-pad connections -->
          <complete input="io.core_in" name="drive_off_chip" output="pad.drive_off_chip">
            <!-- KEM: We have a single LAB_LINE delay coming from global routing into the IO pad 
                 in QII, typical max value: 177 ps, typical min value: 88 ps -->
            <delay_constant max="177e-12" min="88e-12" in_port="io.core_in" out_port="pad.drive_off_chip"/>
          </complete>
          <complete input="pad.recieve_off_chip" name="recieve_off_chip" output="io.core_out"/>
          <!-- io_cell connections -->
          <complete input="pad.recieve_off_chip io.core_in io_cell.data_out" name="io_cell_inputs" output="io_cell.data_in"/>
          <complete input="io_cell.data_out" name="io_cell_outputs" output="io.core_out pad.drive_off_chip"/>
          <complete input="io.clk" name="io_cell_clks" output="io_cell.clk"/>
        </interconnect>
      </mode>
    </pb_type>
    <pb_type name="PLL">
      <input name="in_signal" num_pins="14"/>
      <clock name="in_clock" num_pins="2"/>
      <output name="out_clock" num_pins="10"/>
      <output name="out_signal" num_pins="10"/>
      <mode name="NO_OP">
        <pb_type blif_model=".subckt stratixiv_pll" name="pll_no_op" num_pb="1">
          <input name="areset" num_pins="1"/>
          <input name="clkswitch" num_pins="1"/>
          <input name="configupdate" num_pins="1"/>
          <input name="fbin" num_pins="1"/>
          <input name="pfdena" num_pins="1"/>
          <input name="phasecounterselect" num_pins="4"/>
          <input name="phasestep" num_pins="1"/>
          <input name="phaseupdown" num_pins="1"/>
          <input name="scanclk" num_pins="1"/>
          <input name="scanclkena" num_pins="1"/>
          <input name="scandata" num_pins="1"/>
          <clock name="inclk" num_pins="1"/>
          <output name="activeclock" num_pins="1"/>
          <output name="clkbad" num_pins="2"/>
          <output name="fbout" num_pins="1"/>
          <output name="locked" num_pins="1"/>
          <output name="phasedone" num_pins="1"/>
          <output name="scandataout" num_pins="1"/>
          <output name="scandone" num_pins="1"/>
          <output name="vcooverrange" num_pins="1"/>
          <output name="vcounderrange" num_pins="1"/>
          <output name="clk" num_pins="10"/>
          <T_setup value="0e-12" port="pll_no_op.areset" clock="inclk"/>
          <T_setup value="0e-12" port="pll_no_op.clkswitch" clock="inclk"/>
          <T_setup value="0e-12" port="pll_no_op.configupdate" clock="inclk"/>
          <T_setup value="0e-12" port="pll_no_op.fbin" clock="inclk"/>
          <T_setup value="0e-12" port="pll_no_op.pfdena" clock="inclk"/>
          <T_setup value="0e-12" port="pll_no_op.phasecounterselect" clock="inclk"/>
          <T_setup value="0e-12" port="pll_no_op.phasestep" clock="inclk"/>
          <T_setup value="0e-12" port="pll_no_op.phaseupdown" clock="inclk"/>
          <T_setup value="0e-12" port="pll_no_op.scanclk" clock="inclk"/>
          <T_setup value="0e-12" port="pll_no_op.scanclkena" clock="inclk"/>
          <T_setup value="0e-12" port="pll_no_op.scandata" clock="inclk"/>
          <T_hold value="0e-12" port="pll_no_op.areset" clock="inclk"/>
          <T_hold value="0e-12" port="pll_no_op.clkswitch" clock="inclk"/>
          <T_hold value="0e-12" port="pll_no_op.configupdate" clock="inclk"/>
          <T_hold value="0e-12" port="pll_no_op.fbin" clock="inclk"/>
          <T_hold value="0e-12" port="pll_no_op.pfdena" clock="inclk"/>
          <T_hold value="0e-12" port="pll_no_op.phasecounterselect" clock="inclk"/>
          <T_hold value="0e-12" port="pll_no_op.phasestep" clock="inclk"/>
          <T_hold value="0e-12" port="pll_no_op.phaseupdown" clock="inclk"/>
          <T_hold value="0e-12" port="pll_no_op.scanclk" clock="inclk"/>
          <T_hold value="0e-12" port="pll_no_op.scanclkena" clock="inclk"/>
          <T_hold value="0e-12" port="pll_no_op.scandata" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_no_op.activeclock" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_no_op.clkbad" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_no_op.fbout" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_no_op.locked" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_no_op.phasedone" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_no_op.scandataout" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_no_op.scandone" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_no_op.vcooverrange" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_no_op.vcounderrange" clock="inclk"/>
        </pb_type>
        <interconnect>
          <direct input="PLL.in_signal[0]" name="pll_signal_in0" output="pll_no_op.areset"/>
          <direct input="PLL.in_signal[1]" name="pll_signal_in1" output="pll_no_op.clkswitch"/>
          <direct input="PLL.in_signal[2]" name="pll_signal_in2" output="pll_no_op.configupdate"/>
          <direct input="PLL.in_signal[3]" name="pll_signal_in3" output="pll_no_op.fbin"/>
          <direct input="PLL.in_signal[4]" name="pll_signal_in4" output="pll_no_op.pfdena"/>
          <direct input="PLL.in_signal[8:5]" name="pll_signal_in5" output="pll_no_op.phasecounterselect"/>
          <direct input="PLL.in_signal[9]" name="pll_signal_in6" output="pll_no_op.phasestep"/>
          <direct input="PLL.in_signal[10]" name="pll_signal_in7" output="pll_no_op.phaseupdown"/>
          <direct input="PLL.in_signal[11]" name="pll_signal_in8" output="pll_no_op.scanclk"/>
          <direct input="PLL.in_signal[12]" name="pll_signal_in9" output="pll_no_op.scanclkena"/>
          <direct input="PLL.in_signal[13]" name="pll_signal_in10" output="pll_no_op.scandata"/>
          <direct input="pll_no_op.activeclock" name="pll_signal_out0" output="PLL.out_signal[0]"/>
          <direct input="pll_no_op.clkbad" name="pll_signal_out1" output="PLL.out_signal[2:1]"/>
          <direct input="pll_no_op.fbout" name="pll_signal_out2" output="PLL.out_signal[3]"/>
          <direct input="pll_no_op.locked" name="pll_signal_out3" output="PLL.out_signal[4]"/>
          <direct input="pll_no_op.phasedone" name="pll_signal_out4" output="PLL.out_signal[5]"/>
          <direct input="pll_no_op.scandataout" name="pll_signal_out5" output="PLL.out_signal[6]"/>
          <direct input="pll_no_op.scandone" name="pll_signal_out6" output="PLL.out_signal[7]"/>
          <direct input="pll_no_op.vcooverrange" name="pll_signal_out7" output="PLL.out_signal[8]"/>
          <direct input="pll_no_op.vcounderrange" name="pll_signal_out8" output="PLL.out_signal[9]"/>
          <direct input="pll_no_op.clk" name="pll_clk_out" output="PLL.out_clock"/>
          <complete input="PLL.in_clock" name="pll_clk_in" output="pll_no_op.inclk"/>
        </interconnect>
      </mode>
      <mode name="normal">
        <pb_type blif_model=".subckt stratixiv_pll.opmode{normal}" name="pll_normal" num_pb="1">
          <input name="areset" num_pins="1"/>
          <input name="clkswitch" num_pins="1"/>
          <input name="configupdate" num_pins="1"/>
          <input name="fbin" num_pins="1"/>
          <input name="pfdena" num_pins="1"/>
          <input name="phasecounterselect" num_pins="4"/>
          <input name="phasestep" num_pins="1"/>
          <input name="phaseupdown" num_pins="1"/>
          <input name="scanclk" num_pins="1"/>
          <input name="scanclkena" num_pins="1"/>
          <input name="scandata" num_pins="1"/>
          <clock name="inclk" num_pins="1"/>
          <output name="activeclock" num_pins="1"/>
          <output name="clkbad" num_pins="2"/>
          <output name="fbout" num_pins="1"/>
          <output name="locked" num_pins="1"/>
          <output name="phasedone" num_pins="1"/>
          <output name="scandataout" num_pins="1"/>
          <output name="scandone" num_pins="1"/>
          <output name="vcooverrange" num_pins="1"/>
          <output name="vcounderrange" num_pins="1"/>
          <output name="clk" num_pins="10"/>
          <T_setup value="0e-12" port="pll_normal.areset" clock="inclk"/>
          <T_setup value="0e-12" port="pll_normal.clkswitch" clock="inclk"/>
          <T_setup value="0e-12" port="pll_normal.configupdate" clock="inclk"/>
          <T_setup value="0e-12" port="pll_normal.fbin" clock="inclk"/>
          <T_setup value="0e-12" port="pll_normal.pfdena" clock="inclk"/>
          <T_setup value="0e-12" port="pll_normal.phasecounterselect" clock="inclk"/>
          <T_setup value="0e-12" port="pll_normal.phasestep" clock="inclk"/>
          <T_setup value="0e-12" port="pll_normal.phaseupdown" clock="inclk"/>
          <T_setup value="0e-12" port="pll_normal.scanclk" clock="inclk"/>
          <T_setup value="0e-12" port="pll_normal.scanclkena" clock="inclk"/>
          <T_setup value="0e-12" port="pll_normal.scandata" clock="inclk"/>
          <T_hold value="0e-12" port="pll_normal.areset" clock="inclk"/>
          <T_hold value="0e-12" port="pll_normal.clkswitch" clock="inclk"/>
          <T_hold value="0e-12" port="pll_normal.configupdate" clock="inclk"/>
          <T_hold value="0e-12" port="pll_normal.fbin" clock="inclk"/>
          <T_hold value="0e-12" port="pll_normal.pfdena" clock="inclk"/>
          <T_hold value="0e-12" port="pll_normal.phasecounterselect" clock="inclk"/>
          <T_hold value="0e-12" port="pll_normal.phasestep" clock="inclk"/>
          <T_hold value="0e-12" port="pll_normal.phaseupdown" clock="inclk"/>
          <T_hold value="0e-12" port="pll_normal.scanclk" clock="inclk"/>
          <T_hold value="0e-12" port="pll_normal.scanclkena" clock="inclk"/>
          <T_hold value="0e-12" port="pll_normal.scandata" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_normal.activeclock" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_normal.clkbad" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_normal.fbout" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_normal.locked" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_normal.phasedone" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_normal.scandataout" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_normal.scandone" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_normal.vcooverrange" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_normal.vcounderrange" clock="inclk"/>
        </pb_type>
        <interconnect>
          <direct input="PLL.in_signal[0]" name="pll_signal_in0" output="pll_normal.areset"/>
          <direct input="PLL.in_signal[1]" name="pll_signal_in1" output="pll_normal.clkswitch"/>
          <direct input="PLL.in_signal[2]" name="pll_signal_in2" output="pll_normal.configupdate"/>
          <direct input="PLL.in_signal[3]" name="pll_signal_in3" output="pll_normal.fbin"/>
          <direct input="PLL.in_signal[4]" name="pll_signal_in4" output="pll_normal.pfdena"/>
          <direct input="PLL.in_signal[8:5]" name="pll_signal_in5" output="pll_normal.phasecounterselect"/>
          <direct input="PLL.in_signal[9]" name="pll_signal_in6" output="pll_normal.phasestep"/>
          <direct input="PLL.in_signal[10]" name="pll_signal_in7" output="pll_normal.phaseupdown"/>
          <direct input="PLL.in_signal[11]" name="pll_signal_in8" output="pll_normal.scanclk"/>
          <direct input="PLL.in_signal[12]" name="pll_signal_in9" output="pll_normal.scanclkena"/>
          <direct input="PLL.in_signal[13]" name="pll_signal_in10" output="pll_normal.scandata"/>
          <direct input="pll_normal.activeclock" name="pll_signal_out0" output="PLL.out_signal[0]"/>
          <direct input="pll_normal.clkbad" name="pll_signal_out1" output="PLL.out_signal[2:1]"/>
          <direct input="pll_normal.fbout" name="pll_signal_out2" output="PLL.out_signal[3]"/>
          <direct input="pll_normal.locked" name="pll_signal_out3" output="PLL.out_signal[4]"/>
          <direct input="pll_normal.phasedone" name="pll_signal_out4" output="PLL.out_signal[5]"/>
          <direct input="pll_normal.scandataout" name="pll_signal_out5" output="PLL.out_signal[6]"/>
          <direct input="pll_normal.scandone" name="pll_signal_out6" output="PLL.out_signal[7]"/>
          <direct input="pll_normal.vcooverrange" name="pll_signal_out7" output="PLL.out_signal[8]"/>
          <direct input="pll_normal.vcounderrange" name="pll_signal_out8" output="PLL.out_signal[9]"/>
          <direct input="pll_normal.clk" name="pll_clk_out" output="PLL.out_clock"/>
          <complete input="PLL.in_clock" name="pll_clk_in" output="pll_normal.inclk"/>
        </interconnect>
      </mode>
      <mode name="no_compensation">
        <pb_type blif_model=".subckt stratixiv_pll.opmode{no_compensation}" name="pll_no_compensation" num_pb="1">
          <input name="areset" num_pins="1"/>
          <input name="clkswitch" num_pins="1"/>
          <input name="configupdate" num_pins="1"/>
          <input name="fbin" num_pins="1"/>
          <input name="pfdena" num_pins="1"/>
          <input name="phasecounterselect" num_pins="4"/>
          <input name="phasestep" num_pins="1"/>
          <input name="phaseupdown" num_pins="1"/>
          <input name="scanclk" num_pins="1"/>
          <input name="scanclkena" num_pins="1"/>
          <input name="scandata" num_pins="1"/>
          <clock name="inclk" num_pins="1"/>
          <output name="activeclock" num_pins="1"/>
          <output name="clkbad" num_pins="2"/>
          <output name="fbout" num_pins="1"/>
          <output name="locked" num_pins="1"/>
          <output name="phasedone" num_pins="1"/>
          <output name="scandataout" num_pins="1"/>
          <output name="scandone" num_pins="1"/>
          <output name="vcooverrange" num_pins="1"/>
          <output name="vcounderrange" num_pins="1"/>
          <output name="clk" num_pins="10"/>
          <T_setup value="0e-12" port="pll_no_compensation.areset" clock="inclk"/>
          <T_setup value="0e-12" port="pll_no_compensation.clkswitch" clock="inclk"/>
          <T_setup value="0e-12" port="pll_no_compensation.configupdate" clock="inclk"/>
          <T_setup value="0e-12" port="pll_no_compensation.fbin" clock="inclk"/>
          <T_setup value="0e-12" port="pll_no_compensation.pfdena" clock="inclk"/>
          <T_setup value="0e-12" port="pll_no_compensation.phasecounterselect" clock="inclk"/>
          <T_setup value="0e-12" port="pll_no_compensation.phasestep" clock="inclk"/>
          <T_setup value="0e-12" port="pll_no_compensation.phaseupdown" clock="inclk"/>
          <T_setup value="0e-12" port="pll_no_compensation.scanclk" clock="inclk"/>
          <T_setup value="0e-12" port="pll_no_compensation.scanclkena" clock="inclk"/>
          <T_setup value="0e-12" port="pll_no_compensation.scandata" clock="inclk"/>
          <T_hold value="0e-12" port="pll_no_compensation.areset" clock="inclk"/>
          <T_hold value="0e-12" port="pll_no_compensation.clkswitch" clock="inclk"/>
          <T_hold value="0e-12" port="pll_no_compensation.configupdate" clock="inclk"/>
          <T_hold value="0e-12" port="pll_no_compensation.fbin" clock="inclk"/>
          <T_hold value="0e-12" port="pll_no_compensation.pfdena" clock="inclk"/>
          <T_hold value="0e-12" port="pll_no_compensation.phasecounterselect" clock="inclk"/>
          <T_hold value="0e-12" port="pll_no_compensation.phasestep" clock="inclk"/>
          <T_hold value="0e-12" port="pll_no_compensation.phaseupdown" clock="inclk"/>
          <T_hold value="0e-12" port="pll_no_compensation.scanclk" clock="inclk"/>
          <T_hold value="0e-12" port="pll_no_compensation.scanclkena" clock="inclk"/>
          <T_hold value="0e-12" port="pll_no_compensation.scandata" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_no_compensation.activeclock" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_no_compensation.clkbad" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_no_compensation.fbout" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_no_compensation.locked" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_no_compensation.phasedone" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_no_compensation.scandataout" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_no_compensation.scandone" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_no_compensation.vcooverrange" clock="inclk"/>
          <T_clock_to_Q max="0e-12" min="0e-12" port="pll_no_compensation.vcounderrange" clock="inclk"/>
        </pb_type>
        <interconnect>
          <direct input="PLL.in_signal[0]" name="pll_signal_in0" output="pll_no_compensation.areset"/>
          <direct input="PLL.in_signal[1]" name="pll_signal_in1" output="pll_no_compensation.clkswitch"/>
          <direct input="PLL.in_signal[2]" name="pll_signal_in2" output="pll_no_compensation.configupdate"/>
          <direct input="PLL.in_signal[3]" name="pll_signal_in3" output="pll_no_compensation.fbin"/>
          <direct input="PLL.in_signal[4]" name="pll_signal_in4" output="pll_no_compensation.pfdena"/>
          <direct input="PLL.in_signal[8:5]" name="pll_signal_in5" output="pll_no_compensation.phasecounterselect"/>
          <direct input="PLL.in_signal[9]" name="pll_signal_in6" output="pll_no_compensation.phasestep"/>
          <direct input="PLL.in_signal[10]" name="pll_signal_in7" output="pll_no_compensation.phaseupdown"/>
          <direct input="PLL.in_signal[11]" name="pll_signal_in8" output="pll_no_compensation.scanclk"/>
          <direct input="PLL.in_signal[12]" name="pll_signal_in9" output="pll_no_compensation.scanclkena"/>
          <direct input="PLL.in_signal[13]" name="pll_signal_in10" output="pll_no_compensation.scandata"/>
          <direct input="pll_no_compensation.activeclock" name="pll_signal_out0" output="PLL.out_signal[0]"/>
          <direct input="pll_no_compensation.clkbad" name="pll_signal_out1" output="PLL.out_signal[2:1]"/>
          <direct input="pll_no_compensation.fbout" name="pll_signal_out2" output="PLL.out_signal[3]"/>
          <direct input="pll_no_compensation.locked" name="pll_signal_out3" output="PLL.out_signal[4]"/>
          <direct input="pll_no_compensation.phasedone" name="pll_signal_out4" output="PLL.out_signal[5]"/>
          <direct input="pll_no_compensation.scandataout" name="pll_signal_out5" output="PLL.out_signal[6]"/>
          <direct input="pll_no_compensation.scandone" name="pll_signal_out6" output="PLL.out_signal[7]"/>
          <direct input="pll_no_compensation.vcooverrange" name="pll_signal_out7" output="PLL.out_signal[8]"/>
          <direct input="pll_no_compensation.vcounderrange" name="pll_signal_out8" output="PLL.out_signal[9]"/>
          <direct input="pll_no_compensation.clk" name="pll_clk_out" output="PLL.out_clock"/>
          <complete input="PLL.in_clock" name="pll_clk_in" output="pll_no_compensation.inclk"/>
        </interconnect>
      </mode>
    </pb_type>
    <pb_type name="LAB">
      <input name="data_in" num_pins="80" equivalent="full"/>
      <input name="control_in" num_pins="7" equivalent="full"/>
      <input name="cin" num_pins="1" equivalent="none"/>
      <input name="sharein" num_pins="1" equivalent="none"/>
      <output name="data_out" num_pins="40" equivalent="instance"/>
      <output name="cout" num_pins="1" equivalent="none"/>
      <output name="shareout" num_pins="1" equivalent="none"/>
      <clock name="clk" num_pins="2"/>
      <mode name="LAB">
        <pb_type name="alm" num_pb="10">
          <input name="data_in" num_pins="8"/>
          <input name="control" num_pins="7"/>
          <input name="cin" num_pins="1"/>
          <input name="sharein" num_pins="1"/>
          <output name="data_out" num_pins="6"/>
          <output name="cout" num_pins="1"/>
          <output name="shareout" num_pins="1"/>
          <clock name="clock" num_pins="2"/>
          <mode name="alm">
            <pb_type name="lut" num_pb="2">
              <input name="lin" num_pins="7"/>
              <input name="cin" num_pins="1"/>
              <input name="sharein" num_pins="1"/>
              <output name="lout" num_pins="2"/>
              <output name="cout" num_pins="1"/>
              <output name="shareout" num_pins="1"/>
              <mode name="stratixiv_lcell">
                <pb_type blif_model=".subckt stratixiv_lcell_comb" name="lcell_comb" num_pb="1">
                  <input name="dataa" num_pins="1"/>
                  <input name="datab" num_pins="1"/>
                  <input name="datac" num_pins="1"/>
                  <input name="datad" num_pins="1"/>
                  <input name="datae" num_pins="1"/>
                  <input name="dataf" num_pins="1"/>
                  <input name="datag" num_pins="1"/>
                  <input name="cin" num_pins="1"/>
                  <input name="sharein" num_pins="1"/>
                  <output name="combout" num_pins="1"/>
                  <output name="sumout" num_pins="1"/>
                  <output name="cout" num_pins="1"/>
                  <output name="shareout" num_pins="1"/>
                  <!-- These are the physical minimum and maximum delay inputs on a Stratix IV LUT to the combout ouptut. 
                       However, since VPR cannot do LUT rebalancing, we instead take the average of 
                       these numbers to get more stable results

                       From QII:
                        datag: 
                        	max: 183e-12 //datag is a special case it is only used in extended LUT mode
                        	min: 176e-12
                        dataf: 
                        	max: 82e-12,64e-12,70e-12
                        	min: 64e-12
                        datae: 
                        	max: 173e-12
                        	min: 136e-12, 132e-12
                        datad: 
                        	max: 213e-12,286e-12
                        	min: 176e-12
                        datac: 
                        	max: 320e-12,263e-12,291e-12,239e-12,205e-12
                        	min: 175e-12
                        datab: 
                        	max: 398e-12,339e-12
                        	min: 175e-12
                        dataa: 
                        	max: 402e-12,338e-12
                        	min: 321e-12

                       Max delays from VTR flagship arch:
                        dataf: 82e-12
                        datae: 173e-12
                        datad: 261e-12
                        datac: 263e-12
                        datab: 398e-12
                        dataa: 397e-12

                        Average value used: max: 261e-12 min: 193e-12
                    -->
                  <!-- Combinational LUT output delays -->
                  <delay_constant max="261e-12" min="193e-12" in_port="lcell_comb.dataa" out_port="lcell_comb.combout"/>
                  <delay_constant max="261e-12" min="193e-12" in_port="lcell_comb.datab" out_port="lcell_comb.combout"/>
                  <delay_constant max="261e-12" min="193e-12" in_port="lcell_comb.datac" out_port="lcell_comb.combout"/>
                  <delay_constant max="261e-12" min="193e-12" in_port="lcell_comb.datad" out_port="lcell_comb.combout"/>
                  <delay_constant max="261e-12" min="193e-12" in_port="lcell_comb.datae" out_port="lcell_comb.combout"/>
                  <delay_constant max="261e-12" min="193e-12" in_port="lcell_comb.dataf" out_port="lcell_comb.combout"/>
                  <delay_constant max="261e-12" min="193e-12" in_port="lcell_comb.datag" out_port="lcell_comb.combout"/>
                  <!-- Arithmetic output delays -->
                  <delay_constant max="491e-12" min="335e-12" in_port="lcell_comb.dataa" out_port="lcell_comb.sumout"/>
                  <delay_constant max="491e-12" min="335e-12" in_port="lcell_comb.datab" out_port="lcell_comb.sumout"/>
                  <delay_constant max="491e-12" min="335e-12" in_port="lcell_comb.datac" out_port="lcell_comb.sumout"/>
                  <delay_constant max="491e-12" min="335e-12" in_port="lcell_comb.datad" out_port="lcell_comb.sumout"/>
                  <delay_constant max="491e-12" min="335e-12" in_port="lcell_comb.dataf" out_port="lcell_comb.sumout"/>
                  <!-- Carry input to carry output delay -->
                  <delay_constant max="11e-12" min="8e-12" in_port="lcell_comb.cin" out_port="lcell_comb.cout"/>
                  <!-- Carry input to sumout delay 
                       
                       Observed max values in QII:
                         287e-12, 256e-12, 272e-12
                       Observed min values in QII:
                         200e-12, 228e-12
                       -->
                  <delay_constant max="287e-12" min="228e-12" in_port="lcell_comb.cin" out_port="lcell_comb.sumout"/>
                  <!-- Combinational LUT input to carry out delays 
                  -->
                  <delay_constant max="261e-12" min="193e-12" in_port="lcell_comb.dataa" out_port="lcell_comb.cout"/>
                  <delay_constant max="261e-12" min="193e-12" in_port="lcell_comb.datab" out_port="lcell_comb.cout"/>
                  <delay_constant max="261e-12" min="193e-12" in_port="lcell_comb.datac" out_port="lcell_comb.cout"/>
                  <delay_constant max="261e-12" min="193e-12" in_port="lcell_comb.datad" out_port="lcell_comb.cout"/>
                  <delay_constant max="261e-12" min="193e-12" in_port="lcell_comb.dataf" out_port="lcell_comb.cout"/>
                  <!-- Share input to combout delay -->
                  <!--   In Stratix IV Shared Arithmetic mode (the only mode that uses sharein/shareout)
                         the shareout is always generated by a LUT, so we should use LUT delays here
                         [See Shared Arithmetic Mode Section of Stratix IV Handbook or QUIP documentation].
                       -->
                  <delay_constant max="261e-12" min="223e-12" in_port="lcell_comb.sharein" out_port="lcell_comb.cout"/>
                  <delay_constant max="261e-12" min="223e-12" in_port="lcell_comb.sharein" out_port="lcell_comb.sumout"/>
                  <!-- Combinational LUT input to shareout delays -->
                  <!--   The shareout output is only driven by a 4-LUT (fractured part of a 6-LUT)
                         so it will be faster than the full 6-LUT

                         Typical values observed in QII:
                            max: 154e-12, 157e-12
                            min: 98e-12
                       -->
                  <delay_constant max="154e-12" min="98e-12" in_port="lcell_comb.dataa" out_port="lcell_comb.shareout"/>
                  <delay_constant max="154e-12" min="98e-12" in_port="lcell_comb.datab" out_port="lcell_comb.shareout"/>
                  <delay_constant max="154e-12" min="98e-12" in_port="lcell_comb.datac" out_port="lcell_comb.shareout"/>
                  <delay_constant max="154e-12" min="98e-12" in_port="lcell_comb.datad" out_port="lcell_comb.shareout"/>
                </pb_type>
                <interconnect>
                  <complete input="lut.lin" name="in_comp1" output="lcell_comb.dataa"/>
                  <complete input="lut.lin" name="in_comp2" output="lcell_comb.datab"/>
                  <complete input="lut.lin" name="in_comp3" output="lcell_comb.datac"/>
                  <complete input="lut.lin" name="in_comp4" output="lcell_comb.datad"/>
                  <complete input="lut.lin" name="in_comp5" output="lcell_comb.datae"/>
                  <complete input="lut.lin" name="in_comp6" output="lcell_comb.dataf"/>
                  <complete input="lut.lin" name="in_comp7" output="lcell_comb.datag"/>
                  <complete input="lcell_comb.combout" name="out_comp1" output="lut.lout"/>
                  <complete input="lcell_comb.sumout" name="out_comp2" output="lut.lout"/>
                  <!-- LUT carry chain -->
                  <direct input="lut.cin" name="lut_cin" output="lcell_comb.cin">
                    <pack_pattern name="LAB_carry_chain" in_port="lut.cin" out_port="lcell_comb.cin"/>
                  </direct>
                  <direct input="lcell_comb.cout" name="out_comp3" output="lut.cout">
                    <pack_pattern name="LAB_carry_chain" in_port="lcell_comb.cout" out_port="lut.cout"/>
                  </direct>
                  <!-- LUT share chain -->
                  <direct input="lut.sharein" name="lut_sharein" output="lcell_comb.sharein">
                    <pack_pattern name="share_chain" in_port="lut.sharein" out_port="lcell_comb.sharein"/>
                  </direct>
                  <direct input="lcell_comb.shareout" name="out_comp4" output="lut.shareout">
                    <pack_pattern name="share_chain" in_port="lcell_comb.shareout" out_port="lut.shareout"/>
                  </direct>
                </interconnect>
              </mode>
              <mode name="names_lut">
                <pb_type blif_model=".names" class="lut" name="lut6" num_pb="1">
                  <input name="in" num_pins="6" port_class="lut_in"/>
                  <output name="out" num_pins="1" port_class="lut_out"/>
                  <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
					261e-12
					261e-12
					261e-12
					261e-12
					261e-12
					261e-12
				  </delay_matrix>
                  <delay_matrix type="min" in_port="lut6.in" out_port="lut6.out">
					193e-12
					193e-12
					193e-12
					193e-12
					193e-12
					193e-12
				  </delay_matrix>
                </pb_type>
                <interconnect>
                  <complete input="lut.lin" name="l_complete1" output="lut6.in[5:0]"/>
                  <complete input="lut6.out" name="l_complete2" output="lut.lout"/>
                </interconnect>
              </mode>
            </pb_type>
            <pb_type name="dff" num_pb="2">
              <input name="prn" num_pins="1"/>
              <input name="clrn" num_pins="1"/>
              <input name="aload" num_pins="1"/>
              <input name="sload" num_pins="1"/>
              <input name="sclr" num_pins="1"/>
              <input name="devclrn" num_pins="1"/>
              <input name="devpor" num_pins="1"/>
              <input name="ena" num_pins="1"/>
              <input name="asdata" num_pins="1"/>
              <input name="d" num_pins="1"/>
              <output name="q" num_pins="1"/>
              <clock name="clk" num_pins="1"/>
              <mode name="stratixiv_dffeas">
                <pb_type blif_model=".subckt dffeas" name="dffeas" num_pb="1">
                  <input name="prn" num_pins="1"/>
                  <input name="clrn" num_pins="1"/>
                  <input name="aload" num_pins="1"/>
                  <input name="sload" num_pins="1"/>
                  <input name="sclr" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="ena" num_pins="1"/>
                  <input name="asdata" num_pins="1"/>
                  <input name="d" num_pins="1"/>
                  <output name="q" num_pins="1"/>
                  <clock name="clk" num_pins="1"/>
                  <T_setup value="66e-12" port="dffeas.d" clock="clk"/>
                  <T_setup value="66e-12" port="dffeas.prn" clock="clk"/>
                  <T_setup value="66e-12" port="dffeas.clrn" clock="clk"/>
                  <T_setup value="66e-12" port="dffeas.sload" clock="clk"/>
                  <T_setup value="66e-12" port="dffeas.sclr" clock="clk"/>
                  <T_setup value="66e-12" port="dffeas.devclrn" clock="clk"/>
                  <T_setup value="66e-12" port="dffeas.devpor" clock="clk"/>
                  <T_setup value="66e-12" port="dffeas.ena" clock="clk"/>
                  <T_hold value="37e-12" port="dffeas.d" clock="clk"/>
                  <T_hold value="37e-12" port="dffeas.prn" clock="clk"/>
                  <T_hold value="37e-12" port="dffeas.clrn" clock="clk"/>
                  <T_hold value="37e-12" port="dffeas.sload" clock="clk"/>
                  <T_hold value="37e-12" port="dffeas.sclr" clock="clk"/>
                  <T_hold value="37e-12" port="dffeas.devclrn" clock="clk"/>
                  <T_hold value="37e-12" port="dffeas.devpor" clock="clk"/>
                  <T_hold value="37e-12" port="dffeas.ena" clock="clk"/>
                  <!-- VPR does not analyze async removal/recover so we treat it as a lax setup constraint -->
                  <T_setup value="0e-12" port="dffeas.aload" clock="clk"/>
                  <T_setup value="0e-12" port="dffeas.asdata" clock="clk"/>
                  <T_hold value="0e-12" port="dffeas.aload" clock="clk"/>
                  <T_hold value="0e-12" port="dffeas.asdata" clock="clk"/>
                  <T_clock_to_Q max="42e-12" min="37e-12" port="dffeas.q" clock="clk"/>
                </pb_type>
                <interconnect>
                  <direct input="dff.prn" name="dffeas_prn" output="dffeas.prn"/>
                  <direct input="dff.clrn" name="dffeas_clrn" output="dffeas.clrn"/>
                  <direct input="dff.aload" name="dffeas_aload" output="dffeas.aload"/>
                  <direct input="dff.sload" name="dffeas_sload" output="dffeas.sload"/>
                  <direct input="dff.sclr" name="dffeas_sclr" output="dffeas.sclr"/>
                  <direct input="dff.devclrn" name="dffeas_devclrn" output="dffeas.devclrn"/>
                  <direct input="dff.devpor" name="dffeas_devpor" output="dffeas.devpor"/>
                  <direct input="dff.ena" name="dffeas_ena" output="dffeas.ena"/>
                  <direct input="dff.asdata" name="dffeas_asdata" output="dffeas.asdata"/>
                  <direct input="dff.d" name="dffeas_d" output="dffeas.d"/>
                  <direct input="dffeas.q" name="dffeas_q" output="dff.q"/>
                  <direct input="dff.clk" name="dffeas_clk" output="dffeas.clk"/>
                </interconnect>
              </mode>
              <mode name="latch">
                <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
                  <input name="D" num_pins="1" port_class="D"/>
                  <output name="Q" num_pins="1" port_class="Q"/>
                  <clock name="clk" num_pins="1" port_class="clock"/>
                  <T_setup value="66e-12" port="ff.D" clock="clk"/>
                  <T_hold value="37e-12" port="ff.D" clock="clk"/>
                  <T_clock_to_Q max="42e-12" min="37e-12" port="ff.Q" clock="clk"/>
                </pb_type>
                <interconnect>
                  <direct input="dff.d" name="ff_d" output="ff.D"/>
                  <direct input="ff.Q" name="ff_q" output="dff.q"/>
                  <direct input="dff.clk" name="ff_clk" output="ff.clk"/>
                </interconnect>
              </mode>
            </pb_type>
            <interconnect>
              <!-- ALM Inputs to LUTs and FFs -->
              <complete input="alm.data_in" name="in_comp1" output="lut[1:0].lin dff[1:0].d dff[1:0].ena dff[1:0].asdata"/>
              <!-- LUT Output to FFs and ALM Outputs-->
              <complete input="lut[0].lout" name="lut0_out" output="dff[0].d dff[0].ena dff[0].asdata alm.data_out">
                <delay_constant max="25e-12" min="24e-12" in_port="lut[0].lout" out_port="alm.data_out"/>
              </complete>
              <complete input="lut[1].lout" name="lut1_out" output="dff[1].d dff[1].ena dff[1].asdata alm.data_out">
                <delay_constant max="25e-12" min="24e-12" in_port="lut[1].lout" out_port="alm.data_out"/>
              </complete>
              <!-- FF Clocks -->
              <complete input="alm.clock" name="clock_dff0" output="dff[0].clk"/>
              <complete input="alm.clock" name="clock_dff1" output="dff[1].clk"/>
              <!-- FF ALM Output -->
              <complete input="dff[1:0].q" name="out_comp2" output="alm.data_out">
                <delay_constant max="45e-12" min="27e-12" in_port="dff[1:0].q" out_port="alm.data_out"/>
              </complete>
              <!-- ALM Carry Chain -->
              <direct input="alm.cin" name="alm_cin" output="lut[0].cin">
                <pack_pattern name="LAB_carry_chain" in_port="alm.cin" out_port="lut[0].cin"/>
              </direct>
              <direct input="lut[0].cout" name="lut_to_lut_carry" output="lut[1].cin">
                <pack_pattern name="LAB_carry_chain" in_port="lut[0].cout" out_port="lut[1].cin"/>
              </direct>
              <direct input="lut[1].cout" name="alm_cout" output="alm.cout">
                <pack_pattern name="LAB_carry_chain" in_port="lut[1].cout" out_port="alm.cout"/>
              </direct>
              <!-- ALM Share Chain -->
              <direct input="alm.sharein" name="alm_sharein" output="lut[0].sharein">
                <pack_pattern name="share_chain" in_port="alm.sharein" out_port="lut[0].sharein"/>
              </direct>
              <direct input="lut[0].shareout" name="lut_to_lut_share" output="lut[1].sharein">
                <pack_pattern name="share_chain" in_port="lut[0].shareout" out_port="lut[1].sharein"/>
              </direct>
              <direct input="lut[1].shareout" name="alm_shareout" output="alm.shareout">
                <pack_pattern name="share_chain" in_port="lut[1].shareout" out_port="alm.shareout"/>
              </direct>
              <!-- FF Control Signals -->
              <direct input="alm.control[0]" name="control_0_dff0" output="dff[0].prn"/>
              <direct input="alm.control[1]" name="control_1_dff0" output="dff[0].clrn"/>
              <direct input="alm.control[2]" name="control_2_dff0" output="dff[0].aload"/>
              <direct input="alm.control[3]" name="control_3_dff0" output="dff[0].sload"/>
              <direct input="alm.control[4]" name="control_4_dff0" output="dff[0].sclr"/>
              <direct input="alm.control[5]" name="control_5_dff0" output="dff[0].devclrn"/>
              <direct input="alm.control[6]" name="control_6_dff0" output="dff[0].devpor"/>
              <direct input="alm.control[0]" name="control_0_dff1" output="dff[1].prn"/>
              <direct input="alm.control[1]" name="control_1_dff1" output="dff[1].clrn"/>
              <direct input="alm.control[2]" name="control_2_dff1" output="dff[1].aload"/>
              <direct input="alm.control[3]" name="control_3_dff1" output="dff[1].sload"/>
              <direct input="alm.control[4]" name="control_4_dff1" output="dff[1].sclr"/>
              <direct input="alm.control[5]" name="control_5_dff1" output="dff[1].devclrn"/>
              <direct input="alm.control[6]" name="control_6_dff1" output="dff[1].devpor"/>
            </interconnect>
          </mode>
        </pb_type>
        <interconnect>
          <!--LAB-ALM Interconnect-->
          <!-- LAB Input: Global Routing to ALM inputs -->
          <complete input="LAB.data_in" name="LAB_datain" output="alm[9:0].data_in">
            <!-- The delay modeled here is the delay from global routing to the ALM inputs.
                   In QII the maximum delay varies from 121 ps to 258 ps.  Taking the average of the
                   values observed in QII we arrive at: 171 ps. The minimum delay ranges from 111 ps to 79 ps.
                   The average observed is: 104 ps-->
            <delay_constant max="171e-12" min="104e-12" in_port="LAB.data_in" out_port="alm[9:0].data_in"/>
          </complete>
          <!-- ALM feedback: two of six ALM outputs (one from each 1/2 ALM) feedback to the ALM inputs  -->
          <complete input="alm[9:0].data_out[0] alm[9:0].data_out[3]" name="LAB_alm_feedback" output="alm[9:0].data_in">
            <delay_constant max="75e-12" min="40e-12" in_port="alm[9:0].data_out[0] alm[9:0].data_out[3]" out_port="alm[9:0].data_in"/>
          </complete>
          <!-- ALM Outputs: directly drive global routing -->
          <complete input="alm[9:0].data_out[1:2] alm[9:0].data_out[4:5]" name="LAB_dataout" output="LAB.data_out"/>
          <!-- ALM Control Inputs -->
          <complete input="LAB.control_in" name="LAB_control" output="alm[9:0].control">
            <!-- The delay modeled here on the ALM control inputs consists of two components:
                    1) The LAB_SEC_MUX or LAB_CONTROL_MUX delay: 52 ps
                    2) The delay from the LAB_CONTROL_MUX to the ALM DFF: 385 ps 
                 Therefore the total delay modeled here is: (1) + (2) = 437 ps 

				 A similar calculation for the minimum delay results in:
                    1) The LAB_SEC_MUX or LAB_CONTROL_MUX delay: 48 ps
                    2) The delay from the LAB_CONTROL_MUX to the ALM DFF: 289 ps 
                 Therefore the total delay modeled here is: (1) + (2) = 333 ps 
					-->
            <delay_constant max="437e-12" min="333e-12" in_port="LAB.control_in" out_port="alm[9:0].control"/>
          </complete>
          <!-- LAB Clocks -->
          <complete input="LAB.clk" name="LAB_clock" output="alm[9:0].clock"/>
          <!-- LAB Carry Chain mid-point entry/exit points, this allows the chain to jump early to
               the next LAB, if the full chain would overuse the number of LAB inputs -->
          <!--<complete input="alm[4].cout" name="alm4_midpoint_exit_carry" output="LAB.data_out"/>-->
          <!--<complete input="LAB.data_in" name="alm5_midpoint_entry_carry" output="alm[5].cin"/>-->
          <!--LAB carry chain-->
          <direct input="LAB.cin" name="LAB_cin" output="alm[0].cin">
            <pack_pattern name="LAB_carry_chain" in_port="LAB.cin" out_port="alm[0].cin"/>
          </direct>
          <direct input="alm[0].cout" name="alm0_alm1_carry" output="alm[1].cin">
            <pack_pattern name="LAB_carry_chain" in_port="alm[0].cout" out_port="alm[1].cin"/>
          </direct>
          <direct input="alm[1].cout" name="alm1_alm2_carry" output="alm[2].cin">
            <pack_pattern name="LAB_carry_chain" in_port="alm[1].cout" out_port="alm[2].cin"/>
          </direct>
          <direct input="alm[2].cout" name="alm2_alm3_carry" output="alm[3].cin">
            <pack_pattern name="LAB_carry_chain" in_port="alm[2].cout" out_port="alm[3].cin"/>
          </direct>
          <direct input="alm[3].cout" name="alm3_alm4_carry" output="alm[4].cin">
            <pack_pattern name="LAB_carry_chain" in_port="alm[3].cout" out_port="alm[4].cin"/>
          </direct>
          <direct input="alm[4].cout" name="alm4_alm5_carry" output="alm[5].cin">
            <!--
                 - There is extra delay crossing from the 5th to 6th ALM in
                 - a LAB due to the extra distance (crossing control circuitry) and 
                 - the optional entry/exit mux at the mid-point of the carry chain.
                 - 
                 - From experiments with Quartus II the maximum delay is roughly 65ps, 
                 - since we already account for 11ps on the LUT we will account 
                 - for the remainder (55ps) here.

				 - Similarly, the value observed in QII for minimum delay is 53ps,
				 - Subtracting the 8ps on the LUT, we account for 45ps here.
                 -->
            <delay_constant max="55e-12" min="45e-12" in_port="alm[4].cout" out_port="alm[5].cin"/>
            <pack_pattern name="LAB_carry_chain" in_port="alm[4].cout" out_port="alm[5].cin"/>
          </direct>
          <direct input="alm[5].cout" name="alm5_alm6_carry" output="alm[6].cin">
            <pack_pattern name="LAB_carry_chain" in_port="alm[5].cout" out_port="alm[6].cin"/>
          </direct>
          <direct input="alm[6].cout" name="alm6_alm7_carry" output="alm[7].cin">
            <pack_pattern name="LAB_carry_chain" in_port="alm[6].cout" out_port="alm[7].cin"/>
          </direct>
          <direct input="alm[7].cout" name="alm7_alm8_carry" output="alm[8].cin">
            <pack_pattern name="LAB_carry_chain" in_port="alm[7].cout" out_port="alm[8].cin"/>
          </direct>
          <direct input="alm[8].cout" name="alm8_alm9_carry" output="alm[9].cin">
            <pack_pattern name="LAB_carry_chain" in_port="alm[8].cout" out_port="alm[9].cin"/>
          </direct>
          <direct input="alm[9].cout" name="LAB_cout" output="LAB.cout">
            <!--
                 - There is extra delay to enter and exit the LAB carry chain.  In Quartus II
                 - this delay is accounted for only on the output side.
                 - 
                 - From Quaruts II the maximum delay was found to be roughly 124ps and the
                 - minimum delay is roughly 107 ps
                 -->
            <delay_constant max="124e-12" min="107e-12" in_port="alm[9].cout" out_port="LAB.cout"/>
            <pack_pattern name="LAB_carry_chain" in_port="alm[9].cout" out_port="LAB.cout"/>
          </direct>
          <!-- LAB share chain 
               Note: No timing delays placed on share chain, so that critical path is
                     alwasy reported on carry chain. The share chain is only every used
                     in conjunction with the carry chain. -->
          <direct input="LAB.sharein" name="LAB_sharein" output="alm[0].sharein">
            <pack_pattern name="share_chain" in_port="LAB.sharein" out_port="alm[0].sharein"/>
          </direct>
          <direct input="alm[0].shareout" name="alm0_alm1_share" output="alm[1].sharein">
            <pack_pattern name="share_chain" in_port="alm[0].shareout" out_port="alm[1].sharein"/>
          </direct>
          <direct input="alm[1].shareout" name="alm1_alm2_share" output="alm[2].sharein">
            <pack_pattern name="share_chain" in_port="alm[1].shareout" out_port="alm[2].sharein"/>
          </direct>
          <direct input="alm[2].shareout" name="alm2_alm3_share" output="alm[3].sharein">
            <pack_pattern name="share_chain" in_port="alm[2].shareout" out_port="alm[3].sharein"/>
          </direct>
          <direct input="alm[3].shareout" name="alm3_alm4_share" output="alm[4].sharein">
            <pack_pattern name="share_chain" in_port="alm[3].shareout" out_port="alm[4].sharein"/>
          </direct>
          <direct input="alm[4].shareout" name="alm4_alm5_share" output="alm[5].sharein">
            <pack_pattern name="share_chain" in_port="alm[4].shareout" out_port="alm[5].sharein"/>
          </direct>
          <direct input="alm[5].shareout" name="alm5_alm6_share" output="alm[6].sharein">
            <pack_pattern name="share_chain" in_port="alm[5].shareout" out_port="alm[6].sharein"/>
          </direct>
          <direct input="alm[6].shareout" name="alm6_alm7_share" output="alm[7].sharein">
            <pack_pattern name="share_chain" in_port="alm[6].shareout" out_port="alm[7].sharein"/>
          </direct>
          <direct input="alm[7].shareout" name="alm7_alm8_share" output="alm[8].sharein">
            <pack_pattern name="share_chain" in_port="alm[7].shareout" out_port="alm[8].sharein"/>
          </direct>
          <direct input="alm[8].shareout" name="alm8_alm9_share" output="alm[9].sharein">
            <pack_pattern name="share_chain" in_port="alm[8].shareout" out_port="alm[9].sharein"/>
          </direct>
          <direct input="alm[9].shareout" name="LAB_shareout" output="LAB.shareout">
            <pack_pattern name="share_chain" in_port="alm[9].shareout" out_port="LAB.shareout"/>
          </direct>
        </interconnect>
      </mode>
      <mode name="MLAB">
        <pb_type name="mlab_cell" num_pb="1">
          <input name="ena0" num_pins="1"/>
          <input name="portaaddr" num_pins="14"/>
          <input name="portabyteenamasks" num_pins="8"/>
          <input name="portadatain" num_pins="36"/>
          <input name="portbaddr" num_pins="14"/>
          <clock name="clk0" num_pins="1"/>
          <output name="portbdataout" num_pins="36"/>
          <mode name="normal">
            <pb_type blif_model=".subckt stratixiv_mlab_cell" name="mlab_cell_clocked" num_pb="1">
              <input name="ena0" num_pins="1"/>
              <input name="portaaddr" num_pins="14"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portadatain" num_pins="36"/>
              <input name="portbaddr" num_pins="14"/>
              <clock name="clk0" num_pins="1"/>
              <output name="portbdataout" num_pins="36"/>
              <T_setup value="66e-12" port="mlab_cell_clocked.ena0" clock="clk0"/>
              <T_setup value="66e-12" port="mlab_cell_clocked.portaaddr" clock="clk0"/>
              <T_setup value="66e-12" port="mlab_cell_clocked.portabyteenamasks" clock="clk0"/>
              <T_setup value="66e-12" port="mlab_cell_clocked.portadatain" clock="clk0"/>
              <T_setup value="66e-12" port="mlab_cell_clocked.portbaddr" clock="clk0"/>
              <T_hold value="30e-12" port="mlab_cell_clocked.ena0" clock="clk0"/>
              <T_hold value="30e-12" port="mlab_cell_clocked.portaaddr" clock="clk0"/>
              <T_hold value="30e-12" port="mlab_cell_clocked.portabyteenamasks" clock="clk0"/>
              <T_hold value="30e-12" port="mlab_cell_clocked.portadatain" clock="clk0"/>
              <T_hold value="30e-12" port="mlab_cell_clocked.portbaddr" clock="clk0"/>
              <T_clock_to_Q max="124e-12" min="60e-12" port="mlab_cell_clocked.portbdataout" clock="clk0"/>
            </pb_type>
            <interconnect>
              <complete input="mlab_cell.ena0" name="ena0" output="mlab_cell_clocked.ena0"/>
              <complete input="mlab_cell.portaaddr" name="portaaddr" output="mlab_cell_clocked.portaaddr"/>
              <complete input="mlab_cell.portabyteenamasks" name="portabytenamasks" output="mlab_cell_clocked.portabyteenamasks"/>
              <complete input="mlab_cell.portadatain" name="portadatain" output="mlab_cell_clocked.portadatain"/>
              <complete input="mlab_cell.portbaddr" name="portabddr" output="mlab_cell_clocked.portbaddr"/>
              <complete input="mlab_cell_clocked.portbdataout" name="portbdataout" output="mlab_cell.portbdataout"/>
              <complete input="mlab_cell.clk0" name="clk0" output="mlab_cell_clocked.clk0"/>
            </interconnect>
          </mode>
          <mode name="ROM">
            <pb_type blif_model=".subckt stratixiv_mlab_cell.opmode{ROM}" name="mlab_cell_comb" num_pb="1">
              <input name="ena0" num_pins="1"/>
              <input name="portaaddr" num_pins="14"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portadatain" num_pins="36"/>
              <input name="portbaddr" num_pins="14"/>
              <clock name="clk0" num_pins="1"/>
              <output name="portbdataout" num_pins="36"/>
              <delay_constant max="261e-12" min="193e-12" in_port="mlab_cell_comb.ena0" out_port="mlab_cell_comb.portbdataout"/>
              <delay_constant max="261e-12" min="193e-12" in_port="mlab_cell_comb.portaaddr" out_port="mlab_cell_comb.portbdataout"/>
              <delay_constant max="261e-12" min="193e-12" in_port="mlab_cell_comb.portabyteenamasks" out_port="mlab_cell_comb.portbdataout"/>
              <delay_constant max="261e-12" min="193e-12" in_port="mlab_cell_comb.portadatain" out_port="mlab_cell_comb.portbdataout"/>
              <delay_constant max="261e-12" min="193e-12" in_port="mlab_cell_comb.portbaddr" out_port="mlab_cell_comb.portbdataout"/>
            </pb_type>
            <interconnect>
              <complete input="mlab_cell.ena0" name="ena0" output="mlab_cell_comb.ena0"/>
              <complete input="mlab_cell.portaaddr" name="portaaddr" output="mlab_cell_comb.portaaddr"/>
              <complete input="mlab_cell.portabyteenamasks" name="portabytenamasks" output="mlab_cell_comb.portabyteenamasks"/>
              <complete input="mlab_cell.portadatain" name="portadatain" output="mlab_cell_comb.portadatain"/>
              <complete input="mlab_cell.portbaddr" name="portabddr" output="mlab_cell_comb.portbaddr"/>
              <complete input="mlab_cell_comb.portbdataout" name="portbdataout" output="mlab_cell.portbdataout"/>
              <complete input="mlab_cell.clk0" name="clk0" output="mlab_cell_comb.clk0"/>
            </interconnect>
          </mode>
        </pb_type>
        <interconnect>
          <complete input="LAB.clk" name="mlab_clk" output="mlab_cell.clk0"/>
          <complete input="LAB.data_in" name="mlab_in1" output="mlab_cell.ena0"/>
          <complete input="LAB.data_in" name="mlab_in2" output="mlab_cell.portaaddr"/>
          <complete input="LAB.data_in" name="mlab_in3" output="mlab_cell.portabyteenamasks"/>
          <complete input="LAB.data_in" name="mlab_in4" output="mlab_cell.portadatain"/>
          <complete input="LAB.data_in" name="mlab_in5" output="mlab_cell.portbaddr"/>
          <complete input="mlab_cell.portbdataout" name="mlab_out" output="LAB.data_out"/>
        </interconnect>
      </mode>
    </pb_type>
    <pb_type name="DSP">
      <input name="data_in" num_pins="288"/>
      <input name="chain_in" num_pins="44"/>
      <input name="control_in" num_pins="21"/>
      <input name="scan_a_in" num_pins="18"/>
      <clock name="clk" num_pins="4"/>
      <output name="data_out_top" num_pins="72"/>
      <output name="data_out_bot" num_pins="72"/>
      <output name="chain_out" num_pins="44"/>
      <output name="scan_a_out" num_pins="18"/>
      <output name="signal_out" num_pins="6"/>
      <mode name="full_DSP">
        <pb_type name="half_DSP" num_pb="2">
          <input name="data_in" num_pins="144"/>
          <input name="chain_in" num_pins="44"/>
          <input name="scan_a_in" num_pins="18"/>
          <input name="control_in" num_pins="21"/>
          <clock name="clk" num_pins="4"/>
          <output name="data_out" num_pins="72"/>
          <output name="chain_out" num_pins="44"/>
          <output name="scan_a_out" num_pins="18"/>
          <output name="signal_out" num_pins="3"/>
          <mode name="half_DSP_normal">
            <pb_type name="mac_mult" num_pb="4">
              <input name="dataa" num_pins="18"/>
              <input name="datab" num_pins="18"/>
              <input name="signa" num_pins="1"/>
              <input name="signb" num_pins="1"/>
              <input name="ena" num_pins="4"/>
              <input name="aclr" num_pins="4"/>
              <input name="devclrn" num_pins="1"/>
              <input name="devpor" num_pins="1"/>
              <clock name="clk" num_pins="4"/>
              <output name="scanouta" num_pins="18"/>
              <output name="dataout" num_pins="36"/>
              <!--
                   For the mac_mult, we model it with to operation modes:
                        .input_type{comb}: All inputs to the multiplier are combinational (not registered)
                        .input_type{reg} : All inputs to the multiplier are registered
                   In both modes it is assumed that all outputs are combinational only.

                   This captures the key timing characteristics, although it does make some approximations.

                   Specifically, the signa, signb, dataa and datab inputs, and also the scanouta output may be used in
                   registered or combinational mode independently. While it would be unusuall to have these in different
                   modes, it is permitted in the Startix IV architecture.  
                   
                   To fully model this behaviour would require choosing (# inputs + # outputs) each having two modes (registered,
                   and combinational). Then we have a set of 10 (5 ports * 2 modes [reg, comb]) and we must choose 5. 
                   This yeilds: 10!/(5!(10!-5!)) = 252 modes, far too many to model here. This is why we make the
                   above approximation.

                   Also note that the mac_mult supports up to 4 clocks, but VPR does not support more than one, which
                   is why we have only one clock port on the stratixiv_mac_mult primitive.
                   -->
              <mode name="mac_mult_comb">
                <pb_type name="mac_mult_comb" blif_model=".subckt stratixiv_mac_mult.input_type{comb}" num_pb="1">
                  <input name="dataa" num_pins="18"/>
                  <input name="datab" num_pins="18"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="ena" num_pins="4"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <output name="scanouta" num_pins="18"/>
                  <output name="dataout" num_pins="36"/>
                  <!-- 
                       For the combinational multiplier mode, we primarily model the delay from
                       the data* and sign* inputs to the primary dataout output.  All other delays
                       are modeled with a delay of zero, since they should not fall upon the critical path.

                       From Quartus II the measured maximum delay is 1496 ps and the minimum delay is 640 ps from data inputs to data output.

                       The only other timing paths are from the dataa input to the scanouta input, which we model with zero delay.

                       Also, it should be noted that this block, being combinational can not have a clock port
                       -->
                  <delay_constant max="1496e-12" min="640e-12" in_port="mac_mult_comb.dataa" out_port="mac_mult_comb.dataout"/>
                  <delay_constant max="1496e-12" min="640e-12" in_port="mac_mult_comb.datab" out_port="mac_mult_comb.dataout"/>
                  <delay_constant max="1496e-12" min="640e-12" in_port="mac_mult_comb.signa" out_port="mac_mult_comb.dataout"/>
                  <delay_constant max="1496e-12" min="640e-12" in_port="mac_mult_comb.signb" out_port="mac_mult_comb.dataout"/>
                  <!-- Un-modeled paths -->
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_mult_comb.dataa" out_port="mac_mult_comb.scanouta"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_mult_comb.ena" out_port="mac_mult_comb.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_mult_comb.aclr" out_port="mac_mult_comb.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_mult_comb.devclrn" out_port="mac_mult_comb.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_mult_comb.devpor" out_port="mac_mult_comb.dataout"/>
                </pb_type>
                <!-- mac_mult -->
                <interconnect>
                  <!-- Directly connect inputs -->
                  <direct name="dataa_in" input="mac_mult.dataa" output="mac_mult_comb.dataa"/>
                  <direct name="datab_in" input="mac_mult.datab" output="mac_mult_comb.datab"/>
                  <direct name="signa_in" input="mac_mult.signa" output="mac_mult_comb.signa"/>
                  <direct name="signb_in" input="mac_mult.signb" output="mac_mult_comb.signb"/>
                  <direct name="ena_in" input="mac_mult.ena" output="mac_mult_comb.ena"/>
                  <direct name="aclr_in" input="mac_mult.aclr" output="mac_mult_comb.aclr"/>
                  <direct name="devclrn_in" input="mac_mult.devclrn" output="mac_mult_comb.devclrn"/>
                  <direct name="devpor_in" input="mac_mult.devpor" output="mac_mult_comb.devpor"/>
                  <!-- Directly connect outputs -->
                  <direct name="scanouta_out" input="mac_mult_comb.scanouta" output="mac_mult.scanouta"/>
                  <direct name="dataout_out" input="mac_mult_comb.dataout" output="mac_mult.dataout">
                    <!-- Output only patterns -->
                    <pack_pattern name="mac_mult_comb_to_mac_out_output_only_comb_comb" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_output_only_reg_comb" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_output_only_comb_reg" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_output_only_reg_reg" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <!-- 36-bit multiply patterns -->
                    <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_comb_comb" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_reg_comb" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_comb_reg" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_reg_reg" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <!-- One Level Adder patterns -->
                    <pack_pattern name="mac_mult_comb_to_mac_out_one_level_adder_comb_comb" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_one_level_adder_reg_comb" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_one_level_adder_comb_reg" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_one_level_adder_reg_reg" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <!-- Double patterns -->
                    <pack_pattern name="mac_mult_comb_to_mac_out_double_comb_comb" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_double_reg_comb" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_double_comb_reg" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_double_reg_reg" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <!-- Two Level Adder patterns -->
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_comb_comb" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_reg_comb" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_comb_reg" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_reg_reg" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <!-- Two-Level Adder Chain Out multiply patterns -->
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_comb_comb" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_reg_comb" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_comb_reg" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_reg_reg" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <!-- Accmulator patterns -->
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_comb_comb" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_reg_comb" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_comb_reg" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_reg_reg" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <!-- Accmulator chain out patterns -->
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_comb_comb" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_reg_comb" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_comb_reg" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_reg_reg" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <!-- Shift patterns -->
                    <pack_pattern name="mac_mult_comb_to_mac_out_shift_comb_comb" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_shift_reg_comb" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_shift_comb_reg" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_shift_reg_reg" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <!-- Loopback patterns -->
                    <pack_pattern name="mac_mult_comb_to_mac_out_loopback_comb_comb" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_loopback_reg_comb" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_loopback_comb_reg" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_loopback_reg_reg" in_port="mac_mult_comb.dataout[0]" out_port="mac_mult.dataout[0]"/>
                  </direct>
                </interconnect>
              </mode>
              <mode name="mac_mult_reg">
                <pb_type name="mac_mult_reg" blif_model=".subckt stratixiv_mac_mult.input_type{reg}" num_pb="1">
                  <input name="dataa" num_pins="18"/>
                  <input name="datab" num_pins="18"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="ena" num_pins="4"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="scanouta" num_pins="18"/>
                  <output name="dataout" num_pins="36"/>
                  <!-- 
                       For the registered multiplier mode we assume all inputs are registered, while all outputs are
                       combinational.
                       
                       From Quartus II the delay from the mac_mult input registers is:   max: 428ps |  min: 205ps
                       From Quartus II the input register setup time is: 					  99ps
                       From Quartus II the output register hold time is: 					  48ps

                       Therefore, for the input paths we model the setup time as:
                            Input to register delay:    428ps
                         +  Register setup time:         99ps
                            _________________________________
                            Total Tsu:                  527ps
                       
                       Correspondingly, we model the input path hold time as:
                            Register hold time:          48ps
                         -  Input to register delay:    205ps
                            _________________________________
                            Total Hold Value            -157ps

                       Note that the total hold is a negative value. This ensures that a hold time violation on this mac_mult is very unlikely.
                       This might be due to an error in calculation or an incorrectly recorded value since it is negative.

                       From Quartus II the input register clock to output time is:       max:   97ps |  min:  37ps
                       From Quartus II the dataout combinational multiplier delay is:    max: 1185ps |  min: 487ps
                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_mult_reg.dataa" value="527e-12"/>
                  <T_setup clock="clk" port="mac_mult_reg.datab" value="527e-12"/>
                  <T_setup clock="clk" port="mac_mult_reg.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_mult_reg.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_mult_reg.ena" value="99e-12"/>
                  <T_setup clock="clk" port="mac_mult_reg.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async -->
                  <T_setup clock="clk" port="mac_mult_reg.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_mult_reg.devpor" value="99e-12"/>
                  <T_hold clock="clk" port="mac_mult_reg.dataa" value="-157e-12"/>
                  <T_hold clock="clk" port="mac_mult_reg.datab" value="-157e-12"/>
                  <T_hold clock="clk" port="mac_mult_reg.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_mult_reg.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_mult_reg.ena" value="48e-12"/>
                  <T_hold clock="clk" port="mac_mult_reg.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async -->
                  <T_hold clock="clk" port="mac_mult_reg.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_mult_reg.devpor" value="48e-12"/>
                  <!-- Internal input timing -->
                  <T_clock_to_Q clock="clk" port="mac_mult_reg.dataa" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_mult_reg.datab" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_mult_reg.signa" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_mult_reg.signb" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_mult_reg.ena" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_mult_reg.devclrn" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_mult_reg.devpor" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_mult_reg.aclr" max="97e-12" min="97e-12"/>
                  <!-- Internal combinational delay -->
                  <delay_constant in_port="mac_mult_reg.dataa" out_port="mac_mult_reg.dataout" max="1185e-12" min="487e-12"/>
                  <delay_constant in_port="mac_mult_reg.datab" out_port="mac_mult_reg.dataout" max="1185e-12" min="487e-12"/>
                  <delay_constant in_port="mac_mult_reg.signa" out_port="mac_mult_reg.dataout" max="1185e-12" min="487e-12"/>
                  <delay_constant in_port="mac_mult_reg.signb" out_port="mac_mult_reg.dataout" max="1185e-12" min="487e-12"/>
                  <delay_constant in_port="mac_mult_reg.ena" out_port="mac_mult_reg.dataout" max="1185e-12" min="487e-12"/>
                  <delay_constant in_port="mac_mult_reg.devclrn" out_port="mac_mult_reg.dataout" max="1185e-12" min="487e-12"/>
                  <delay_constant in_port="mac_mult_reg.devpor" out_port="mac_mult_reg.dataout" max="1185e-12" min="487e-12"/>
                  <delay_constant in_port="mac_mult_reg.aclr" out_port="mac_mult_reg.dataout" max="1185e-12" min="487e-12"/>
                  <!-- External output Timing -->
                  <T_clock_to_Q clock="clk" port="mac_mult_reg.scanouta" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_mult -->
                <interconnect>
                  <!-- Directly connect inputs -->
                  <direct name="dataa_in" input="mac_mult.dataa" output="mac_mult_reg.dataa"/>
                  <direct name="datab_in" input="mac_mult.datab" output="mac_mult_reg.datab"/>
                  <direct name="signa_in" input="mac_mult.signa" output="mac_mult_reg.signa"/>
                  <direct name="signb_in" input="mac_mult.signb" output="mac_mult_reg.signb"/>
                  <direct name="ena_in" input="mac_mult.ena" output="mac_mult_reg.ena"/>
                  <direct name="aclr_in" input="mac_mult.aclr" output="mac_mult_reg.aclr"/>
                  <direct name="devclrn_in" input="mac_mult.devclrn" output="mac_mult_reg.devclrn"/>
                  <direct name="devpor_in" input="mac_mult.devpor" output="mac_mult_reg.devpor"/>
                  <!-- Directly connect outputs -->
                  <direct name="scanouta_out" input="mac_mult_reg.scanouta" output="mac_mult.scanouta"/>
                  <direct name="dataout_out" input="mac_mult_reg.dataout" output="mac_mult.dataout">
                    <!-- Output only patterns -->
                    <pack_pattern name="mac_mult_reg_to_mac_out_output_only_comb_comb" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_output_only_reg_comb" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_output_only_comb_reg" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_output_only_reg_reg" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <!-- 36-bit multiply patterns -->
                    <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_comb_comb" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_reg_comb" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_comb_reg" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_reg_reg" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <!-- One Level Adder patterns -->
                    <pack_pattern name="mac_mult_reg_to_mac_out_one_level_adder_comb_comb" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_one_level_adder_reg_comb" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_one_level_adder_comb_reg" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_one_level_adder_reg_reg" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <!-- Double patterns -->
                    <pack_pattern name="mac_mult_reg_to_mac_out_double_comb_comb" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_double_reg_comb" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_double_comb_reg" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_double_reg_reg" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <!-- Two Level Adder patterns -->
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_comb_comb" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_reg_comb" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_comb_reg" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_reg_reg" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <!-- Two-Level Adder Chain Out multiply patterns -->
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_comb_comb" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_reg_comb" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_comb_reg" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_reg_reg" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <!-- Accmulator patterns -->
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_comb_comb" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_reg_comb" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_comb_reg" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_reg_reg" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <!-- Accmulator chain out patterns -->
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_comb_comb" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_reg_comb" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_comb_reg" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_reg_reg" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <!-- Shift patterns -->
                    <pack_pattern name="mac_mult_reg_to_mac_out_shift_comb_comb" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_shift_reg_comb" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_shift_comb_reg" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_shift_reg_reg" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <!-- Loopback patterns -->
                    <pack_pattern name="mac_mult_reg_to_mac_out_loopback_comb_comb" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_loopback_reg_comb" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_loopback_comb_reg" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_loopback_reg_reg" in_port="mac_mult_reg.dataout[0]" out_port="mac_mult.dataout[0]"/>
                  </direct>
                  <!-- Drop the unsupported extra clocks -->
                  <complete name="clk_in" input="mac_mult.clk" output="mac_mult_reg.clk"/>
                </interconnect>
              </mode>
            </pb_type>
            <pb_type name="mac_out" num_pb="1">
              <input name="data_in" num_pins="144"/>
              <input name="chain_in" num_pins="44"/>
              <input name="control_in" num_pins="21"/>
              <clock name="clk" num_pins="4"/>
              <output name="data_out" num_pins="72"/>
              <output name="signal_out" num_pins="3"/>
              <output name="loopback_out" num_pins="18"/>
              <!-- 
                   We model several different operation modes of the mac_out primitive:
                        output_only
                        36_bit_multiply
                        one_level_adder
                        two_level_adder
                        two_level_chainout
                        loopback
                        accumulator
                        accumulator_chainout
                        shift
                        double

                   We also model 4 variations of each operation mode to capture timing differences based on whether the inputs and/or outputs are 
                   registered or combinational.

                   This is itself an approximation of the actual Stratix IV architecture, which can support multiple levels of internal registers
                   inside each DSP block.  To model this would be extremely verbose and time consuming. The approximation mentioned above is a 
                   reasonable compromise, since it captures the key timing characteristics of the mac_mult from an external perspective (which is
                   what most pack/place/route CAD tools would care about).  
                   
                   Since we do not model the internal paths and registers inside the mac_out, it is useful to keep in mind that in the actual Stratix
                   IV the DSP blocks are typically limited to ~700 MHz at the maximum level of internal pipelining.  However they are more typically
                   limited to 510 MHz by minimum clock pulse width violations. Hence, any circuit using this architecture that reports an operating 
                   frequency above 510 MHz but includes paths through DSP blocks may be optimistic.

                   Furthermore, since most designs use only the 36-bit multiply and output only operation modes, the timing for these modes were 
                   carefully measured in Quartus II and modeled below. All other operation modes have the same timing values, which where measured 
                   in the two-level adder mode.
                   -->
              <mode name="output_only.input_type{comb}.output_type{comb}">
                <pb_type name="mac_out_output_only" blif_model=".subckt stratixiv_mac_out.opmode{output_only}.input_type{comb}.output_type{comb}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <output name="dataout" num_pins="36"/>
                  <output name="dftout" num_pins="1"/>
                  <!-- 
                       In this mode the block is purely combinational. We model only the main data path, but add 
                       zero delay edges to other possible timing paths through the block.  It is very unlikely 
                       that the non-datapath signals would every end up on the critical path.

                       Delay through the mac_out in this mode has a maximum delay of 1105ps, and a minimum delay of 581ps, 
                       as measured using a combinational 18bit LPM_Mult in QII.
                       -->
                  <delay_constant max="1105e-12" min="581e-12" in_port="mac_out_output_only.dataa" out_port="mac_out_output_only.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_output_only.round" out_port="mac_out_output_only.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_output_only.saturate" out_port="mac_out_output_only.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_output_only.devclrn" out_port="mac_out_output_only.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_output_only.devpor" out_port="mac_out_output_only.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_output_only.ena" out_port="mac_out_output_only.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_output_only.dataa" out_port="mac_out_output_only.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_output_only.round" out_port="mac_out_output_only.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_output_only.saturate" out_port="mac_out_output_only.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_output_only.devclrn" out_port="mac_out_output_only.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_output_only.devpor" out_port="mac_out_output_only.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_output_only.aclr" out_port="mac_out_output_only.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_output_only.ena" out_port="mac_out_output_only.dftout"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_output_only.dataa">
                    <pack_pattern name="mac_mult_comb_to_mac_out_output_only_comb_comb" in_port="mac_out.data_in[0]" out_port="mac_out_output_only.dataa[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_output_only_comb_comb" in_port="mac_out.data_in[0]" out_port="mac_out_output_only.dataa[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_output_only.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_output_only.saturate"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_output_only.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_output_only.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_output_only.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_output_only.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 36 (dataa width) in this mode -->
                  <direct name="out_c2" input="mac_out_output_only.dataout" output="mac_out.data_out[35:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_3" input="mac_out_output_only.dftout" output="mac_out.signal_out[2]"/>
                </interconnect>
              </mode>
              <!-- output_only-->
              <mode name="output_only.input_type{reg}.output_type{comb}">
                <pb_type name="mac_out_output_only" blif_model=".subckt stratixiv_mac_out.opmode{output_only}.input_type{reg}.output_type{comb}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="36"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has input registers with a combinational output.  

                       Measuring with QII we arrived at the following maximum values:
                          Input Register Setup Time (iTsu):              99ps
                          Input Register Clock-to-Q Time (iTcq):         97ps
                          Input delay to the input registers (iTd):       0ps
                          Combinational Output delay to dataout (oTd): 1041ps
                          
                       QII also output the following minimum values:
                          Input Register Setup Time (iTsu):              48ps
                          Input Register Clock-to-Q Time (iTcq):         97ps
                          Input delay to the input registers (iTd):       0ps
                          Combinational Output delay to dataout (oTd):  663ps

                       Note that iTd is zero in this mode, but not in others.  This mode seems to have
                       a special bypass path that skips the first level adders in the mac_out (see
                       QUIP documentation)

                       This results in the following Tsu and Tcq times:
                          All inputs Tsu   : iTsu         =       99ps
                          Hold time uTh    : uTh          =       48ps
                          dataa Tcq        : iTcq         = max:   97ps 	| min:  97ps
                          output comb delay: oTd          = max: 1041ps 	| min: 663ps
                          All other Tcq    : iTcq         = max:   97ps 	| min:  97ps
                       -->
                  <!-- Input external timing -->
                  <T_setup clock="clk" port="mac_out_output_only.dataa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_output_only.round" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_output_only.saturate" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_output_only.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_output_only.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_output_only.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_output_only.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_output_only.dataa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_output_only.round" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_output_only.saturate" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_output_only.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_output_only.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_output_only.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_output_only.ena" value="48e-12"/>
                  <!-- Input internal timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_output_only.dataa" max="97e-12" min="97e-12"/>
                  <!-- Output combinational delay -->
                  <delay_constant in_port="mac_out_output_only.dataa" out_port="mac_out_output_only.dataout" max="1041e-12" min="663e-12"/>
                  <!-- Output external timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_output_only.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_output_only.dataa">
                    <pack_pattern name="mac_mult_comb_to_mac_out_output_only_reg_comb" in_port="mac_out.data_in[0]" out_port="mac_out_output_only.dataa[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_output_only_reg_comb" in_port="mac_out.data_in[0]" out_port="mac_out_output_only.dataa[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_output_only.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_output_only.saturate"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_output_only.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_output_only.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_output_only.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_output_only.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 36 (dataa width) in this mode -->
                  <direct name="out_c2" input="mac_out_output_only.dataout" output="mac_out.data_out[35:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_3" input="mac_out_output_only.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock inputs -->
                  <complete name="clk_in" input="mac_out.clk" output="mac_out_output_only.clk"/>
                </interconnect>
              </mode>
              <!-- output_only-->
              <mode name="output_only.input_type{comb}.output_type{reg}">
                <pb_type name="mac_out_output_only" blif_model=".subckt stratixiv_mac_out.opmode{output_only}.input_type{comb}.output_type{reg}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="36"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has a combinational input with a registered output.  

                       We estimate the following based on other modes:
                          Input delay to the output registers (iTd):      max: 	708ps 	|  min:  456ps

                       Measuring with QII we arrived at the following values:
                          Output Register Setup Time (oTsu):              	     99ps
                          Output Register Hold Time (uTh):		  	             48ps
					  With setup analysis in QII, we arrived at the following maximum values:
                          Output Register Clock-to-Q Time (oTcq):           	 97ps
                          Combinational Output delay to dataout (oTd):      	333ps
					  With hold analysis in QII, we arrived at the following minimum values:
                          Output Register Clock-to-Q Time (oTcq):           	 97ps
                          Combinational Output delay to dataout (oTd):      	158ps


                       This results in the following Tsu and Tcq times:
                          'dataa' combinational input delay: iTd         = max:  708ps	|  min:  456ps
                           All Tsu                         : oTsu        =        99ps
                           All uTh                         : uTh	     =        48ps
                          'dataout' Tcq                    : oTcq + oTd  = max:  430ps	|  min:  255ps   
                          All other Tcq                    : oTcq        = max:   97ps	|  min:   97ps   
                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_output_only.round" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_output_only.saturate" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_output_only.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_output_only.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_output_only.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_output_only.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_output_only.round" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_output_only.saturate" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_output_only.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_output_only.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_output_only.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_output_only.ena" value="48e-12"/>
                  <!-- Input combinational delay -->
                  <delay_constant in_port="mac_out_output_only.dataa" out_port="mac_out_output_only.dataout" max="708e-12" min="456e-12"/>
                  <!-- Internal output timing -->
                  <T_setup clock="clk" port="mac_out_output_only.dataout" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_output_only.dataout" value="48e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_output_only.dataout" max="430e-12" min="255e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_output_only.dftout" max="99e-12" min="99e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_output_only.dataa">
                    <pack_pattern name="mac_mult_comb_to_mac_out_output_only_comb_reg" in_port="mac_out.data_in[0]" out_port="mac_out_output_only.dataa[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_output_only_comb_reg" in_port="mac_out.data_in[0]" out_port="mac_out_output_only.dataa[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_output_only.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_output_only.saturate"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_output_only.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_output_only.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_output_only.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_output_only.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 36 (dataa width) in this mode -->
                  <direct name="out_c2" input="mac_out_output_only.dataout" output="mac_out.data_out[35:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_3" input="mac_out_output_only.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock inputs -->
                  <complete name="clk_in" input="mac_out.clk" output="mac_out_output_only.clk"/>
                </interconnect>
              </mode>
              <!-- output_only-->
              <mode name="output_only.input_type{reg}.output_type{reg}">
                <pb_type name="mac_out_output_only" blif_model=".subckt stratixiv_mac_out.opmode{output_only}.input_type{reg}.output_type{reg}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="36"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has a registered input and a registered output.  
                       We model the combinational input delay as part of the setup time, and
                       the combinational output delay as part of the clock to q time.

                       Note that there may or may not actually have been additional pipelining
                       inside the DSP block, so in this case we are not cycle accurate to Stratix IV.
                       Since Stratix IV DSP blocks are practically limited to an speed of 510MHz,
                       we create an internal combinational path which models ths limit.

                       Measuring with QII we arrived at the following values:
                          Input/Output Register Setup Time (iTsu/oTsu):       99ps
                          Input/Output Register Hold Time (uTh):      	      48ps
					            Setup timing analysis with QII arrived at the following maximum values:
                          Input/Output Register Clock-to-Q Time (iTcq/oTcq):  97ps 
                          Combinational Output delay to dataout (oTd):       367ps 
                          Input delay to the input registers (iTd):            0ps
					            Hold timing analysis with QII arrived at the following minimum values:
                          Input/Output Register Clock-to-Q Time (iTcq/oTcq):  97ps
                          Combinational Output delay to dataout (oTd):       183ps
                          Input delay to the input registers (iTd):            0ps


                       This results in the following Tsu and Tcq times:
                          'dataa' Tsu:     iTsu + iTd  =  	        99ps   
                          'dataa' uTh:     uTh  - iTd  =  	        48ps
                          'dataout' Tcq:   oTcq + iTd  =    max:   464ps   |   min: 280ps
                          All others Tcq:  oTcq        =    max:    97ps   |   min: 97ps
                          All others Tsu:  iTsu        = 	        99ps

                          Internal Tsu: iTsu           = 		    99ps
                          Internal uTh: uTh            = 		    48ps
                          Internal Tcq: iTcq           =    max:    97ps   |   min: 97ps
                          
                          Maximum combinational delay  : (1 / 510MHz) - iTsu - iTcq = 		1765ps
                          Minimum combinational delay  :  441 ps
                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_output_only.dataa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_output_only.round" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_output_only.saturate" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_output_only.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_output_only.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_output_only.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_output_only.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_output_only.dataa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_output_only.round" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_output_only.saturate" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_output_only.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_output_only.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_output_only.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_output_only.ena" value="48e-12"/>
                  <!-- Internal input timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_output_only.dataa" max="97e-12" min="97e-12"/>
                  <!-- Internal combinational delay -->
                  <delay_constant in_port="mac_out_output_only.dataa" out_port="mac_out_output_only.dataout" max="1765e-12" min="441e-12"/>
                  <!-- Internal output timing -->
                  <T_setup clock="clk" port="mac_out_output_only.dataout" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_output_only.dataout" value="48e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_output_only.dataout" max="464e-12" min="280e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_output_only.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_output_only.dataa">
                    <pack_pattern name="mac_mult_comb_to_mac_out_output_only_reg_reg" in_port="mac_out.data_in[0]" out_port="mac_out_output_only.dataa[0]"/>
                    <pack_pattern name="mac_mult_reg_to_mac_out_output_only_reg_reg" in_port="mac_out.data_in[0]" out_port="mac_out_output_only.dataa[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_output_only.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_output_only.saturate"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_output_only.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_output_only.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_output_only.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_output_only.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 36 (dataa width) in this mode -->
                  <direct name="out_c2" input="mac_out_output_only.dataout" output="mac_out.data_out[35:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_3" input="mac_out_output_only.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock inputs -->
                  <complete name="clk_in" input="mac_out.clk" output="mac_out_output_only.clk"/>
                </interconnect>
              </mode>
              <!-- output_only-->
              <mode name="36_bit_multiply.input_type{comb}.output_type{comb}">
                <pb_type name="mac_out_36_bit_multiply" blif_model=".subckt stratixiv_mac_out.opmode{36_bit_multiply}.input_type{comb}.output_type{comb}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <output name="dataout" num_pins="72"/>
                  <output name="dftout" num_pins="1"/>
                  <!-- 
                       In this mode the block is purely combinational. We model only the main data path, but add 
                       zero delay edges to other possible timing paths through the block.  It is very unlikely 
                       that the non-datapath signals would every end up on the critical path.

                       The delay through the mac_out in this mode has a maximum value of 1947ps, and a minimum 
                       delay of 750ps, as measured using a combinational 36 bit LPM_Mult in QII.
                       -->
                  <delay_constant max="1947e-12" min="750e-12" in_port="mac_out_36_bit_multiply.dataa" out_port="mac_out_36_bit_multiply.dataout"/>
                  <delay_constant max="1947e-12" min="750e-12" in_port="mac_out_36_bit_multiply.datab" out_port="mac_out_36_bit_multiply.dataout"/>
                  <delay_constant max="1947e-12" min="750e-12" in_port="mac_out_36_bit_multiply.datac" out_port="mac_out_36_bit_multiply.dataout"/>
                  <delay_constant max="1947e-12" min="750e-12" in_port="mac_out_36_bit_multiply.datad" out_port="mac_out_36_bit_multiply.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_36_bit_multiply.signa" out_port="mac_out_36_bit_multiply.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_36_bit_multiply.signb" out_port="mac_out_36_bit_multiply.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_36_bit_multiply.devclrn" out_port="mac_out_36_bit_multiply.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_36_bit_multiply.devpor" out_port="mac_out_36_bit_multiply.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_36_bit_multiply.aclr" out_port="mac_out_36_bit_multiply.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_36_bit_multiply.ena" out_port="mac_out_36_bit_multiply.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_36_bit_multiply.dataa" out_port="mac_out_36_bit_multiply.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_36_bit_multiply.datab" out_port="mac_out_36_bit_multiply.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_36_bit_multiply.datac" out_port="mac_out_36_bit_multiply.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_36_bit_multiply.datad" out_port="mac_out_36_bit_multiply.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_36_bit_multiply.signa" out_port="mac_out_36_bit_multiply.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_36_bit_multiply.signb" out_port="mac_out_36_bit_multiply.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_36_bit_multiply.devclrn" out_port="mac_out_36_bit_multiply.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_36_bit_multiply.devpor" out_port="mac_out_36_bit_multiply.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_36_bit_multiply.ena" out_port="mac_out_36_bit_multiply.dftout"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_36_bit_multiply.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_comb_comb" in_port="mac_out.data_in[0]" out_port="mac_out_36_bit_multiply.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_comb_comb" in_port="mac_out.data_in[0]" out_port="mac_out_36_bit_multiply.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_36_bit_multiply.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_comb_comb" in_port="mac_out.data_in[36]" out_port="mac_out_36_bit_multiply.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_comb_comb" in_port="mac_out.data_in[36]" out_port="mac_out_36_bit_multiply.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_36_bit_multiply.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_comb_comb" in_port="mac_out.data_in[72]" out_port="mac_out_36_bit_multiply.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_comb_comb" in_port="mac_out.data_in[72]" out_port="mac_out_36_bit_multiply.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_36_bit_multiply.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_comb_comb" in_port="mac_out.data_in[108]" out_port="mac_out_36_bit_multiply.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_comb_comb" in_port="mac_out.data_in[108]" out_port="mac_out_36_bit_multiply.datad[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_36_bit_multiply.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_36_bit_multiply.signb"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_36_bit_multiply.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_36_bit_multiply.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_36_bit_multiply.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_36_bit_multiply.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 72 (dataa width + datab width) in this mode -->
                  <direct name="out_c2" input="mac_out_36_bit_multiply.dataout[71:0]" output="mac_out.data_out"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_3" input="mac_out_36_bit_multiply.dftout" output="mac_out.signal_out[2]"/>
                </interconnect>
              </mode>
              <!-- 36_bit_multiply-->
              <mode name="36_bit_multiply.input_type{reg}.output_type{comb}">
                <pb_type name="mac_out_36_bit_multiply" blif_model=".subckt stratixiv_mac_out.opmode{36_bit_multiply}.input_type{reg}.output_type{comb}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="72"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has input registers with a combinational out.  

                       Measuring with QII we arrived at the following values:

                          Input Register Setup Time (iTsu):              99ps
                          Input Register Hold Time (uTh):                48ps
					  Setup analysis using QII arrived at the following maximum values:
                          Input delay to the input registers (iTd):     432ps
                          Input Register Clock-to-Q Time (iTcq):         97ps
                          Combinational Output delay to dataout (oTd): 1922ps
					  Hold analysis in QII arrived at the following minimum values:					   
                          Input delay to the input registers (iTd):       4ps
                          Input Register Clock-to-Q Time (iTcq):         97ps
                          Combinational Output delay to dataout (oTd):  755ps

                       This results in the following Tsu and Tcq times:
                          'data*' Tsu         : iTd + iTsu  =       531ps
                          'data*' uTh	      : uTh - iTd   =        44ps 
                          Other inputs Tsu    : iTsu        =        99ps		
                          Other inputs uTh	  : uTh         =        48ps
                          All inputs Tcq      : iTcq        = max:   97ps   |  	min:  97ps
                          'dataout' comb delay: oTd         = max: 1922ps	|  	min: 755ps
                          other outputs Tcq   : iTcq        = max:   97ps	|	min:  97ps
                       -->
                  <!-- Input external timing -->
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.dataa" value="531e-12"/>
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.datab" value="531e-12"/>
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.datac" value="531e-12"/>
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.datad" value="531e-12"/>
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.dataa" value="44e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.datab" value="44e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.datac" value="44e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.datad" value="44e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.ena" value="48e-12"/>
                  <!-- Input internal timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_36_bit_multiply.dataa" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_36_bit_multiply.datab" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_36_bit_multiply.datac" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_36_bit_multiply.datad" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_36_bit_multiply.signa" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_36_bit_multiply.signb" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_36_bit_multiply.devclrn" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_36_bit_multiply.devpor" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_36_bit_multiply.ena" max="97e-12" min="97e-12"/>
                  <!-- Output combinational delay -->
                  <delay_constant in_port="mac_out_36_bit_multiply.dataa" out_port="mac_out_36_bit_multiply.dataout" max="1922e-12" min="755e-12"/>
                  <delay_constant in_port="mac_out_36_bit_multiply.datab" out_port="mac_out_36_bit_multiply.dataout" max="1922e-12" min="755e-12"/>
                  <delay_constant in_port="mac_out_36_bit_multiply.datac" out_port="mac_out_36_bit_multiply.dataout" max="1922e-12" min="755e-12"/>
                  <delay_constant in_port="mac_out_36_bit_multiply.datad" out_port="mac_out_36_bit_multiply.dataout" max="1922e-12" min="755e-12"/>
                  <delay_constant in_port="mac_out_36_bit_multiply.signa" out_port="mac_out_36_bit_multiply.dataout" max="1922e-12" min="755e-12"/>
                  <delay_constant in_port="mac_out_36_bit_multiply.signb" out_port="mac_out_36_bit_multiply.dataout" max="1922e-12" min="755e-12"/>
                  <delay_constant in_port="mac_out_36_bit_multiply.devclrn" out_port="mac_out_36_bit_multiply.dataout" max="1922e-12" min="755e-12"/>
                  <delay_constant in_port="mac_out_36_bit_multiply.devpor" out_port="mac_out_36_bit_multiply.dataout" max="1922e-12" min="755e-12"/>
                  <delay_constant in_port="mac_out_36_bit_multiply.ena" out_port="mac_out_36_bit_multiply.dataout" max="1922e-12" min="755e-12"/>
                  <!-- Output external timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_36_bit_multiply.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_36_bit_multiply.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_reg_comb" in_port="mac_out.data_in[0]" out_port="mac_out_36_bit_multiply.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_reg_comb" in_port="mac_out.data_in[0]" out_port="mac_out_36_bit_multiply.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_36_bit_multiply.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_reg_comb" in_port="mac_out.data_in[36]" out_port="mac_out_36_bit_multiply.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_reg_comb" in_port="mac_out.data_in[36]" out_port="mac_out_36_bit_multiply.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_36_bit_multiply.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_reg_comb" in_port="mac_out.data_in[72]" out_port="mac_out_36_bit_multiply.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_reg_comb" in_port="mac_out.data_in[72]" out_port="mac_out_36_bit_multiply.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_36_bit_multiply.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_reg_comb" in_port="mac_out.data_in[108]" out_port="mac_out_36_bit_multiply.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_reg_comb" in_port="mac_out.data_in[108]" out_port="mac_out_36_bit_multiply.datad[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_36_bit_multiply.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_36_bit_multiply.signb"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_36_bit_multiply.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_36_bit_multiply.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_36_bit_multiply.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_36_bit_multiply.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 72 (dataa width + datab width) in this mode -->
                  <direct name="out_c2" input="mac_out_36_bit_multiply.dataout[71:0]" output="mac_out.data_out"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_3" input="mac_out_36_bit_multiply.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_36_bit_multiply.clk"/>
                </interconnect>
              </mode>
              <!-- 36_bit_multiply-->
              <mode name="36_bit_multiply.input_type{comb}.output_type{reg}">
                <pb_type name="mac_out_36_bit_multiply" blif_model=".subckt stratixiv_mac_out.opmode{36_bit_multiply}.input_type{comb}.output_type{reg}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="72"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has a combinational input with a registered out.  

                       We estimate the following maximum delays based on other modes:
                          Combinational Output delay to dataout (oTd):  max:  333ps  |  min: 183ps

                       Measuring setup analysis with QII we arrived at the following maximum delay values:
                          Output Register Setup Time (oTsu):              99ps
                          Output Register Clock-to-Q Time (oTcq):         97ps
                          Input delay to the output registers (iTd):    1361ps
						  
					   Measuring hold analysis with QII, we arrived at the following minimum delay values:
                          Output Register Hold Time (uTh):                48ps
                          Output Register Clock-to-Q Time (oTcq):         97ps
                          Input delay to the output registers (iTd):     393ps
					   

                       This results in the following times:
                          'data*' input comb delay: iTd    =   max: 1361ps	|  min: 183ps
                          'data*' Tsu             : oTsu   = 		  99ps 
                          'data*' uTh             : uTh    = 		  48ps
                          'dataout' Tcq      : oTcq + oTd  =   max:  430ps  |  min: 180ps
                          All others Tcq     : oTcq        =   max:   97ps	|  min:  97ps
                          All others Tsu     : oTsu        = 		  99ps
                          All others uTh     : uTh         = 		  48ps
                       -->
                  <!-- Input combinational delay -->
                  <delay_constant in_port="mac_out_36_bit_multiply.dataa" out_port="mac_out_36_bit_multiply.dataout" max="1361e-12" min="183e-12"/>
                  <delay_constant in_port="mac_out_36_bit_multiply.datab" out_port="mac_out_36_bit_multiply.dataout" max="1361e-12" min="183e-12"/>
                  <delay_constant in_port="mac_out_36_bit_multiply.datac" out_port="mac_out_36_bit_multiply.dataout" max="1361e-12" min="183e-12"/>
                  <delay_constant in_port="mac_out_36_bit_multiply.datad" out_port="mac_out_36_bit_multiply.dataout" max="1361e-12" min="183e-12"/>
                  <!-- Input external timing -->
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.ena" value="48e-12"/>
                  <!-- Output internal timing -->
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.dataout" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.dataout" value="48e-12"/>
                  <!-- Output external timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_36_bit_multiply.dataout" max="430e-12" min="180e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_36_bit_multiply.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_36_bit_multiply.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_comb_reg" in_port="mac_out.data_in[0]" out_port="mac_out_36_bit_multiply.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_comb_reg" in_port="mac_out.data_in[0]" out_port="mac_out_36_bit_multiply.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_36_bit_multiply.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_comb_reg" in_port="mac_out.data_in[36]" out_port="mac_out_36_bit_multiply.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_comb_reg" in_port="mac_out.data_in[36]" out_port="mac_out_36_bit_multiply.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_36_bit_multiply.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_comb_reg" in_port="mac_out.data_in[72]" out_port="mac_out_36_bit_multiply.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_comb_reg" in_port="mac_out.data_in[72]" out_port="mac_out_36_bit_multiply.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_36_bit_multiply.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_comb_reg" in_port="mac_out.data_in[108]" out_port="mac_out_36_bit_multiply.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_comb_reg" in_port="mac_out.data_in[108]" out_port="mac_out_36_bit_multiply.datad[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_36_bit_multiply.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_36_bit_multiply.signb"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_36_bit_multiply.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_36_bit_multiply.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_36_bit_multiply.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_36_bit_multiply.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 72 (dataa width + datab width) in this mode -->
                  <direct name="out_c2" input="mac_out_36_bit_multiply.dataout[71:0]" output="mac_out.data_out"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_3" input="mac_out_36_bit_multiply.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_36_bit_multiply.clk"/>
                </interconnect>
              </mode>
              <!-- 36_bit_multiply-->
              <mode name="36_bit_multiply.input_type{reg}.output_type{reg}">
                <pb_type name="mac_out_36_bit_multiply" blif_model=".subckt stratixiv_mac_out.opmode{36_bit_multiply}.input_type{reg}.output_type{reg}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="72"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has a registered input and a registered out.  
                       We model the combinational input delay as part of the setup time, and
                       the combinational output delay as part of the clock to q time.

                       Note that there may or may not actually have been additional pipelining
                       inside the DSP block, so in this case we are not cycle accurate to Stratix IV.
                       Since Stratix IV DSP blocks are practically limited to an speed of 510MHz,
                       we create an internal combinational path which models ths limit.

                       Measuring with QII we arrived at the following maximum values:
                          Input/Output Register Setup Time (iTsu/oTsu):      99ps
                          Input/Output Register Clock-to-Q Time (iTcq/oTcq): 97ps
                          Combinational Output delay to dataout (oTd):      355ps
                          Input delay to the input registers (iTd):         432ps
						  
                       Measuring with QII we arrived at the following minimum values:
                          Input/Output Register Hold Time (uTh):      		 48ps
                          Input/Output Register Clock-to-Q Time (iTcq/oTcq): 97ps
                          Combinational Output delay to dataout (oTd):      183ps
                          Input delay to the input registers (iTd):           4ps
                          Min comb delay  :  520ps

                       This results in the following Tsu and Tcq times:
                          'dataa' Tsu:     iTsu + iTd  =      531ps   
                          'dataa' uTh:     uTh  - iTd  =       44ps
                          'dataout' Tcq:   oTcq + oTd  = max: 452ps  |	min: 280ps
                          All others Tcq:  oTcq        = max:  97ps	 |	min:  97ps
                          All others Tsu:  iTsu        =       99ps
                          All others uTh:  uTh         =       48ps

                          Internal Tsu: iTsu           =       99ps
                          Internal uTh: uTh            =       48ps
                          Internal Tcq: iTcq           = max:  97ps  |  min:  97ps

                          Max comb delay  : (1 / 510MHz) - iTsu - iTcq = 1765ps

                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.dataa" value="531e-12"/>
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.datab" value="531e-12"/>
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.datac" value="531e-12"/>
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.datad" value="531e-12"/>
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.dataa" value="44e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.datab" value="44e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.datac" value="44e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.datad" value="44e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.ena" value="48e-12"/>
                  <!-- Internal input timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_36_bit_multiply.dataa" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_36_bit_multiply.datab" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_36_bit_multiply.datac" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_36_bit_multiply.datad" max="97e-12" min="97e-12"/>
                  <!-- Internal combinational delay -->
                  <delay_constant in_port="mac_out_36_bit_multiply.dataa" out_port="mac_out_36_bit_multiply.dataout" max="1765e-12" min="520e-12"/>
                  <delay_constant in_port="mac_out_36_bit_multiply.datab" out_port="mac_out_36_bit_multiply.dataout" max="1765e-12" min="520e-12"/>
                  <delay_constant in_port="mac_out_36_bit_multiply.datac" out_port="mac_out_36_bit_multiply.dataout" max="1765e-12" min="520e-12"/>
                  <delay_constant in_port="mac_out_36_bit_multiply.datad" out_port="mac_out_36_bit_multiply.dataout" max="1765e-12" min="520e-12"/>
                  <!-- Internal output timing -->
                  <T_setup clock="clk" port="mac_out_36_bit_multiply.dataout" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_36_bit_multiply.dataout" value="48e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_36_bit_multiply.dataout" max="452e-12" min="280e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_36_bit_multiply.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_36_bit_multiply.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_reg_reg" in_port="mac_out.data_in[0]" out_port="mac_out_36_bit_multiply.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_reg_reg" in_port="mac_out.data_in[0]" out_port="mac_out_36_bit_multiply.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_36_bit_multiply.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_reg_reg" in_port="mac_out.data_in[36]" out_port="mac_out_36_bit_multiply.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_reg_reg" in_port="mac_out.data_in[36]" out_port="mac_out_36_bit_multiply.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_36_bit_multiply.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_reg_reg" in_port="mac_out.data_in[72]" out_port="mac_out_36_bit_multiply.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_reg_reg" in_port="mac_out.data_in[72]" out_port="mac_out_36_bit_multiply.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_36_bit_multiply.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_reg_reg" in_port="mac_out.data_in[108]" out_port="mac_out_36_bit_multiply.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_reg_reg" in_port="mac_out.data_in[108]" out_port="mac_out_36_bit_multiply.datad[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_36_bit_multiply.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_36_bit_multiply.signb"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_36_bit_multiply.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_36_bit_multiply.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_36_bit_multiply.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_36_bit_multiply.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 72 (dataa width + datab width) in this mode -->
                  <direct name="out_c2" input="mac_out_36_bit_multiply.dataout[71:0]" output="mac_out.data_out"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_3" input="mac_out_36_bit_multiply.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_36_bit_multiply.clk"/>
                </interconnect>
              </mode>
              <!-- 36_bit_multiply-->
              <mode name="one_level_adder.input_type{comb}.output_type{comb}">
                <pb_type name="mac_out_one_level_adder" blif_model=".subckt stratixiv_mac_out.opmode{one_level_adder}.input_type{comb}.output_type{comb}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <output name="dataout" num_pins="36"/>
                  <output name="dftout" num_pins="1"/>
                  <!-- 
                       In this mode the block is purely combinational. We model only the main data path, but add 
                       zero delay edges to other possible timing paths through the block.  It is very unlikely 
                       that the non-datapath signals would every end up on the critical path.

                       Maximum delay through the mac_out in this mode is 1765ps, and minimum delay is 763ps,
					             as measured using the 'two level chain out' mode in QII.
                       -->
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_one_level_adder.dataa" out_port="mac_out_one_level_adder.dataout"/>
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_one_level_adder.datab" out_port="mac_out_one_level_adder.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_one_level_adder.signa" out_port="mac_out_one_level_adder.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_one_level_adder.signb" out_port="mac_out_one_level_adder.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_one_level_adder.round" out_port="mac_out_one_level_adder.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_one_level_adder.saturate" out_port="mac_out_one_level_adder.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_one_level_adder.devclrn" out_port="mac_out_one_level_adder.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_one_level_adder.devpor" out_port="mac_out_one_level_adder.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_one_level_adder.aclr" out_port="mac_out_one_level_adder.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_one_level_adder.ena" out_port="mac_out_one_level_adder.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_one_level_adder.dataa" out_port="mac_out_one_level_adder.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_one_level_adder.datab" out_port="mac_out_one_level_adder.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_one_level_adder.signa" out_port="mac_out_one_level_adder.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_one_level_adder.signb" out_port="mac_out_one_level_adder.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_one_level_adder.round" out_port="mac_out_one_level_adder.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_one_level_adder.saturate" out_port="mac_out_one_level_adder.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_one_level_adder.devclrn" out_port="mac_out_one_level_adder.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_one_level_adder.devpor" out_port="mac_out_one_level_adder.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_one_level_adder.ena" out_port="mac_out_one_level_adder.dftout"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_one_level_adder.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_one_level_adder_comb_comb" in_port="mac_out.data_in[0]" out_port="mac_out_one_level_adder.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_one_level_adder_comb_comb" in_port="mac_out.data_in[0]" out_port="mac_out_one_level_adder.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_one_level_adder.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_one_level_adder_comb_comb" in_port="mac_out.data_in[36]" out_port="mac_out_one_level_adder.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_one_level_adder_comb_comb" in_port="mac_out.data_in[36]" out_port="mac_out_one_level_adder.datab[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_one_level_adder.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_one_level_adder.signb"/>
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_one_level_adder.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_one_level_adder.saturate"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_one_level_adder.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_one_level_adder.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_one_level_adder.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_one_level_adder.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 36 (dataa width, NOT dataa width + 1) in this mode -->
                  <direct name="out_c2" input="mac_out_one_level_adder.dataout" output="mac_out.data_out[35:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_3" input="mac_out_one_level_adder.dftout" output="mac_out.signal_out[2]"/>
                </interconnect>
              </mode>
              <!-- one_level_adder-->
              <mode name="one_level_adder.input_type{reg}.output_type{comb}">
                <pb_type name="mac_out_one_level_adder" blif_model=".subckt stratixiv_mac_out.opmode{one_level_adder}.input_type{reg}.output_type{comb}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="36"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has input registers with a combinational output.  

                       Measuring with QII in 'two level adder chain out mode' we arrived at the following values:
                          Input Register Setup Time (iTsu):              99ps
                          Input Register Hold Time (uTh):     	         48ps
					   The following maximum delays through setup analysis in QII:
                          Input Register Clock-to-Q Time (iTcq):         97ps
                          Input delay to the input registers (iTd):     213ps
                          Combinational Output delay to dataout (oTd): 1689ps
					   The following minimum delays through setup analysis in QII:
                          Input Register Clock-to-Q Time (iTcq):         97ps
                          Input delay to the input registers (iTd):      44ps
                          Combinational Output delay to dataout (oTd):  806ps
					   

                       This results in the following Tsu and Tcq times:
                          'data*' Tsu        : iTsu + iTd  =         312 ps
                          'data*' uTh        : uTh - iTd   =           4 ps
                          All other Tsu      : iTsu        =          99 ps
                          All other uTh      : uTh         =          48 ps
                          'data*' Tcq        : iTcq        =   max:   97 ps  |	min: 97 ps
                          'data*' comb delay : oTd         =   max: 1689 ps  | 	min: 806 ps
                          All other Tcq      : iTcq        =   max:   97 ps  |	min: 97 ps
                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_one_level_adder.dataa" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_one_level_adder.datab" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_one_level_adder.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_one_level_adder.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_one_level_adder.round" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_one_level_adder.saturate" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_one_level_adder.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_one_level_adder.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_one_level_adder.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_one_level_adder.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.dataa" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.datab" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.round" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.saturate" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_one_level_adder.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.ena" value="48e-12"/>
                  <!-- Internal input timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_one_level_adder.dataa" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_one_level_adder.datab" max="97e-12" min="97e-12"/>
                  <!-- Output combinational delay -->
                  <delay_constant in_port="mac_out_one_level_adder.dataa" out_port="mac_out_one_level_adder.dataout" max="1689e-12" min="806e-12"/>
                  <delay_constant in_port="mac_out_one_level_adder.datab" out_port="mac_out_one_level_adder.dataout" max="1689e-12" min="806e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_one_level_adder.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_one_level_adder.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_one_level_adder_reg_comb" in_port="mac_out.data_in[0]" out_port="mac_out_one_level_adder.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_one_level_adder_reg_comb" in_port="mac_out.data_in[0]" out_port="mac_out_one_level_adder.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_one_level_adder.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_one_level_adder_reg_comb" in_port="mac_out.data_in[36]" out_port="mac_out_one_level_adder.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_one_level_adder_reg_comb" in_port="mac_out.data_in[36]" out_port="mac_out_one_level_adder.datab[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_one_level_adder.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_one_level_adder.signb"/>
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_one_level_adder.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_one_level_adder.saturate"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_one_level_adder.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_one_level_adder.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_one_level_adder.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_one_level_adder.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 36 (dataa width, NOT dataa width + 1) in this mode -->
                  <direct name="out_c2" input="mac_out_one_level_adder.dataout" output="mac_out.data_out[35:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_3" input="mac_out_one_level_adder.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_one_level_adder.clk"/>
                </interconnect>
              </mode>
              <!-- one_level_adder-->
              <mode name="one_level_adder.input_type{comb}.output_type{reg}">
                <pb_type name="mac_out_one_level_adder" blif_model=".subckt stratixiv_mac_out.opmode{one_level_adder}.input_type{comb}.output_type{reg}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="36"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has a combinational input with a registered out.  

                       Measuring with QII in 'two level adder chain out' mode we arrived at the following values:
                          Output Register Setup Time (oTsu):              99 ps
                          Output Register Hold Time (uTh):                48 ps
					            The following maximum values:
                          Output Register Clock-to-Q Time (oTcq):         97 ps
                          Combinational Output delay to dataout (oTd):   333 ps
                          Input delay to the output registers (iTd):    1227 ps
					            The following minimum values:
                          Output Register Clock-to-Q Time (oTcq):         97 ps
                          Combinational Output delay to dataout (oTd):   180 ps
                          Input delay to the output registers (iTd):     475 ps


                       This results in the following Tsu and Tcq times:
                          'data*' comb delay : iTd         =   max: 1227 ps	 |  min: 475 ps
                          'dataout' Tsu      : oTsu        = 		  99 ps   
                          'dataout' uTh      : uTh         =  		  48 ps   
                          'dataout' Tcq      : oTcq + oTd  =   max:  430 ps	 |  min: 277 ps
                          All others Tcq     : oTcq        =   max:   97 ps	 |  min:  97 ps
                          All others Tsu     : oTsu        = 		  99 ps
                          All others uTh     : uTh         = 		  48 ps
                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_one_level_adder.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_one_level_adder.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_one_level_adder.round" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_one_level_adder.saturate" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_one_level_adder.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_one_level_adder.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_one_level_adder.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_one_level_adder.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.round" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.saturate" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_one_level_adder.ena" value="48e-12"/>
                  <!-- Input combinational delay -->
                  <delay_constant in_port="mac_out_one_level_adder.dataa" out_port="mac_out_one_level_adder.dataout" max="1227e-12" min="475e-12"/>
                  <delay_constant in_port="mac_out_one_level_adder.datab" out_port="mac_out_one_level_adder.dataout" max="1227e-12" min="475e-12"/>
                  <!-- Internal output timing -->
                  <T_setup clock="clk" port="mac_out_one_level_adder.dataout" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.dataout" value="48e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_one_level_adder.dataout" max="430e-12" min="277e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_one_level_adder.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_one_level_adder.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_one_level_adder_comb_reg" in_port="mac_out.data_in[0]" out_port="mac_out_one_level_adder.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_one_level_adder_comb_reg" in_port="mac_out.data_in[0]" out_port="mac_out_one_level_adder.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_one_level_adder.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_one_level_adder_comb_reg" in_port="mac_out.data_in[36]" out_port="mac_out_one_level_adder.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_one_level_adder_comb_reg" in_port="mac_out.data_in[36]" out_port="mac_out_one_level_adder.datab[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_one_level_adder.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_one_level_adder.signb"/>
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_one_level_adder.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_one_level_adder.saturate"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_one_level_adder.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_one_level_adder.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_one_level_adder.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_one_level_adder.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 36 (dataa width, NOT dataa width + 1) in this mode -->
                  <direct name="out_c2" input="mac_out_one_level_adder.dataout" output="mac_out.data_out[35:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_3" input="mac_out_one_level_adder.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_one_level_adder.clk"/>
                </interconnect>
              </mode>
              <!-- one_level_adder-->
              <mode name="one_level_adder.input_type{reg}.output_type{reg}">
                <pb_type name="mac_out_one_level_adder" blif_model=".subckt stratixiv_mac_out.opmode{one_level_adder}.input_type{reg}.output_type{reg}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="36"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has a registered input and a registered out.  
                       We model the combinational input delay as part of the setup time, and
                       the combinational output delay as part of the clock to q time.

                       Note that there may or may not actually have been additional pipelining
                       inside the DSP block, so in this case we are not cycle accurate to Stratix IV.
                       Since Stratix IV DSP blocks are practically limited to an speed of 510MHz,
                       we create an internal combinational path which models ths limit.

                       Measuring with QII in 'two level adder chain out' we arrived at the following values:
                          Input/Output Register Setup Time (iTsu/oTsu):      99ps
                          Input/Output Register Hold Time (uTh):			 48ps
                       We arrived at the following maximum values using QII:
                          Input/Output Register Clock-to-Q Time (iTcq/oTcq): 97ps
                          Combinational Output delay to dataout (oTd):      333ps
                          Input delay to the input registers (iTd):         213ps
                       Also the following minimum values using QII:
                          Input/Output Register Clock-to-Q Time (iTcq/oTcq): 97ps
                          Combinational Output delay to dataout (oTd):      180ps
                          Input delay to the input registers (iTd):          44ps
                          Minimum comb delay  :  456 ps

                       This results in the following Tsu, uTh, and Tcq times:
                          'data*' Tsu        : iTsu + iTd  = 	   312ps
                          'data*' uTh        : uTh - iTd   = 	     4ps 
                          'dataout' Tcq      : oTcq + oTd  =  max: 430ps  |  min: 277ps
                          All others Tcq     : oTcq        =  max:  97ps  |  min: 97ps
                          All others Tsu     : iTsu        = 		99ps
                          All others uTh     : uTh         = 		48ps

                          Internal Tsu: iTsu               =        99ps
                          Internal uTh:  uTh               =        48ps
                          Internal Tcq: iTcq               =        97ps

                          Maximum comb delay  : (1 / 510MHz) - iTsu - iTcq = 1765ps

                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_one_level_adder.dataa" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_one_level_adder.datab" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_one_level_adder.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_one_level_adder.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_one_level_adder.round" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_one_level_adder.saturate" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_one_level_adder.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_one_level_adder.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_one_level_adder.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_one_level_adder.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.dataa" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.datab" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.round" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.saturate" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_one_level_adder.ena" value="48e-12"/>
                  <!-- Internal input timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_one_level_adder.dataa" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_one_level_adder.datab" max="97e-12" min="97e-12"/>
                  <!-- Internal combinational delay -->
                  <delay_constant in_port="mac_out_one_level_adder.dataa" out_port="mac_out_one_level_adder.dataout" max="1765e-12" min="456e-12"/>
                  <delay_constant in_port="mac_out_one_level_adder.datab" out_port="mac_out_one_level_adder.dataout" max="1765e-12" min="456e-12"/>
                  <!-- Internal output timing -->
                  <T_setup clock="clk" port="mac_out_one_level_adder.dataout" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_one_level_adder.dataout" value="48e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_one_level_adder.dataout" max="430e-12" min="277e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_one_level_adder.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_one_level_adder.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_one_level_adder_reg_reg" in_port="mac_out.data_in[0]" out_port="mac_out_one_level_adder.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_one_level_adder_reg_reg" in_port="mac_out.data_in[0]" out_port="mac_out_one_level_adder.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_one_level_adder.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_one_level_adder_reg_reg" in_port="mac_out.data_in[36]" out_port="mac_out_one_level_adder.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_one_level_adder_reg_reg" in_port="mac_out.data_in[36]" out_port="mac_out_one_level_adder.datab[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_one_level_adder.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_one_level_adder.signb"/>
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_one_level_adder.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_one_level_adder.saturate"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_one_level_adder.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_one_level_adder.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_one_level_adder.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_one_level_adder.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 36 (dataa width, NOT dataa width + 1) in this mode -->
                  <direct name="out_c2" input="mac_out_one_level_adder.dataout" output="mac_out.data_out[35:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_3" input="mac_out_one_level_adder.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_one_level_adder.clk"/>
                </interconnect>
              </mode>
              <!-- one_level_adder-->
              <mode name="double.input_type{comb}.output_type{comb}">
                <pb_type name="mac_out_double" blif_model=".subckt stratixiv_mac_out.opmode{double}.input_type{comb}.output_type{comb}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <output name="dataout" num_pins="55"/>
                  <output name="dftout" num_pins="1"/>
                  <!-- 
                       In this mode the block is purely combinational. We model only the main data path, but add 
                       zero delay edges to other possible timing paths through the block.  It is very unlikely 
                       that the non-datapath signals would every end up on the critical path.

                       Maximum delay through the mac_out in this mode is 1765ps, and minimum delay is 763ps,
					   as measured using the 'two level chain out' mode in QII.
                       -->
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_double.dataa" out_port="mac_out_double.dataout"/>
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_double.datab" out_port="mac_out_double.dataout"/>
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_double.datac" out_port="mac_out_double.dataout"/>
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_double.datad" out_port="mac_out_double.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_double.signa" out_port="mac_out_double.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_double.signb" out_port="mac_out_double.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_double.devclrn" out_port="mac_out_double.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_double.devpor" out_port="mac_out_double.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_double.aclr" out_port="mac_out_double.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_double.ena" out_port="mac_out_double.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_double.dataa" out_port="mac_out_double.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_double.datab" out_port="mac_out_double.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_double.datac" out_port="mac_out_double.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_double.datad" out_port="mac_out_double.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_double.signa" out_port="mac_out_double.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_double.signb" out_port="mac_out_double.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_double.devclrn" out_port="mac_out_double.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_double.devpor" out_port="mac_out_double.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_double.ena" out_port="mac_out_double.dftout"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_double.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_double_comb_comb" in_port="mac_out.data_in[0]" out_port="mac_out_double.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_double_comb_comb" in_port="mac_out.data_in[0]" out_port="mac_out_double.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_double.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_double_comb_comb" in_port="mac_out.data_in[36]" out_port="mac_out_double.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_double_comb_comb" in_port="mac_out.data_in[36]" out_port="mac_out_double.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_double.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_double_comb_comb" in_port="mac_out.data_in[72]" out_port="mac_out_double.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_double_comb_comb" in_port="mac_out.data_in[72]" out_port="mac_out_double.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_double.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_double_comb_comb" in_port="mac_out.data_in[108]" out_port="mac_out_double.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_double_comb_comb" in_port="mac_out.data_in[108]" out_port="mac_out_double.datad[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_double.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_double.signb"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_double.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_double.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_double.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_double.ena"/>
                  <!-- Data output -->
                  <direct name="out_c2" input="mac_out_double.dataout" output="mac_out.data_out[54:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_3" input="mac_out_double.dftout" output="mac_out.signal_out[2]"/>
                </interconnect>
              </mode>
              <!-- double-->
              <mode name="double.input_type{reg}.output_type{comb}">
                <pb_type name="mac_out_double" blif_model=".subckt stratixiv_mac_out.opmode{double}.input_type{reg}.output_type{comb}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="55"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has input registers with a combinational output.  

                       Measuring with QII in 'two level adder chain out mode' we arrived at the following values:
                          Input Register Setup Time (iTsu):              99ps
                          Input Register Hold Time (uTh):     	         48ps
					            The following maximum delays through setup analysis in QII:
                          Input Register Clock-to-Q Time (iTcq):         97ps
                          Input delay to the input registers (iTd):     213ps
                          Combinational Output delay to dataout (oTd): 1689ps
					            The following minimum delays through setup analysis in QII:
                          Input Register Clock-to-Q Time (iTcq):         97ps
                          Input delay to the input registers (iTd):      44ps
                          Combinational Output delay to dataout (oTd):  806ps
					   

                       This results in the following Tsu and Tcq times:
                          'data*' Tsu        : iTsu + iTd  =         312 ps
                          'data*' uTh        : uTh - iTd   =           4ps
                          All other Tsu      : iTsu        =          99 ps
                          All other uTh      : uTh         =          48 ps
                          'data*' Tcq        : iTcq        =   max:   97 ps  |	min: 97 ps
                          'data*' comb delay : oTd         =   max: 1689 ps  | 	min: 806 ps
                          All other Tcq      : iTcq        =   max:   97 ps  |	min: 97 ps
                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_double.dataa" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_double.datab" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_double.datac" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_double.datad" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_double.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_double.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_double.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_double.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_double.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_double.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_double.dataa" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_double.datab" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_double.datac" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_double.datad" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_double.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_double.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_double.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_double.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_double.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_double.ena" value="48e-12"/>
                  <!-- Internal input timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_double.dataa" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_double.datab" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_double.datac" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_double.datad" max="97e-12" min="97e-12"/>
                  <!-- Output combinational delay -->
                  <delay_constant in_port="mac_out_double.dataa" out_port="mac_out_double.dataout" max="1689e-12" min="806e-12"/>
                  <delay_constant in_port="mac_out_double.datab" out_port="mac_out_double.dataout" max="1689e-12" min="806e-12"/>
                  <delay_constant in_port="mac_out_double.datac" out_port="mac_out_double.dataout" max="1689e-12" min="806e-12"/>
                  <delay_constant in_port="mac_out_double.datad" out_port="mac_out_double.dataout" max="1689e-12" min="806e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_double.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_double.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_double_reg_comb" in_port="mac_out.data_in[0]" out_port="mac_out_double.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_double_reg_comb" in_port="mac_out.data_in[0]" out_port="mac_out_double.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_double.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_double_reg_comb" in_port="mac_out.data_in[36]" out_port="mac_out_double.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_double_reg_comb" in_port="mac_out.data_in[36]" out_port="mac_out_double.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_double.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_double_reg_comb" in_port="mac_out.data_in[72]" out_port="mac_out_double.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_double_reg_comb" in_port="mac_out.data_in[72]" out_port="mac_out_double.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_double.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_double_reg_comb" in_port="mac_out.data_in[108]" out_port="mac_out_double.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_double_reg_comb" in_port="mac_out.data_in[108]" out_port="mac_out_double.datad[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_double.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_double.signb"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_double.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_double.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_double.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_double.ena"/>
                  <!-- Data output -->
                  <direct name="out_c2" input="mac_out_double.dataout" output="mac_out.data_out[54:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_3" input="mac_out_double.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_double.clk"/>
                </interconnect>
              </mode>
              <!-- double-->
              <mode name="double.input_type{comb}.output_type{reg}">
                <pb_type name="mac_out_double" blif_model=".subckt stratixiv_mac_out.opmode{double}.input_type{comb}.output_type{reg}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="55"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has a combinational input with a registered out.  

                       Measuring with QII in 'two level adder chain out' mode we arrived at the following values:
                          Output Register Setup Time (oTsu):              99 ps
                          Output Register Hold Time (uTh):                48 ps
					   The following maximum values:
                          Output Register Clock-to-Q Time (oTcq):         97 ps
                          Combinational Output delay to dataout (oTd):   333 ps
                          Input delay to the output registers (iTd):    1227 ps
					   The following minimum values:
                          Output Register Clock-to-Q Time (oTcq):         97 ps
                          Combinational Output delay to dataout (oTd):   180 ps
                          Input delay to the output registers (iTd):     475 ps


                       This results in the following Tsu and Tcq times:
                          'data*' comb delay : iTd         =   max: 1227 ps	 |  min: 475 ps
                          'dataout' Tsu      : oTsu        = 		  99 ps   
                          'dataout' uTh      : uTh         =  		  48 ps   
                          'dataout' Tcq      : oTcq + oTd  =   max:  430 ps	 |  min: 277 ps
                          All others Tcq     : oTcq        =   max:   97 ps	 |  min:  97 ps
                          All others Tsu     : oTsu        = 		  99 ps
                          All others uTh     : uTh         = 		  48 ps
                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_double.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_double.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_double.ena" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_double.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_double.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_double.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_double.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_double.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_double.ena" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_double.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_double.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_double.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <!-- Input combinational delay -->
                  <delay_constant in_port="mac_out_double.dataa" out_port="mac_out_double.dataout" max="1227e-12" min="475e-12"/>
                  <delay_constant in_port="mac_out_double.datab" out_port="mac_out_double.dataout" max="1227e-12" min="475e-12"/>
                  <delay_constant in_port="mac_out_double.datac" out_port="mac_out_double.dataout" max="1227e-12" min="475e-12"/>
                  <delay_constant in_port="mac_out_double.datad" out_port="mac_out_double.dataout" max="1227e-12" min="475e-12"/>
                  <!-- Internal output timing -->
                  <T_setup clock="clk" port="mac_out_double.dataout" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_double.dataout" value="48e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_double.dataout" max="430e-12" min="277e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_double.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_double.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_double_comb_reg" in_port="mac_out.data_in[0]" out_port="mac_out_double.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_double_comb_reg" in_port="mac_out.data_in[0]" out_port="mac_out_double.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_double.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_double_comb_reg" in_port="mac_out.data_in[36]" out_port="mac_out_double.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_double_comb_reg" in_port="mac_out.data_in[36]" out_port="mac_out_double.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_double.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_double_comb_reg" in_port="mac_out.data_in[72]" out_port="mac_out_double.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_double_comb_reg" in_port="mac_out.data_in[72]" out_port="mac_out_double.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_double.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_double_comb_reg" in_port="mac_out.data_in[108]" out_port="mac_out_double.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_double_comb_reg" in_port="mac_out.data_in[108]" out_port="mac_out_double.datad[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_double.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_double.signb"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_double.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_double.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_double.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_double.ena"/>
                  <!-- Data output -->
                  <direct name="out_c2" input="mac_out_double.dataout" output="mac_out.data_out[54:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_3" input="mac_out_double.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_double.clk"/>
                </interconnect>
              </mode>
              <!-- double-->
              <mode name="double.input_type{reg}.output_type{reg}">
                <pb_type name="mac_out_double" blif_model=".subckt stratixiv_mac_out.opmode{double}.input_type{reg}.output_type{reg}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="55"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has a registered input and a registered out.  
                       We model the combinational input delay as part of the setup time, and
                       the combinational output delay as part of the clock to q time.

                       Note that there may or may not actually have been additional pipelining
                       inside the DSP block, so in this case we are not cycle accurate to Stratix IV.
                       Since Stratix IV DSP blocks are practically limited to an speed of 510MHz,
                       we create an internal combinational path which models ths limit.

                       Measuring with QII in 'two level adder chain out' we arrived at the following values:
                          Input/Output Register Setup Time (iTsu/oTsu):      99ps
                          Input/Output Register Hold Time (uTh):			 48ps
                       We arrived at the following maximum values using QII:
                          Input/Output Register Clock-to-Q Time (iTcq/oTcq): 97ps
                          Combinational Output delay to dataout (oTd):      333ps
                          Input delay to the input registers (iTd):         213ps
                       Also the following minimum values using QII:
                          Input/Output Register Clock-to-Q Time (iTcq/oTcq): 97ps
                          Combinational Output delay to dataout (oTd):      180ps
                          Input delay to the input registers (iTd):          44ps
                          Minimum comb delay  :  456 ps

                       This results in the following Tsu, uTh, and Tcq times:
                          'data*' Tsu        : iTsu + iTd  = 	   312ps
                          'data*' uTh        : uTh - iTd   = 	     4ps 
                          'dataout' Tcq      : oTcq + oTd  =  max: 430ps  |  min: 277ps
                          All others Tcq     : oTcq        =  max:  97ps  |  min: 97ps
                          All others Tsu     : iTsu        = 		99ps
                          All others uTh     : uTh         = 		48ps

                          Internal Tsu: iTsu               =        99ps
                          Internal uTh:  uTh               =        48ps
                          Internal Tcq: iTcq               =        97ps

                          Maximum comb delay  : (1 / 510MHz) - iTsu - iTcq = 1765ps

                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_double.dataa" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_double.datab" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_double.datac" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_double.datad" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_double.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_double.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_double.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_double.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_double.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_double.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_double.dataa" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_double.datab" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_double.datac" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_double.datad" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_double.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_double.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_double.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_double.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_double.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_double.ena" value="48e-12"/>
                  <!-- Internal input timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_double.dataa" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_double.datab" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_double.datac" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_double.datad" max="97e-12" min="97e-12"/>
                  <!-- Internal combinational delay -->
                  <delay_constant in_port="mac_out_double.dataa" out_port="mac_out_double.dataout" max="1765e-12" min="456e-12"/>
                  <delay_constant in_port="mac_out_double.datab" out_port="mac_out_double.dataout" max="1765e-12" min="456e-12"/>
                  <delay_constant in_port="mac_out_double.datac" out_port="mac_out_double.dataout" max="1765e-12" min="456e-12"/>
                  <delay_constant in_port="mac_out_double.datad" out_port="mac_out_double.dataout" max="1765e-12" min="456e-12"/>
                  <!-- Internal output timing -->
                  <T_setup clock="clk" port="mac_out_double.dataout" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_double.dataout" value="48e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_double.dataout" max="430e-12" min="277e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_double.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_double.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_double_reg_reg" in_port="mac_out.data_in[0]" out_port="mac_out_double.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_double_reg_reg" in_port="mac_out.data_in[0]" out_port="mac_out_double.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_double.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_double_reg_reg" in_port="mac_out.data_in[36]" out_port="mac_out_double.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_double_reg_reg" in_port="mac_out.data_in[36]" out_port="mac_out_double.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_double.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_double_reg_reg" in_port="mac_out.data_in[72]" out_port="mac_out_double.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_double_reg_reg" in_port="mac_out.data_in[72]" out_port="mac_out_double.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_double.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_double_reg_reg" in_port="mac_out.data_in[108]" out_port="mac_out_double.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_double_reg_reg" in_port="mac_out.data_in[108]" out_port="mac_out_double.datad[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_double.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_double.signb"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_double.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_double.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_double.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_double.ena"/>
                  <!-- Data output -->
                  <direct name="out_c2" input="mac_out_double.dataout" output="mac_out.data_out[54:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_3" input="mac_out_double.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_double.clk"/>
                </interconnect>
              </mode>
              <!-- double-->
              <mode name="two_level_adder.input_type{comb}.output_type{comb}">
                <pb_type name="mac_out_two_level_adder" blif_model=".subckt stratixiv_mac_out.opmode{two_level_adder}.input_type{comb}.output_type{comb}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <output name="dataout" num_pins="38"/>
                  <output name="overflow" num_pins="1"/>
                  <output name="dftout" num_pins="1"/>
                  <!-- 
                       In this mode the block is purely combinational. We model only the main data path, but add 
                       zero delay edges to other possible timing paths through the block.  It is very unlikely 
                       that the non-datapath signals would every end up on the critical path.

                       Maximum delay through the mac_out in this mode is 1765ps, and minimum delay is 763ps,
					   as measured using the 'two level chain out' mode in QII.
                       -->
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_two_level_adder.dataa" out_port="mac_out_two_level_adder.dataout"/>
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_two_level_adder.datab" out_port="mac_out_two_level_adder.dataout"/>
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_two_level_adder.datac" out_port="mac_out_two_level_adder.dataout"/>
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_two_level_adder.datad" out_port="mac_out_two_level_adder.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.signa" out_port="mac_out_two_level_adder.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.signb" out_port="mac_out_two_level_adder.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.round" out_port="mac_out_two_level_adder.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.saturate" out_port="mac_out_two_level_adder.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.devclrn" out_port="mac_out_two_level_adder.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.devpor" out_port="mac_out_two_level_adder.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.aclr" out_port="mac_out_two_level_adder.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.ena" out_port="mac_out_two_level_adder.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.dataa" out_port="mac_out_two_level_adder.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.datab" out_port="mac_out_two_level_adder.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.datac" out_port="mac_out_two_level_adder.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.datad" out_port="mac_out_two_level_adder.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.signa" out_port="mac_out_two_level_adder.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.signb" out_port="mac_out_two_level_adder.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.round" out_port="mac_out_two_level_adder.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.saturate" out_port="mac_out_two_level_adder.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.devclrn" out_port="mac_out_two_level_adder.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.devpor" out_port="mac_out_two_level_adder.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.ena" out_port="mac_out_two_level_adder.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.dataa" out_port="mac_out_two_level_adder.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.datab" out_port="mac_out_two_level_adder.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.datac" out_port="mac_out_two_level_adder.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.datad" out_port="mac_out_two_level_adder.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.signa" out_port="mac_out_two_level_adder.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.signb" out_port="mac_out_two_level_adder.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.round" out_port="mac_out_two_level_adder.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.saturate" out_port="mac_out_two_level_adder.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.devclrn" out_port="mac_out_two_level_adder.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.devpor" out_port="mac_out_two_level_adder.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder.ena" out_port="mac_out_two_level_adder.overflow"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_two_level_adder.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_comb_comb" in_port="mac_out.data_in[0]" out_port="mac_out_two_level_adder.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_comb_comb" in_port="mac_out.data_in[0]" out_port="mac_out_two_level_adder.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_two_level_adder.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_comb_comb" in_port="mac_out.data_in[36]" out_port="mac_out_two_level_adder.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_comb_comb" in_port="mac_out.data_in[36]" out_port="mac_out_two_level_adder.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_two_level_adder.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_comb_comb" in_port="mac_out.data_in[72]" out_port="mac_out_two_level_adder.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_comb_comb" in_port="mac_out.data_in[72]" out_port="mac_out_two_level_adder.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_two_level_adder.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_comb_comb" in_port="mac_out.data_in[108]" out_port="mac_out_two_level_adder.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_comb_comb" in_port="mac_out.data_in[108]" out_port="mac_out_two_level_adder.datad[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_two_level_adder.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_two_level_adder.signb"/>
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_two_level_adder.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_two_level_adder.saturate"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_two_level_adder.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_two_level_adder.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_two_level_adder.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_two_level_adder.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 38 (dataa width + 2) in this mode -->
                  <direct name="out_c2" input="mac_out_two_level_adder.dataout" output="mac_out.data_out[37:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_1" input="mac_out_two_level_adder.overflow" output="mac_out.signal_out[0]"/>
                  <direct name="signal_3" input="mac_out_two_level_adder.dftout" output="mac_out.signal_out[2]"/>
                </interconnect>
              </mode>
              <!-- two_level_adder -->
              <mode name="two_level_adder.input_type{reg}.output_type{comb}">
                <pb_type name="mac_out_two_level_adder" blif_model=".subckt stratixiv_mac_out.opmode{two_level_adder}.input_type{reg}.output_type{comb}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="38"/>
                  <output name="overflow" num_pins="1"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has input registers with a combinational output.  

                       Measuring with QII in 'two level adder chain out mode' we arrived at the following values:
                          Input Register Setup Time (iTsu):              99ps
                          Input Register Hold Time (uTh):     	         48ps
					            The following maximum delays through setup analysis in QII:
                          Input Register Clock-to-Q Time (iTcq):         97ps
                          Input delay to the input registers (iTd):     213ps
                          Combinational Output delay to dataout (oTd): 1689ps
					            The following minimum delays through setup analysis in QII:
                          Input Register Clock-to-Q Time (iTcq):         97ps
                          Input delay to the input registers (iTd):      44ps
                          Combinational Output delay to dataout (oTd):  806ps
					   

                       This results in the following Tsu and Tcq times:
                          'data*' Tsu        : iTsu + iTd  =         312 ps
                          'data*' uTh        : uTh - iTd   =           4 ps
                          All other Tsu      : iTsu        =          99 ps
                          All other uTh      : uTh         =          48 ps
                          'data*' Tcq        : iTcq        =   max:   97 ps  |	min: 97 ps
                          'data*' comb delay : oTd         =   max: 1689 ps  | 	min: 806 ps
                          All other Tcq      : iTcq        =   max:   97 ps  |	min: 97 ps
                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_two_level_adder.dataa" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.datab" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.datac" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.datad" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.round" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.saturate" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_two_level_adder.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.dataa" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.datab" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.datac" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.datad" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.round" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.saturate" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_two_level_adder.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.ena" value="48e-12"/>
                  <!-- Internal input timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder.dataa" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder.datab" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder.datac" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder.datad" max="97e-12" min="97e-12"/>
                  <!-- Output combinational delay -->
                  <delay_constant in_port="mac_out_two_level_adder.dataa" out_port="mac_out_two_level_adder.dataout" max="1689e-12" min="806e-12"/>
                  <delay_constant in_port="mac_out_two_level_adder.datab" out_port="mac_out_two_level_adder.dataout" max="1689e-12" min="806e-12"/>
                  <delay_constant in_port="mac_out_two_level_adder.datac" out_port="mac_out_two_level_adder.dataout" max="1689e-12" min="806e-12"/>
                  <delay_constant in_port="mac_out_two_level_adder.datad" out_port="mac_out_two_level_adder.dataout" max="1689e-12" min="806e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder.overflow" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_two_level_adder.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_reg_comb" in_port="mac_out.data_in[0]" out_port="mac_out_two_level_adder.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_reg_comb" in_port="mac_out.data_in[0]" out_port="mac_out_two_level_adder.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_two_level_adder.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_reg_comb" in_port="mac_out.data_in[36]" out_port="mac_out_two_level_adder.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_reg_comb" in_port="mac_out.data_in[36]" out_port="mac_out_two_level_adder.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_two_level_adder.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_reg_comb" in_port="mac_out.data_in[72]" out_port="mac_out_two_level_adder.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_reg_comb" in_port="mac_out.data_in[72]" out_port="mac_out_two_level_adder.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_two_level_adder.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_reg_comb" in_port="mac_out.data_in[108]" out_port="mac_out_two_level_adder.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_reg_comb" in_port="mac_out.data_in[108]" out_port="mac_out_two_level_adder.datad[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_two_level_adder.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_two_level_adder.signb"/>
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_two_level_adder.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_two_level_adder.saturate"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_two_level_adder.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_two_level_adder.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_two_level_adder.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_two_level_adder.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 38 (dataa width + 2) in this mode -->
                  <direct name="out_c2" input="mac_out_two_level_adder.dataout" output="mac_out.data_out[37:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_1" input="mac_out_two_level_adder.overflow" output="mac_out.signal_out[0]"/>
                  <direct name="signal_3" input="mac_out_two_level_adder.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_two_level_adder.clk"/>
                </interconnect>
              </mode>
              <!-- two_level_adder -->
              <mode name="two_level_adder.input_type{comb}.output_type{reg}">
                <pb_type name="mac_out_two_level_adder" blif_model=".subckt stratixiv_mac_out.opmode{two_level_adder}.input_type{comb}.output_type{reg}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="38"/>
                  <output name="overflow" num_pins="1"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has a combinational input with a registered out.  

                       Measuring with QII in 'two level adder chain out' mode we arrived at the following values:
                          Output Register Setup Time (oTsu):              99 ps
                          Output Register Hold Time (uTh):                48 ps
					   The following maximum values:
                          Output Register Clock-to-Q Time (oTcq):         97 ps
                          Combinational Output delay to dataout (oTd):   333 ps
                          Input delay to the output registers (iTd):    1227 ps
					   The following minimum values:
                          Output Register Clock-to-Q Time (oTcq):         97 ps
                          Combinational Output delay to dataout (oTd):   180 ps
                          Input delay to the output registers (iTd):     475 ps


                       This results in the following Tsu and Tcq times:
                          'data*' comb delay : iTd         =   max: 1227 ps	 |  min: 475 ps
                          'dataout' Tsu      : oTsu        = 		  99 ps   
                          'dataout' uTh      : uTh         =  		  48 ps   
                          'dataout' Tcq      : oTcq + oTd  =   max:  430 ps	 |  min: 277 ps
                          All others Tcq     : oTcq        =   max:   97 ps	 |  min:  97 ps
                          All others Tsu     : oTsu        = 		  99 ps
                          All others uTh     : uTh         = 		  48 ps
                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_two_level_adder.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.round" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.saturate" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_two_level_adder.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.round" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.saturate" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_two_level_adder.ena" value="48e-12"/>
                  <!-- Input combinational delay -->
                  <delay_constant in_port="mac_out_two_level_adder.dataa" out_port="mac_out_two_level_adder.dataout" max="1227e-12" min="475e-12"/>
                  <delay_constant in_port="mac_out_two_level_adder.datab" out_port="mac_out_two_level_adder.dataout" max="1227e-12" min="475e-12"/>
                  <delay_constant in_port="mac_out_two_level_adder.datac" out_port="mac_out_two_level_adder.dataout" max="1227e-12" min="475e-12"/>
                  <delay_constant in_port="mac_out_two_level_adder.datad" out_port="mac_out_two_level_adder.dataout" max="1227e-12" min="475e-12"/>
                  <!-- Internal output timing -->
                  <T_setup clock="clk" port="mac_out_two_level_adder.dataout" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.dataout" value="48e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder.dataout" max="430e-12" min="277e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder.overflow" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_two_level_adder.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_comb_reg" in_port="mac_out.data_in[0]" out_port="mac_out_two_level_adder.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_comb_reg" in_port="mac_out.data_in[0]" out_port="mac_out_two_level_adder.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_two_level_adder.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_comb_reg" in_port="mac_out.data_in[36]" out_port="mac_out_two_level_adder.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_comb_reg" in_port="mac_out.data_in[36]" out_port="mac_out_two_level_adder.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_two_level_adder.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_comb_reg" in_port="mac_out.data_in[72]" out_port="mac_out_two_level_adder.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_comb_reg" in_port="mac_out.data_in[72]" out_port="mac_out_two_level_adder.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_two_level_adder.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_comb_reg" in_port="mac_out.data_in[108]" out_port="mac_out_two_level_adder.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_comb_reg" in_port="mac_out.data_in[108]" out_port="mac_out_two_level_adder.datad[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_two_level_adder.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_two_level_adder.signb"/>
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_two_level_adder.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_two_level_adder.saturate"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_two_level_adder.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_two_level_adder.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_two_level_adder.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_two_level_adder.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 38 (dataa width + 2) in this mode -->
                  <direct name="out_c2" input="mac_out_two_level_adder.dataout" output="mac_out.data_out[37:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_1" input="mac_out_two_level_adder.overflow" output="mac_out.signal_out[0]"/>
                  <direct name="signal_3" input="mac_out_two_level_adder.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_two_level_adder.clk"/>
                </interconnect>
              </mode>
              <!-- two_level_adder -->
              <mode name="two_level_adder.input_type{reg}.output_type{reg}">
                <pb_type name="mac_out_two_level_adder" blif_model=".subckt stratixiv_mac_out.opmode{two_level_adder}.input_type{reg}.output_type{reg}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="38"/>
                  <output name="overflow" num_pins="1"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has a registered input and a registered out.  
                       We model the combinational input delay as part of the setup time, and
                       the combinational output delay as part of the clock to q time.

                       Note that there may or may not actually have been additional pipelining
                       inside the DSP block, so in this case we are not cycle accurate to Stratix IV.
                       Since Stratix IV DSP blocks are practically limited to an speed of 510MHz,
                       we create an internal combinational path which models ths limit.

                       Measuring with QII in 'two level adder chain out' we arrived at the following values:
                          Input/Output Register Setup Time (iTsu/oTsu):      99ps
                          Input/Output Register Hold Time (uTh):			 48ps
                       We arrived at the following maximum values using QII:
                          Input/Output Register Clock-to-Q Time (iTcq/oTcq): 97ps
                          Combinational Output delay to dataout (oTd):      333ps
                          Input delay to the input registers (iTd):         213ps
                       Also the following minimum values using QII:
                          Input/Output Register Clock-to-Q Time (iTcq/oTcq): 97ps
                          Combinational Output delay to dataout (oTd):      180ps
                          Input delay to the input registers (iTd):          44ps
                          Minimum comb delay  :                            456 ps

                       This results in the following Tsu, uTh, and Tcq times:
                          'data*' Tsu        : iTsu + iTd  = 	   312ps
                          'data*' uTh        : uTh - iTd   = 	     4ps 
                          'dataout' Tcq      : oTcq + oTd  =  max: 430ps  |  min: 277ps
                          All others Tcq     : oTcq        =  max:  97ps  |  min: 97ps
                          All others Tsu     : iTsu        = 		99ps
                          All others uTh     : uTh         = 		48ps

                          Internal Tsu: iTsu               =        99ps
                          Internal uTh:  uTh               =        48ps
                          Internal Tcq: iTcq               =        97ps

                          Maximum comb delay  : (1 / 510MHz) - iTsu - iTcq = 1765ps

                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_two_level_adder.dataa" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.datab" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.datac" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.datad" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.round" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.saturate" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_two_level_adder.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.dataa" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.datab" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.datac" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.datad" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.round" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.saturate" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_two_level_adder.ena" value="48e-12"/>
                  <!-- Internal input timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder.dataa" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder.datab" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder.datac" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder.datad" max="97e-12" min="97e-12"/>
                  <!-- Internal combinational delay -->
                  <delay_constant in_port="mac_out_two_level_adder.dataa" out_port="mac_out_two_level_adder.dataout" max="1765e-12" min="456e-12"/>
                  <delay_constant in_port="mac_out_two_level_adder.datab" out_port="mac_out_two_level_adder.dataout" max="1765e-12" min="456e-12"/>
                  <delay_constant in_port="mac_out_two_level_adder.datac" out_port="mac_out_two_level_adder.dataout" max="1765e-12" min="456e-12"/>
                  <delay_constant in_port="mac_out_two_level_adder.datad" out_port="mac_out_two_level_adder.dataout" max="1765e-12" min="456e-12"/>
                  <!-- Internal output timing -->
                  <T_setup clock="clk" port="mac_out_two_level_adder.dataout" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder.dataout" value="48e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder.dataout" max="430e-12" min="277e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder.overflow" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_two_level_adder.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_reg_reg" in_port="mac_out.data_in[0]" out_port="mac_out_two_level_adder.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_reg_reg" in_port="mac_out.data_in[0]" out_port="mac_out_two_level_adder.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_two_level_adder.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_reg_reg" in_port="mac_out.data_in[36]" out_port="mac_out_two_level_adder.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_reg_reg" in_port="mac_out.data_in[36]" out_port="mac_out_two_level_adder.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_two_level_adder.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_reg_reg" in_port="mac_out.data_in[72]" out_port="mac_out_two_level_adder.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_reg_reg" in_port="mac_out.data_in[72]" out_port="mac_out_two_level_adder.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_two_level_adder.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_reg_reg" in_port="mac_out.data_in[108]" out_port="mac_out_two_level_adder.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_reg_reg" in_port="mac_out.data_in[108]" out_port="mac_out_two_level_adder.datad[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_two_level_adder.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_two_level_adder.signb"/>
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_two_level_adder.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_two_level_adder.saturate"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_two_level_adder.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_two_level_adder.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_two_level_adder.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_two_level_adder.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 38 (dataa width + 2) in this mode -->
                  <direct name="out_c2" input="mac_out_two_level_adder.dataout" output="mac_out.data_out[37:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_1" input="mac_out_two_level_adder.overflow" output="mac_out.signal_out[0]"/>
                  <direct name="signal_3" input="mac_out_two_level_adder.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_two_level_adder.clk"/>
                </interconnect>
              </mode>
              <!-- two_level_adder -->
              <mode name="two_level_adder_chain_out.input_type{comb}.output_type{comb}">
                <pb_type name="mac_out_two_level_adder_chain_out" blif_model=".subckt stratixiv_mac_out.opmode{two_level_adder_chain_out}.input_type{comb}.output_type{comb}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="chainin" num_pins="44"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="roundchainout" num_pins="1"/>
                  <input name="saturatechainout" num_pins="1"/>
                  <input name="zerochainout" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <output name="dataout" num_pins="44"/>
                  <output name="overflow" num_pins="1"/>
                  <output name="saturatechainoutoverflow" num_pins="1"/>
                  <output name="dftout" num_pins="1"/>
                  <!-- 
                       In this mode the block is purely combinational. We model only the main data path, but add 
                       zero delay edges to other possible timing paths through the block.  It is very unlikely 
                       that the non-datapath signals would every end up on the critical path.

                       Maximum delay through the mac_out in this mode is 1765ps, and minimum delay is 763ps,
					   as measured using the 'two level chain out' mode in QII.
                       -->
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_two_level_adder_chain_out.dataa" out_port="mac_out_two_level_adder_chain_out.dataout"/>
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_two_level_adder_chain_out.datab" out_port="mac_out_two_level_adder_chain_out.dataout"/>
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_two_level_adder_chain_out.datac" out_port="mac_out_two_level_adder_chain_out.dataout"/>
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_two_level_adder_chain_out.datad" out_port="mac_out_two_level_adder_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.chainin" out_port="mac_out_two_level_adder_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.signa" out_port="mac_out_two_level_adder_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.signb" out_port="mac_out_two_level_adder_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.round" out_port="mac_out_two_level_adder_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.saturate" out_port="mac_out_two_level_adder_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.roundchainout" out_port="mac_out_two_level_adder_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.saturatechainout" out_port="mac_out_two_level_adder_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.zerochainout" out_port="mac_out_two_level_adder_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.devclrn" out_port="mac_out_two_level_adder_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.devpor" out_port="mac_out_two_level_adder_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.aclr" out_port="mac_out_two_level_adder_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.ena" out_port="mac_out_two_level_adder_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.dataa" out_port="mac_out_two_level_adder_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.datab" out_port="mac_out_two_level_adder_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.datac" out_port="mac_out_two_level_adder_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.datad" out_port="mac_out_two_level_adder_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.chainin" out_port="mac_out_two_level_adder_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.signa" out_port="mac_out_two_level_adder_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.signb" out_port="mac_out_two_level_adder_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.round" out_port="mac_out_two_level_adder_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.saturate" out_port="mac_out_two_level_adder_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.roundchainout" out_port="mac_out_two_level_adder_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.saturatechainout" out_port="mac_out_two_level_adder_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.zerochainout" out_port="mac_out_two_level_adder_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.devclrn" out_port="mac_out_two_level_adder_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.devpor" out_port="mac_out_two_level_adder_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.ena" out_port="mac_out_two_level_adder_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.dataa" out_port="mac_out_two_level_adder_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.datab" out_port="mac_out_two_level_adder_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.datac" out_port="mac_out_two_level_adder_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.datad" out_port="mac_out_two_level_adder_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.chainin" out_port="mac_out_two_level_adder_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.signa" out_port="mac_out_two_level_adder_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.signb" out_port="mac_out_two_level_adder_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.round" out_port="mac_out_two_level_adder_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.saturate" out_port="mac_out_two_level_adder_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.roundchainout" out_port="mac_out_two_level_adder_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.saturatechainout" out_port="mac_out_two_level_adder_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.zerochainout" out_port="mac_out_two_level_adder_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.devclrn" out_port="mac_out_two_level_adder_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.devpor" out_port="mac_out_two_level_adder_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.ena" out_port="mac_out_two_level_adder_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.dataa" out_port="mac_out_two_level_adder_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.datab" out_port="mac_out_two_level_adder_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.datac" out_port="mac_out_two_level_adder_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.datad" out_port="mac_out_two_level_adder_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.chainin" out_port="mac_out_two_level_adder_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.signa" out_port="mac_out_two_level_adder_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.signb" out_port="mac_out_two_level_adder_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.round" out_port="mac_out_two_level_adder_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.saturate" out_port="mac_out_two_level_adder_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.roundchainout" out_port="mac_out_two_level_adder_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.saturatechainout" out_port="mac_out_two_level_adder_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.zerochainout" out_port="mac_out_two_level_adder_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.devclrn" out_port="mac_out_two_level_adder_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.devpor" out_port="mac_out_two_level_adder_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_two_level_adder_chain_out.ena" out_port="mac_out_two_level_adder_chain_out.dftout"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_two_level_adder_chain_out.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_comb_comb" in_port="mac_out.data_in[0]" out_port="mac_out_two_level_adder_chain_out.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_comb_comb" in_port="mac_out.data_in[0]" out_port="mac_out_two_level_adder_chain_out.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_two_level_adder_chain_out.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_comb_comb" in_port="mac_out.data_in[36]" out_port="mac_out_two_level_adder_chain_out.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_comb_comb" in_port="mac_out.data_in[36]" out_port="mac_out_two_level_adder_chain_out.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_two_level_adder_chain_out.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_comb_comb" in_port="mac_out.data_in[72]" out_port="mac_out_two_level_adder_chain_out.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_comb_comb" in_port="mac_out.data_in[72]" out_port="mac_out_two_level_adder_chain_out.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_two_level_adder_chain_out.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_comb_comb" in_port="mac_out.data_in[108]" out_port="mac_out_two_level_adder_chain_out.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_comb_comb" in_port="mac_out.data_in[108]" out_port="mac_out_two_level_adder_chain_out.datad[0]"/>
                  </direct>
                  <!-- Arithmetic chain input -->
                  <direct name="data_c5" input="mac_out.chain_in" output="mac_out_two_level_adder_chain_out.chainin"/>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_two_level_adder_chain_out.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_two_level_adder_chain_out.signb"/>
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_two_level_adder_chain_out.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_two_level_adder_chain_out.saturate"/>
                  <direct name="control_in_c_5" input="mac_out.control_in[5]" output="mac_out_two_level_adder_chain_out.roundchainout"/>
                  <direct name="control_in_c_6" input="mac_out.control_in[6]" output="mac_out_two_level_adder_chain_out.saturatechainout"/>
                  <direct name="control_in_c_7" input="mac_out.control_in[7]" output="mac_out_two_level_adder_chain_out.zerochainout"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_two_level_adder_chain_out.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_two_level_adder_chain_out.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_two_level_adder_chain_out.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_two_level_adder_chain_out.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 44 (dataa width + 8) in this mode -->
                  <direct name="out_c2" input="mac_out_two_level_adder_chain_out.dataout" output="mac_out.data_out[43:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_1" input="mac_out_two_level_adder_chain_out.overflow" output="mac_out.signal_out[0]"/>
                  <direct name="signal_2" input="mac_out_two_level_adder_chain_out.saturatechainoutoverflow" output="mac_out.signal_out[1]"/>
                  <direct name="signal_3" input="mac_out_two_level_adder_chain_out.dftout" output="mac_out.signal_out[2]"/>
                </interconnect>
              </mode>
              <!-- two_level_adder_chain_out -->
              <mode name="two_level_adder_chain_out.input_type{reg}.output_type{comb}">
                <pb_type name="mac_out_two_level_adder_chain_out" blif_model=".subckt stratixiv_mac_out.opmode{two_level_adder_chain_out}.input_type{reg}.output_type{comb}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="chainin" num_pins="44"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="roundchainout" num_pins="1"/>
                  <input name="saturatechainout" num_pins="1"/>
                  <input name="zerochainout" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="44"/>
                  <output name="overflow" num_pins="1"/>
                  <output name="saturatechainoutoverflow" num_pins="1"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has input registers with a combinational output.  

                       Measuring with QII in 'two level adder chain out mode' we arrived at the following values:
                          Input Register Setup Time (iTsu):              99ps
                          Input Register Hold Time (uTh):     	         48ps
					            The following maximum delays through setup analysis in QII:
                          Input Register Clock-to-Q Time (iTcq):         97ps
                          Input delay to the input registers (iTd):     213ps
                          Combinational Output delay to dataout (oTd): 1689ps
					            The following minimum delays through setup analysis in QII:
                          Input Register Clock-to-Q Time (iTcq):         97ps
                          Input delay to the input registers (iTd):      44ps
                          Combinational Output delay to dataout (oTd):  806ps
					   

                       This results in the following Tsu and Tcq times:
                          'data*' Tsu        : iTsu + iTd  =         312 ps
                          'data*' uTh        : uTh - iTd   =           4 ps
                          All other Tsu      : iTsu        =          99 ps
                          All other uTh      : uTh         =          48 ps
                          'data*' Tcq        : iTcq        =   max:   97 ps  |	min: 97 ps
                          'data*' comb delay : oTd         =   max: 1689 ps  | 	min: 806 ps
                          All other Tcq      : iTcq        =   max:   97 ps  |	min: 97 ps
                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.dataa" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.datab" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.datac" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.datad" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.chainin" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.round" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.saturate" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.roundchainout" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.saturatechainout" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.zerochainout" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.dataa" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.datab" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.datac" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.datad" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.chainin" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.round" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.saturate" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.roundchainout" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.saturatechainout" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.zerochainout" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.ena" value="48e-12"/>
                  <!-- Internal input timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder_chain_out.dataa" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder_chain_out.datab" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder_chain_out.datac" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder_chain_out.datad" max="97e-12" min="97e-12"/>
                  <!-- Output combinational delay -->
                  <delay_constant in_port="mac_out_two_level_adder_chain_out.dataa" out_port="mac_out_two_level_adder_chain_out.dataout" max="1689e-12" min="806e-12"/>
                  <delay_constant in_port="mac_out_two_level_adder_chain_out.datab" out_port="mac_out_two_level_adder_chain_out.dataout" max="1689e-12" min="806e-12"/>
                  <delay_constant in_port="mac_out_two_level_adder_chain_out.datac" out_port="mac_out_two_level_adder_chain_out.dataout" max="1689e-12" min="806e-12"/>
                  <delay_constant in_port="mac_out_two_level_adder_chain_out.datad" out_port="mac_out_two_level_adder_chain_out.dataout" max="1689e-12" min="806e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder_chain_out.overflow" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder_chain_out.saturatechainoutoverflow" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder_chain_out.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_two_level_adder_chain_out.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_reg_comb" in_port="mac_out.data_in[0]" out_port="mac_out_two_level_adder_chain_out.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_reg_comb" in_port="mac_out.data_in[0]" out_port="mac_out_two_level_adder_chain_out.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_two_level_adder_chain_out.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_reg_comb" in_port="mac_out.data_in[36]" out_port="mac_out_two_level_adder_chain_out.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_reg_comb" in_port="mac_out.data_in[36]" out_port="mac_out_two_level_adder_chain_out.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_two_level_adder_chain_out.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_reg_comb" in_port="mac_out.data_in[72]" out_port="mac_out_two_level_adder_chain_out.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_reg_comb" in_port="mac_out.data_in[72]" out_port="mac_out_two_level_adder_chain_out.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_two_level_adder_chain_out.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_reg_comb" in_port="mac_out.data_in[108]" out_port="mac_out_two_level_adder_chain_out.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_reg_comb" in_port="mac_out.data_in[108]" out_port="mac_out_two_level_adder_chain_out.datad[0]"/>
                  </direct>
                  <!-- Arithmetic chain input -->
                  <direct name="data_c5" input="mac_out.chain_in" output="mac_out_two_level_adder_chain_out.chainin"/>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_two_level_adder_chain_out.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_two_level_adder_chain_out.signb"/>
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_two_level_adder_chain_out.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_two_level_adder_chain_out.saturate"/>
                  <direct name="control_in_c_5" input="mac_out.control_in[5]" output="mac_out_two_level_adder_chain_out.roundchainout"/>
                  <direct name="control_in_c_6" input="mac_out.control_in[6]" output="mac_out_two_level_adder_chain_out.saturatechainout"/>
                  <direct name="control_in_c_7" input="mac_out.control_in[7]" output="mac_out_two_level_adder_chain_out.zerochainout"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_two_level_adder_chain_out.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_two_level_adder_chain_out.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_two_level_adder_chain_out.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_two_level_adder_chain_out.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 44 (dataa width + 8) in this mode -->
                  <direct name="out_c2" input="mac_out_two_level_adder_chain_out.dataout" output="mac_out.data_out[43:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_1" input="mac_out_two_level_adder_chain_out.overflow" output="mac_out.signal_out[0]"/>
                  <direct name="signal_2" input="mac_out_two_level_adder_chain_out.saturatechainoutoverflow" output="mac_out.signal_out[1]"/>
                  <direct name="signal_3" input="mac_out_two_level_adder_chain_out.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_two_level_adder_chain_out.clk"/>
                </interconnect>
              </mode>
              <!-- two_level_adder_chain_out -->
              <mode name="two_level_adder_chain_out.input_type{comb}.output_type{reg}">
                <pb_type name="mac_out_two_level_adder_chain_out" blif_model=".subckt stratixiv_mac_out.opmode{two_level_adder_chain_out}.input_type{comb}.output_type{reg}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="chainin" num_pins="44"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="roundchainout" num_pins="1"/>
                  <input name="saturatechainout" num_pins="1"/>
                  <input name="zerochainout" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="44"/>
                  <output name="overflow" num_pins="1"/>
                  <output name="saturatechainoutoverflow" num_pins="1"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has a combinational input with a registered out.  

                       Measuring with QII in 'two level adder chain out' mode we arrived at the following values:
                          Output Register Setup Time (oTsu):              99 ps
                          Output Register Hold Time (uTh):                48 ps
					   The following maximum values:
                          Output Register Clock-to-Q Time (oTcq):         97 ps
                          Combinational Output delay to dataout (oTd):   333 ps
                          Input delay to the output registers (iTd):    1227 ps
					   The following minimum values:
                          Output Register Clock-to-Q Time (oTcq):         97 ps
                          Combinational Output delay to dataout (oTd):   180 ps
                          Input delay to the output registers (iTd):     475 ps


                       This results in the following Tsu and Tcq times:
                          'data*' comb delay : iTd         =   max: 1227 ps	 |  min: 475 ps
                          'dataout' Tsu      : oTsu        = 		  99 ps   
                          'dataout' uTh      : uTh         =  		  48 ps   
                          'dataout' Tcq      : oTcq + oTd  =   max:  430 ps	 |  min: 277 ps
                          All others Tcq     : oTcq        =   max:   97 ps	 |  min:  97 ps
                          All others Tsu     : oTsu        = 		  99 ps
                          All others uTh     : uTh         = 		  48 ps
                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.chainin" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.round" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.saturate" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.roundchainout" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.saturatechainout" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.zerochainout" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.chainin" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.round" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.saturate" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.roundchainout" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.saturatechainout" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.zerochainout" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.ena" value="48e-12"/>
                  <!-- Input combinational delay -->
                  <!-- Output combinational delay -->
                  <delay_constant in_port="mac_out_two_level_adder_chain_out.dataa" out_port="mac_out_two_level_adder_chain_out.dataout" max="1227e-12" min="475e-12"/>
                  <delay_constant in_port="mac_out_two_level_adder_chain_out.datab" out_port="mac_out_two_level_adder_chain_out.dataout" max="1227e-12" min="475e-12"/>
                  <delay_constant in_port="mac_out_two_level_adder_chain_out.datac" out_port="mac_out_two_level_adder_chain_out.dataout" max="1227e-12" min="475e-12"/>
                  <delay_constant in_port="mac_out_two_level_adder_chain_out.datad" out_port="mac_out_two_level_adder_chain_out.dataout" max="1227e-12" min="475e-12"/>
                  <!-- Internal output timing -->
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.dataout" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.dataout" value="48e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder_chain_out.dataout" max="430e-12" min="277e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder_chain_out.overflow" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder_chain_out.saturatechainoutoverflow" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder_chain_out.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_two_level_adder_chain_out.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_comb_reg" in_port="mac_out.data_in[0]" out_port="mac_out_two_level_adder_chain_out.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_comb_reg" in_port="mac_out.data_in[0]" out_port="mac_out_two_level_adder_chain_out.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_two_level_adder_chain_out.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_comb_reg" in_port="mac_out.data_in[36]" out_port="mac_out_two_level_adder_chain_out.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_comb_reg" in_port="mac_out.data_in[36]" out_port="mac_out_two_level_adder_chain_out.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_two_level_adder_chain_out.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_comb_reg" in_port="mac_out.data_in[72]" out_port="mac_out_two_level_adder_chain_out.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_comb_reg" in_port="mac_out.data_in[72]" out_port="mac_out_two_level_adder_chain_out.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_two_level_adder_chain_out.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_comb_reg" in_port="mac_out.data_in[108]" out_port="mac_out_two_level_adder_chain_out.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_comb_reg" in_port="mac_out.data_in[108]" out_port="mac_out_two_level_adder_chain_out.datad[0]"/>
                  </direct>
                  <!-- Arithmetic chain input -->
                  <direct name="data_c5" input="mac_out.chain_in" output="mac_out_two_level_adder_chain_out.chainin"/>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_two_level_adder_chain_out.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_two_level_adder_chain_out.signb"/>
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_two_level_adder_chain_out.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_two_level_adder_chain_out.saturate"/>
                  <direct name="control_in_c_5" input="mac_out.control_in[5]" output="mac_out_two_level_adder_chain_out.roundchainout"/>
                  <direct name="control_in_c_6" input="mac_out.control_in[6]" output="mac_out_two_level_adder_chain_out.saturatechainout"/>
                  <direct name="control_in_c_7" input="mac_out.control_in[7]" output="mac_out_two_level_adder_chain_out.zerochainout"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_two_level_adder_chain_out.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_two_level_adder_chain_out.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_two_level_adder_chain_out.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_two_level_adder_chain_out.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 44 (dataa width + 8) in this mode -->
                  <direct name="out_c2" input="mac_out_two_level_adder_chain_out.dataout" output="mac_out.data_out[43:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_1" input="mac_out_two_level_adder_chain_out.overflow" output="mac_out.signal_out[0]"/>
                  <direct name="signal_2" input="mac_out_two_level_adder_chain_out.saturatechainoutoverflow" output="mac_out.signal_out[1]"/>
                  <direct name="signal_3" input="mac_out_two_level_adder_chain_out.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_two_level_adder_chain_out.clk"/>
                </interconnect>
              </mode>
              <!-- two_level_adder_chain_out -->
              <mode name="two_level_adder_chain_out.input_type{reg}.output_type{reg}">
                <pb_type name="mac_out_two_level_adder_chain_out" blif_model=".subckt stratixiv_mac_out.opmode{two_level_adder_chain_out}.input_type{reg}.output_type{reg}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="chainin" num_pins="44"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="roundchainout" num_pins="1"/>
                  <input name="saturatechainout" num_pins="1"/>
                  <input name="zerochainout" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="44"/>
                  <output name="overflow" num_pins="1"/>
                  <output name="saturatechainoutoverflow" num_pins="1"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has a registered input and a registered out.  
                       We model the combinational input delay as part of the setup time, and
                       the combinational output delay as part of the clock to q time.

                       Note that there may or may not actually have been additional pipelining
                       inside the DSP block, so in this case we are not cycle accurate to Stratix IV.
                       Since Stratix IV DSP blocks are practically limited to an speed of 510MHz,
                       we create an internal combinational path which models ths limit.

                       Measuring with QII in 'two level adder chain out' we arrived at the following values:
                          Input/Output Register Setup Time (iTsu/oTsu):      99ps
                          Input/Output Register Hold Time (uTh):			 48ps
                       We arrived at the following maximum values using QII:
                          Input/Output Register Clock-to-Q Time (iTcq/oTcq): 97ps
                          Combinational Output delay to dataout (oTd):      333ps
                          Input delay to the input registers (iTd):         213ps
                       Also the following minimum values using QII:
                          Input/Output Register Clock-to-Q Time (iTcq/oTcq): 97ps
                          Combinational Output delay to dataout (oTd):      180ps
                          Input delay to the input registers (iTd):          44ps
                          Minimum comb delay:                              456 ps

                       This results in the following Tsu, uTh, and Tcq times:
                          'data*' Tsu        : iTsu + iTd  = 	   312ps
                          'data*' uTh        : uTh - iTd   = 	     4ps 
                          'dataout' Tcq      : oTcq + oTd  =  max: 430ps  |  min: 277ps
                          All others Tcq     : oTcq        =  max:  97ps  |  min: 97ps
                          All others Tsu     : iTsu        = 		99ps
                          All others uTh     : uTh         = 		48ps

                          Internal Tsu: iTsu               =        99ps
                          Internal uTh:  uTh               =        48ps
                          Internal Tcq: iTcq               =        97ps

                          Maximum comb delay  : (1 / 510MHz) - iTsu - iTcq = 1765ps

                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.dataa" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.datab" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.datac" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.datad" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.chainin" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.round" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.saturate" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.roundchainout" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.saturatechainout" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.zerochainout" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.dataa" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.datab" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.datac" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.datad" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.chainin" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.round" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.saturate" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.roundchainout" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.saturatechainout" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.zerochainout" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.ena" value="48e-12"/>
                  <!-- Internal input timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder_chain_out.dataa" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder_chain_out.datab" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder_chain_out.datac" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder_chain_out.datad" max="97e-12" min="97e-12"/>
                  <!-- Internal combinational delay -->
                  <delay_constant in_port="mac_out_two_level_adder_chain_out.dataa" out_port="mac_out_two_level_adder_chain_out.dataout" max="1765e-12" min="456e-12"/>
                  <delay_constant in_port="mac_out_two_level_adder_chain_out.datab" out_port="mac_out_two_level_adder_chain_out.dataout" max="1765e-12" min="456e-12"/>
                  <delay_constant in_port="mac_out_two_level_adder_chain_out.datac" out_port="mac_out_two_level_adder_chain_out.dataout" max="1765e-12" min="456e-12"/>
                  <delay_constant in_port="mac_out_two_level_adder_chain_out.datad" out_port="mac_out_two_level_adder_chain_out.dataout" max="1765e-12" min="456e-12"/>
                  <!-- Internal output timing -->
                  <T_setup clock="clk" port="mac_out_two_level_adder_chain_out.dataout" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_two_level_adder_chain_out.dataout" value="48e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder_chain_out.dataout" max="430e-12" min="277e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder_chain_out.overflow" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder_chain_out.saturatechainoutoverflow" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_two_level_adder_chain_out.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_two_level_adder_chain_out.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_reg_reg" in_port="mac_out.data_in[0]" out_port="mac_out_two_level_adder_chain_out.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_reg_reg" in_port="mac_out.data_in[0]" out_port="mac_out_two_level_adder_chain_out.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_two_level_adder_chain_out.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_reg_reg" in_port="mac_out.data_in[36]" out_port="mac_out_two_level_adder_chain_out.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_reg_reg" in_port="mac_out.data_in[36]" out_port="mac_out_two_level_adder_chain_out.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_two_level_adder_chain_out.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_reg_reg" in_port="mac_out.data_in[72]" out_port="mac_out_two_level_adder_chain_out.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_reg_reg" in_port="mac_out.data_in[72]" out_port="mac_out_two_level_adder_chain_out.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_two_level_adder_chain_out.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_reg_reg" in_port="mac_out.data_in[108]" out_port="mac_out_two_level_adder_chain_out.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_reg_reg" in_port="mac_out.data_in[108]" out_port="mac_out_two_level_adder_chain_out.datad[0]"/>
                  </direct>
                  <!-- Arithmetic chain input -->
                  <direct name="data_c5" input="mac_out.chain_in" output="mac_out_two_level_adder_chain_out.chainin"/>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_two_level_adder_chain_out.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_two_level_adder_chain_out.signb"/>
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_two_level_adder_chain_out.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_two_level_adder_chain_out.saturate"/>
                  <direct name="control_in_c_5" input="mac_out.control_in[5]" output="mac_out_two_level_adder_chain_out.roundchainout"/>
                  <direct name="control_in_c_6" input="mac_out.control_in[6]" output="mac_out_two_level_adder_chain_out.saturatechainout"/>
                  <direct name="control_in_c_7" input="mac_out.control_in[7]" output="mac_out_two_level_adder_chain_out.zerochainout"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_two_level_adder_chain_out.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_two_level_adder_chain_out.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_two_level_adder_chain_out.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_two_level_adder_chain_out.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 44 (dataa width + 8) in this mode -->
                  <direct name="out_c2" input="mac_out_two_level_adder_chain_out.dataout" output="mac_out.data_out[43:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_1" input="mac_out_two_level_adder_chain_out.overflow" output="mac_out.signal_out[0]"/>
                  <direct name="signal_2" input="mac_out_two_level_adder_chain_out.saturatechainoutoverflow" output="mac_out.signal_out[1]"/>
                  <direct name="signal_3" input="mac_out_two_level_adder_chain_out.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_two_level_adder_chain_out.clk"/>
                </interconnect>
              </mode>
              <!-- two_level_adder_chain_out -->
              <mode name="accumulator.input_type{comb}.output_type{comb}">
                <pb_type name="mac_out_accumulator" blif_model=".subckt stratixiv_mac_out.opmode{accumulator}.input_type{comb}.output_type{comb}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="zeroacc" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <output name="dataout" num_pins="44"/>
                  <output name="overflow" num_pins="1"/>
                  <output name="dftout" num_pins="1"/>
                  <!-- 
                       In this mode the block is purely combinational. We model only the main data path, but add 
                       zero delay edges to other possible timing paths through the block.  It is very unlikely 
                       that the non-datapath signals would every end up on the critical path.

                       Maximum delay through the mac_out in this mode is 1765ps, and minimum delay is 763ps,
					   as measured using the 'two level chain out' mode in QII.
                       -->
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_accumulator.dataa" out_port="mac_out_accumulator.dataout"/>
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_accumulator.datab" out_port="mac_out_accumulator.dataout"/>
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_accumulator.datac" out_port="mac_out_accumulator.dataout"/>
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_accumulator.datad" out_port="mac_out_accumulator.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.signa" out_port="mac_out_accumulator.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.signb" out_port="mac_out_accumulator.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.round" out_port="mac_out_accumulator.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.saturate" out_port="mac_out_accumulator.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.zeroacc" out_port="mac_out_accumulator.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.devclrn" out_port="mac_out_accumulator.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.devpor" out_port="mac_out_accumulator.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.aclr" out_port="mac_out_accumulator.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.ena" out_port="mac_out_accumulator.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.dataa" out_port="mac_out_accumulator.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.datab" out_port="mac_out_accumulator.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.datac" out_port="mac_out_accumulator.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.datad" out_port="mac_out_accumulator.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.signa" out_port="mac_out_accumulator.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.signb" out_port="mac_out_accumulator.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.round" out_port="mac_out_accumulator.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.saturate" out_port="mac_out_accumulator.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.zeroacc" out_port="mac_out_accumulator.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.devclrn" out_port="mac_out_accumulator.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.devpor" out_port="mac_out_accumulator.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.ena" out_port="mac_out_accumulator.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.dataa" out_port="mac_out_accumulator.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.datab" out_port="mac_out_accumulator.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.datac" out_port="mac_out_accumulator.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.datad" out_port="mac_out_accumulator.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.signa" out_port="mac_out_accumulator.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.signb" out_port="mac_out_accumulator.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.round" out_port="mac_out_accumulator.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.saturate" out_port="mac_out_accumulator.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.zeroacc" out_port="mac_out_accumulator.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.devclrn" out_port="mac_out_accumulator.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.devpor" out_port="mac_out_accumulator.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator.ena" out_port="mac_out_accumulator.overflow"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_accumulator.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_comb_comb" in_port="mac_out.data_in[0]" out_port="mac_out_accumulator.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_comb_comb" in_port="mac_out.data_in[0]" out_port="mac_out_accumulator.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_accumulator.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_comb_comb" in_port="mac_out.data_in[36]" out_port="mac_out_accumulator.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_comb_comb" in_port="mac_out.data_in[36]" out_port="mac_out_accumulator.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_accumulator.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_comb_comb" in_port="mac_out.data_in[72]" out_port="mac_out_accumulator.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_comb_comb" in_port="mac_out.data_in[72]" out_port="mac_out_accumulator.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_accumulator.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_comb_comb" in_port="mac_out.data_in[108]" out_port="mac_out_accumulator.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_comb_comb" in_port="mac_out.data_in[108]" out_port="mac_out_accumulator.datad[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_accumulator.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_accumulator.signb"/>
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_accumulator.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_accumulator.saturate"/>
                  <direct name="control_in_c_4" input="mac_out.control_in[4]" output="mac_out_accumulator.zeroacc"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_accumulator.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_accumulator.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_accumulator.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_accumulator.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 44 (dataa width + 8) in this mode -->
                  <direct name="out_c2" input="mac_out_accumulator.dataout" output="mac_out.data_out[43:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_1" input="mac_out_accumulator.overflow" output="mac_out.signal_out[0]"/>
                  <direct name="signal_3" input="mac_out_accumulator.dftout" output="mac_out.signal_out[2]"/>
                </interconnect>
              </mode>
              <!-- accumulator-->
              <mode name="accumulator.input_type{reg}.output_type{comb}">
                <pb_type name="mac_out_accumulator" blif_model=".subckt stratixiv_mac_out.opmode{accumulator}.input_type{reg}.output_type{comb}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="zeroacc" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="44"/>
                  <output name="overflow" num_pins="1"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has input registers with a combinational output.  

                       Measuring with QII in 'two level adder chain out mode' we arrived at the following values:
                          Input Register Setup Time (iTsu):              99ps
                          Input Register Hold Time (uTh):     	         48ps
					            The following maximum delays through setup analysis in QII:
                          Input Register Clock-to-Q Time (iTcq):         97ps
                          Input delay to the input registers (iTd):     213ps
                          Combinational Output delay to dataout (oTd): 1689ps
					            The following minimum delays through setup analysis in QII:
                          Input Register Clock-to-Q Time (iTcq):         97ps
                          Input delay to the input registers (iTd):      44ps
                          Combinational Output delay to dataout (oTd):  806ps
					   

                       This results in the following Tsu and Tcq times:
                          'data*' Tsu        : iTsu + iTd  =         312 ps
                          'data*' uTh        : uTh - iTd   =           4 ps
                          All other Tsu      : iTsu        =          99 ps
                          All other uTh      : uTh         =          48 ps
                          'data*' Tcq        : iTcq        =   max:   97 ps  |	min: 97 ps
                          'data*' comb delay : oTd         =   max: 1689 ps  | 	min: 806 ps
                          All other Tcq      : iTcq        =   max:   97 ps  |	min: 97 ps
                       -->
                  <T_setup clock="clk" port="mac_out_accumulator.dataa" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.datab" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.datac" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.datad" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.round" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.saturate" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.zeroacc" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_accumulator.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.dataa" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.datab" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.datac" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.datad" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.round" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.saturate" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.zeroacc" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_accumulator.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.ena" value="48e-12"/>
                  <!-- Internal input timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator.dataa" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator.datab" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator.datac" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator.datad" max="97e-12" min="97e-12"/>
                  <!-- Output combinational delay -->
                  <delay_constant in_port="mac_out_accumulator.dataa" out_port="mac_out_accumulator.dataout" max="1689e-12" min="806e-12"/>
                  <delay_constant in_port="mac_out_accumulator.datab" out_port="mac_out_accumulator.dataout" max="1689e-12" min="806e-12"/>
                  <delay_constant in_port="mac_out_accumulator.datac" out_port="mac_out_accumulator.dataout" max="1689e-12" min="806e-12"/>
                  <delay_constant in_port="mac_out_accumulator.datad" out_port="mac_out_accumulator.dataout" max="1689e-12" min="806e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator.overflow" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_accumulator.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_reg_comb" in_port="mac_out.data_in[0]" out_port="mac_out_accumulator.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_reg_comb" in_port="mac_out.data_in[0]" out_port="mac_out_accumulator.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_accumulator.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_reg_comb" in_port="mac_out.data_in[36]" out_port="mac_out_accumulator.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_reg_comb" in_port="mac_out.data_in[36]" out_port="mac_out_accumulator.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_accumulator.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_reg_comb" in_port="mac_out.data_in[72]" out_port="mac_out_accumulator.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_reg_comb" in_port="mac_out.data_in[72]" out_port="mac_out_accumulator.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_accumulator.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_reg_comb" in_port="mac_out.data_in[108]" out_port="mac_out_accumulator.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_reg_comb" in_port="mac_out.data_in[108]" out_port="mac_out_accumulator.datad[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_accumulator.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_accumulator.signb"/>
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_accumulator.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_accumulator.saturate"/>
                  <direct name="control_in_c_4" input="mac_out.control_in[4]" output="mac_out_accumulator.zeroacc"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_accumulator.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_accumulator.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_accumulator.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_accumulator.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 44 (dataa width + 8) in this mode -->
                  <direct name="out_c2" input="mac_out_accumulator.dataout" output="mac_out.data_out[43:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_1" input="mac_out_accumulator.overflow" output="mac_out.signal_out[0]"/>
                  <direct name="signal_3" input="mac_out_accumulator.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_accumulator.clk"/>
                </interconnect>
              </mode>
              <!-- accumulator-->
              <mode name="accumulator.input_type{comb}.output_type{reg}">
                <pb_type name="mac_out_accumulator" blif_model=".subckt stratixiv_mac_out.opmode{accumulator}.input_type{comb}.output_type{reg}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="zeroacc" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="44"/>
                  <output name="overflow" num_pins="1"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has a combinational input with a registered out.  

                       Measuring with QII in 'two level adder chain out' mode we arrived at the following values:
                          Output Register Setup Time (oTsu):              99 ps
                          Output Register Hold Time (uTh):                48 ps
					   The following maximum values:
                          Output Register Clock-to-Q Time (oTcq):         97 ps
                          Combinational Output delay to dataout (oTd):   333 ps
                          Input delay to the output registers (iTd):    1227 ps
					   The following minimum values:
                          Output Register Clock-to-Q Time (oTcq):         97 ps
                          Combinational Output delay to dataout (oTd):   180 ps
                          Input delay to the output registers (iTd):     475 ps


                       This results in the following Tsu and Tcq times:
                          'data*' comb delay : iTd         =   max: 1227 ps	 |  min: 475 ps
                          'dataout' Tsu      : oTsu        = 		  99 ps   
                          'dataout' uTh      : uTh         =  		  48 ps   
                          'dataout' Tcq      : oTcq + oTd  =   max:  430 ps	 |  min: 277 ps
                          All others Tcq     : oTcq        =   max:   97 ps	 |  min:  97 ps
                          All others Tsu     : oTsu        = 		  99 ps
                          All others uTh     : uTh         = 		  48 ps
                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_accumulator.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.round" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.saturate" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.zeroacc" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_accumulator.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.round" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.saturate" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.zeroacc" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_accumulator.ena" value="48e-12"/>
                  <!-- Input combinational delay -->
                  <delay_constant in_port="mac_out_accumulator.dataa" out_port="mac_out_accumulator.dataout" max="1227e-12" min="475e-12"/>
                  <delay_constant in_port="mac_out_accumulator.datab" out_port="mac_out_accumulator.dataout" max="1227e-12" min="475e-12"/>
                  <delay_constant in_port="mac_out_accumulator.datac" out_port="mac_out_accumulator.dataout" max="1227e-12" min="475e-12"/>
                  <delay_constant in_port="mac_out_accumulator.datad" out_port="mac_out_accumulator.dataout" max="1227e-12" min="475e-12"/>
                  <!-- Internal output timing -->
                  <T_setup clock="clk" port="mac_out_accumulator.dataout" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.dataout" value="48e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator.dataout" max="430e-12" min="277e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator.overflow" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_accumulator.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_comb_reg" in_port="mac_out.data_in[0]" out_port="mac_out_accumulator.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_comb_reg" in_port="mac_out.data_in[0]" out_port="mac_out_accumulator.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_accumulator.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_comb_reg" in_port="mac_out.data_in[36]" out_port="mac_out_accumulator.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_comb_reg" in_port="mac_out.data_in[36]" out_port="mac_out_accumulator.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_accumulator.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_comb_reg" in_port="mac_out.data_in[72]" out_port="mac_out_accumulator.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_comb_reg" in_port="mac_out.data_in[72]" out_port="mac_out_accumulator.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_accumulator.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_comb_reg" in_port="mac_out.data_in[108]" out_port="mac_out_accumulator.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_comb_reg" in_port="mac_out.data_in[108]" out_port="mac_out_accumulator.datad[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_accumulator.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_accumulator.signb"/>
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_accumulator.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_accumulator.saturate"/>
                  <direct name="control_in_c_4" input="mac_out.control_in[4]" output="mac_out_accumulator.zeroacc"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_accumulator.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_accumulator.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_accumulator.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_accumulator.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 44 (dataa width + 8) in this mode -->
                  <direct name="out_c2" input="mac_out_accumulator.dataout" output="mac_out.data_out[43:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_1" input="mac_out_accumulator.overflow" output="mac_out.signal_out[0]"/>
                  <direct name="signal_3" input="mac_out_accumulator.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_accumulator.clk"/>
                </interconnect>
              </mode>
              <!-- accumulator-->
              <mode name="accumulator.input_type{reg}.output_type{reg}">
                <pb_type name="mac_out_accumulator" blif_model=".subckt stratixiv_mac_out.opmode{accumulator}.input_type{reg}.output_type{reg}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="zeroacc" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="44"/>
                  <output name="overflow" num_pins="1"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has a registered input and a registered out.  
                       We model the combinational input delay as part of the setup time, and
                       the combinational output delay as part of the clock to q time.

                       Note that there may or may not actually have been additional pipelining
                       inside the DSP block, so in this case we are not cycle accurate to Stratix IV.
                       Since Stratix IV DSP blocks are practically limited to an speed of 510MHz,
                       we create an internal combinational path which models ths limit.

                       Measuring with QII in 'two level adder chain out' we arrived at the following values:
                          Input/Output Register Setup Time (iTsu/oTsu):      99ps
                          Input/Output Register Hold Time (uTh):			 48ps
                       We arrived at the following maximum values using QII:
                          Input/Output Register Clock-to-Q Time (iTcq/oTcq): 97ps
                          Combinational Output delay to dataout (oTd):      333ps
                          Input delay to the input registers (iTd):         213ps
                       Also the following minimum values using QII:
                          Input/Output Register Clock-to-Q Time (iTcq/oTcq): 97ps
                          Combinational Output delay to dataout (oTd):      180ps
                          Input delay to the input registers (iTd):          44ps
                          Minimum comb delay:                              456 ps

                       This results in the following Tsu, uTh, and Tcq times:
                          'data*' Tsu        : iTsu + iTd  = 	   312ps
                          'data*' uTh        : uTh - iTd   = 	     4ps 
                          'dataout' Tcq      : oTcq + oTd  =  max: 430ps  |  min: 277ps
                          All others Tcq     : oTcq        =  max:  97ps  |  min: 97ps
                          All others Tsu     : iTsu        = 		99ps
                          All others uTh     : uTh         = 		48ps

                          Internal Tsu: iTsu               =        99ps
                          Internal uTh:  uTh               =        48ps
                          Internal Tcq: iTcq               =        97ps

                          Maximum comb delay  : (1 / 510MHz) - iTsu - iTcq = 1765ps

                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_accumulator.dataa" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.datab" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.datac" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.datad" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.round" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.saturate" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.zeroacc" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_accumulator.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.dataa" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.datab" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.datac" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.datad" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.round" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.saturate" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.zeroacc" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_accumulator.ena" value="48e-12"/>
                  <!-- Internal input timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator.dataa" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator.datab" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator.datac" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator.datad" max="97e-12" min="97e-12"/>
                  <!-- Internal combinational delay -->
                  <delay_constant in_port="mac_out_accumulator.dataa" out_port="mac_out_accumulator.dataout" max="1765e-12" min="456e-12"/>
                  <delay_constant in_port="mac_out_accumulator.datab" out_port="mac_out_accumulator.dataout" max="1765e-12" min="456e-12"/>
                  <delay_constant in_port="mac_out_accumulator.datac" out_port="mac_out_accumulator.dataout" max="1765e-12" min="456e-12"/>
                  <delay_constant in_port="mac_out_accumulator.datad" out_port="mac_out_accumulator.dataout" max="1765e-12" min="456e-12"/>
                  <!-- Internal output timing -->
                  <T_setup clock="clk" port="mac_out_accumulator.dataout" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator.dataout" value="48e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator.dataout" max="430e-12" min="277e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator.overflow" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_accumulator.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_reg_reg" in_port="mac_out.data_in[0]" out_port="mac_out_accumulator.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_reg_reg" in_port="mac_out.data_in[0]" out_port="mac_out_accumulator.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_accumulator.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_reg_reg" in_port="mac_out.data_in[36]" out_port="mac_out_accumulator.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_reg_reg" in_port="mac_out.data_in[36]" out_port="mac_out_accumulator.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_accumulator.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_reg_reg" in_port="mac_out.data_in[72]" out_port="mac_out_accumulator.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_reg_reg" in_port="mac_out.data_in[72]" out_port="mac_out_accumulator.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_accumulator.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_reg_reg" in_port="mac_out.data_in[108]" out_port="mac_out_accumulator.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_reg_reg" in_port="mac_out.data_in[108]" out_port="mac_out_accumulator.datad[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_accumulator.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_accumulator.signb"/>
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_accumulator.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_accumulator.saturate"/>
                  <direct name="control_in_c_4" input="mac_out.control_in[4]" output="mac_out_accumulator.zeroacc"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_accumulator.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_accumulator.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_accumulator.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_accumulator.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 44 (dataa width + 8) in this mode -->
                  <direct name="out_c2" input="mac_out_accumulator.dataout" output="mac_out.data_out[43:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_1" input="mac_out_accumulator.overflow" output="mac_out.signal_out[0]"/>
                  <direct name="signal_3" input="mac_out_accumulator.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_accumulator.clk"/>
                </interconnect>
              </mode>
              <!-- accumulator-->
              <mode name="accumulator_chain_out.input_type{comb}.output_type{comb}">
                <pb_type name="mac_out_accumulator_chain_out" blif_model=".subckt stratixiv_mac_out.opmode{accumulator_chain_out}.input_type{comb}.output_type{comb}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="chainin" num_pins="44"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="zeroacc" num_pins="1"/>
                  <input name="roundchainout" num_pins="1"/>
                  <input name="saturatechainout" num_pins="1"/>
                  <input name="zerochainout" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <output name="dataout" num_pins="44"/>
                  <output name="overflow" num_pins="1"/>
                  <output name="saturatechainoutoverflow" num_pins="1"/>
                  <output name="dftout" num_pins="1"/>
                  <!-- 
                       In this mode the block is purely combinational. We model only the main data path, but add 
                       zero delay edges to other possible timing paths through the block.  It is very unlikely 
                       that the non-datapath signals would every end up on the critical path.

                       Maximum delay through the mac_out in this mode is 1765ps, and minimum delay is 763ps,
					   as measured using the 'two level chain out' mode in QII.
                       -->
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_accumulator_chain_out.dataa" out_port="mac_out_accumulator_chain_out.dataout"/>
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_accumulator_chain_out.datab" out_port="mac_out_accumulator_chain_out.dataout"/>
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_accumulator_chain_out.datac" out_port="mac_out_accumulator_chain_out.dataout"/>
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_accumulator_chain_out.datad" out_port="mac_out_accumulator_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.chainin" out_port="mac_out_accumulator_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.signa" out_port="mac_out_accumulator_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.signb" out_port="mac_out_accumulator_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.round" out_port="mac_out_accumulator_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.saturate" out_port="mac_out_accumulator_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.zeroacc" out_port="mac_out_accumulator_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.roundchainout" out_port="mac_out_accumulator_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.saturatechainout" out_port="mac_out_accumulator_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.zerochainout" out_port="mac_out_accumulator_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.devclrn" out_port="mac_out_accumulator_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.devpor" out_port="mac_out_accumulator_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.aclr" out_port="mac_out_accumulator_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.ena" out_port="mac_out_accumulator_chain_out.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.dataa" out_port="mac_out_accumulator_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.datab" out_port="mac_out_accumulator_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.datac" out_port="mac_out_accumulator_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.datad" out_port="mac_out_accumulator_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.chainin" out_port="mac_out_accumulator_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.signa" out_port="mac_out_accumulator_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.signb" out_port="mac_out_accumulator_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.round" out_port="mac_out_accumulator_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.saturate" out_port="mac_out_accumulator_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.zeroacc" out_port="mac_out_accumulator_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.roundchainout" out_port="mac_out_accumulator_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.saturatechainout" out_port="mac_out_accumulator_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.zerochainout" out_port="mac_out_accumulator_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.devclrn" out_port="mac_out_accumulator_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.devpor" out_port="mac_out_accumulator_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.ena" out_port="mac_out_accumulator_chain_out.overflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.dataa" out_port="mac_out_accumulator_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.datab" out_port="mac_out_accumulator_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.datac" out_port="mac_out_accumulator_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.datad" out_port="mac_out_accumulator_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.chainin" out_port="mac_out_accumulator_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.signa" out_port="mac_out_accumulator_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.signb" out_port="mac_out_accumulator_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.round" out_port="mac_out_accumulator_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.saturate" out_port="mac_out_accumulator_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.zeroacc" out_port="mac_out_accumulator_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.roundchainout" out_port="mac_out_accumulator_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.saturatechainout" out_port="mac_out_accumulator_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.zerochainout" out_port="mac_out_accumulator_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.devclrn" out_port="mac_out_accumulator_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.devpor" out_port="mac_out_accumulator_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.ena" out_port="mac_out_accumulator_chain_out.saturatechainoutoverflow"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.dataa" out_port="mac_out_accumulator_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.datab" out_port="mac_out_accumulator_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.datac" out_port="mac_out_accumulator_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.datad" out_port="mac_out_accumulator_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.chainin" out_port="mac_out_accumulator_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.signa" out_port="mac_out_accumulator_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.signb" out_port="mac_out_accumulator_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.round" out_port="mac_out_accumulator_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.saturate" out_port="mac_out_accumulator_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.zeroacc" out_port="mac_out_accumulator_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.roundchainout" out_port="mac_out_accumulator_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.saturatechainout" out_port="mac_out_accumulator_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.zerochainout" out_port="mac_out_accumulator_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.devclrn" out_port="mac_out_accumulator_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.devpor" out_port="mac_out_accumulator_chain_out.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_accumulator_chain_out.ena" out_port="mac_out_accumulator_chain_out.dftout"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_accumulator_chain_out.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_comb_comb" in_port="mac_out.data_in[0]" out_port="mac_out_accumulator_chain_out.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_comb_comb" in_port="mac_out.data_in[0]" out_port="mac_out_accumulator_chain_out.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_accumulator_chain_out.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_comb_comb" in_port="mac_out.data_in[36]" out_port="mac_out_accumulator_chain_out.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_comb_comb" in_port="mac_out.data_in[36]" out_port="mac_out_accumulator_chain_out.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_accumulator_chain_out.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_comb_comb" in_port="mac_out.data_in[72]" out_port="mac_out_accumulator_chain_out.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_comb_comb" in_port="mac_out.data_in[72]" out_port="mac_out_accumulator_chain_out.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_accumulator_chain_out.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_comb_comb" in_port="mac_out.data_in[108]" out_port="mac_out_accumulator_chain_out.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_comb_comb" in_port="mac_out.data_in[108]" out_port="mac_out_accumulator_chain_out.datad[0]"/>
                  </direct>
                  <!-- Arithmetic chain input -->
                  <direct name="data_c5" input="mac_out.chain_in" output="mac_out_accumulator_chain_out.chainin"/>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_accumulator_chain_out.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_accumulator_chain_out.signb"/>
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_accumulator_chain_out.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_accumulator_chain_out.saturate"/>
                  <direct name="control_in_c_4" input="mac_out.control_in[4]" output="mac_out_accumulator_chain_out.zeroacc"/>
                  <direct name="control_in_c_5" input="mac_out.control_in[5]" output="mac_out_accumulator_chain_out.roundchainout"/>
                  <direct name="control_in_c_6" input="mac_out.control_in[6]" output="mac_out_accumulator_chain_out.saturatechainout"/>
                  <direct name="control_in_c_7" input="mac_out.control_in[7]" output="mac_out_accumulator_chain_out.zerochainout"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_accumulator_chain_out.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_accumulator_chain_out.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_accumulator_chain_out.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_accumulator_chain_out.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 44 (dataa width + 8) in this mode -->
                  <direct name="out_c2" input="mac_out_accumulator_chain_out.dataout" output="mac_out.data_out[43:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_1" input="mac_out_accumulator_chain_out.overflow" output="mac_out.signal_out[0]"/>
                  <direct name="signal_2" input="mac_out_accumulator_chain_out.saturatechainoutoverflow" output="mac_out.signal_out[1]"/>
                  <direct name="signal_3" input="mac_out_accumulator_chain_out.dftout" output="mac_out.signal_out[2]"/>
                </interconnect>
              </mode>
              <!-- accumulator_chain_out -->
              <mode name="accumulator_chain_out.input_type{reg}.output_type{comb}">
                <pb_type name="mac_out_accumulator_chain_out" blif_model=".subckt stratixiv_mac_out.opmode{accumulator_chain_out}.input_type{reg}.output_type{comb}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="chainin" num_pins="44"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="zeroacc" num_pins="1"/>
                  <input name="roundchainout" num_pins="1"/>
                  <input name="saturatechainout" num_pins="1"/>
                  <input name="zerochainout" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="44"/>
                  <output name="overflow" num_pins="1"/>
                  <output name="saturatechainoutoverflow" num_pins="1"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has input registers with a combinational output.  

                       Measuring with QII in 'two level adder chain out mode' we arrived at the following values:
                          Input Register Setup Time (iTsu):              99ps
                          Input Register Hold Time (uTh):     	         48ps
					            The following maximum delays through setup analysis in QII:
                          Input Register Clock-to-Q Time (iTcq):         97ps
                          Input delay to the input registers (iTd):     213ps
                          Combinational Output delay to dataout (oTd): 1689ps
					            The following minimum delays through setup analysis in QII:
                          Input Register Clock-to-Q Time (iTcq):         97ps
                          Input delay to the input registers (iTd):      44ps
                          Combinational Output delay to dataout (oTd):  806ps
					   

                       This results in the following Tsu and Tcq times:
                          'data*' Tsu        : iTsu + iTd  =         312 ps
                          'data*' uTh        : uTh - iTd   =           4 ps
                          All other Tsu      : iTsu        =          99 ps
                          All other uTh      : uTh         =          48 ps
                          'data*' Tcq        : iTcq        =   max:   97 ps  |	min: 97 ps
                          'data*' comb delay : oTd         =   max: 1689 ps  | 	min: 806 ps
                          All other Tcq      : iTcq        =   max:   97 ps  |	min: 97 ps
                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.dataa" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.datab" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.datac" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.datad" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.chainin" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.round" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.saturate" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.zeroacc" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.roundchainout" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.saturatechainout" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.zerochainout" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.dataa" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.datab" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.datac" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.datad" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.chainin" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.round" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.saturate" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.zeroacc" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.roundchainout" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.saturatechainout" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.zerochainout" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.ena" value="48e-12"/>
                  <!-- Internal input timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator_chain_out.dataa" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator_chain_out.datab" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator_chain_out.datac" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator_chain_out.datad" max="97e-12" min="97e-12"/>
                  <!-- Output combinational delay -->
                  <delay_constant in_port="mac_out_accumulator_chain_out.dataa" out_port="mac_out_accumulator_chain_out.dataout" max="1689e-12" min="806e-12"/>
                  <delay_constant in_port="mac_out_accumulator_chain_out.datab" out_port="mac_out_accumulator_chain_out.dataout" max="1689e-12" min="806e-12"/>
                  <delay_constant in_port="mac_out_accumulator_chain_out.datac" out_port="mac_out_accumulator_chain_out.dataout" max="1689e-12" min="806e-12"/>
                  <delay_constant in_port="mac_out_accumulator_chain_out.datad" out_port="mac_out_accumulator_chain_out.dataout" max="1689e-12" min="806e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator_chain_out.overflow" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator_chain_out.saturatechainoutoverflow" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator_chain_out.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_accumulator_chain_out.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_reg_comb" in_port="mac_out.data_in[0]" out_port="mac_out_accumulator_chain_out.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_reg_comb" in_port="mac_out.data_in[0]" out_port="mac_out_accumulator_chain_out.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_accumulator_chain_out.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_reg_comb" in_port="mac_out.data_in[36]" out_port="mac_out_accumulator_chain_out.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_reg_comb" in_port="mac_out.data_in[36]" out_port="mac_out_accumulator_chain_out.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_accumulator_chain_out.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_reg_comb" in_port="mac_out.data_in[72]" out_port="mac_out_accumulator_chain_out.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_reg_comb" in_port="mac_out.data_in[72]" out_port="mac_out_accumulator_chain_out.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_accumulator_chain_out.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_reg_comb" in_port="mac_out.data_in[108]" out_port="mac_out_accumulator_chain_out.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_reg_comb" in_port="mac_out.data_in[108]" out_port="mac_out_accumulator_chain_out.datad[0]"/>
                  </direct>
                  <!-- Arithmetic chain input -->
                  <direct name="data_c5" input="mac_out.chain_in" output="mac_out_accumulator_chain_out.chainin"/>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_accumulator_chain_out.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_accumulator_chain_out.signb"/>
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_accumulator_chain_out.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_accumulator_chain_out.saturate"/>
                  <direct name="control_in_c_4" input="mac_out.control_in[4]" output="mac_out_accumulator_chain_out.zeroacc"/>
                  <direct name="control_in_c_5" input="mac_out.control_in[5]" output="mac_out_accumulator_chain_out.roundchainout"/>
                  <direct name="control_in_c_6" input="mac_out.control_in[6]" output="mac_out_accumulator_chain_out.saturatechainout"/>
                  <direct name="control_in_c_7" input="mac_out.control_in[7]" output="mac_out_accumulator_chain_out.zerochainout"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_accumulator_chain_out.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_accumulator_chain_out.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_accumulator_chain_out.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_accumulator_chain_out.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 44 (dataa width + 8) in this mode -->
                  <direct name="out_c2" input="mac_out_accumulator_chain_out.dataout" output="mac_out.data_out[43:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_1" input="mac_out_accumulator_chain_out.overflow" output="mac_out.signal_out[0]"/>
                  <direct name="signal_2" input="mac_out_accumulator_chain_out.saturatechainoutoverflow" output="mac_out.signal_out[1]"/>
                  <direct name="signal_3" input="mac_out_accumulator_chain_out.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_accumulator_chain_out.clk"/>
                </interconnect>
              </mode>
              <!-- accumulator_chain_out -->
              <mode name="accumulator_chain_out.input_type{comb}.output_type{reg}">
                <pb_type name="mac_out_accumulator_chain_out" blif_model=".subckt stratixiv_mac_out.opmode{accumulator_chain_out}.input_type{comb}.output_type{reg}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="chainin" num_pins="44"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="zeroacc" num_pins="1"/>
                  <input name="roundchainout" num_pins="1"/>
                  <input name="saturatechainout" num_pins="1"/>
                  <input name="zerochainout" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="44"/>
                  <output name="overflow" num_pins="1"/>
                  <output name="saturatechainoutoverflow" num_pins="1"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has a combinational input with a registered out.  

                       Measuring with QII in 'two level adder chain out' mode we arrived at the following values:
                          Output Register Setup Time (oTsu):              99 ps
                          Output Register Hold Time (uTh):                48 ps
					   The following maximum values:
                          Output Register Clock-to-Q Time (oTcq):         97 ps
                          Combinational Output delay to dataout (oTd):   333 ps
                          Input delay to the output registers (iTd):    1227 ps
					   The following minimum values:
                          Output Register Clock-to-Q Time (oTcq):         97 ps
                          Combinational Output delay to dataout (oTd):   180 ps
                          Input delay to the output registers (iTd):     475 ps


                       This results in the following Tsu and Tcq times:
                          'data*' comb delay : iTd         =   max: 1227 ps	 |  min: 475 ps
                          'dataout' Tsu      : oTsu        = 		  99 ps   
                          'dataout' uTh      : uTh         =  		  48 ps   
                          'dataout' Tcq      : oTcq + oTd  =   max:  430 ps	 |  min: 277 ps
                          All others Tcq     : oTcq        =   max:   97 ps	 |  min:  97 ps
                          All others Tsu     : oTsu        = 		  99 ps
                          All others uTh     : uTh         = 		  48 ps
                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.chainin" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.round" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.saturate" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.zeroacc" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.roundchainout" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.saturatechainout" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.zerochainout" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.chainin" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.round" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.saturate" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.zeroacc" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.roundchainout" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.saturatechainout" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.zerochainout" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.ena" value="48e-12"/>
                  <!-- Input combinational delay -->
                  <delay_constant in_port="mac_out_accumulator_chain_out.dataa" out_port="mac_out_accumulator_chain_out.dataout" max="1227e-12" min="475e-12"/>
                  <delay_constant in_port="mac_out_accumulator_chain_out.datab" out_port="mac_out_accumulator_chain_out.dataout" max="1227e-12" min="475e-12"/>
                  <delay_constant in_port="mac_out_accumulator_chain_out.datac" out_port="mac_out_accumulator_chain_out.dataout" max="1227e-12" min="475e-12"/>
                  <delay_constant in_port="mac_out_accumulator_chain_out.datad" out_port="mac_out_accumulator_chain_out.dataout" max="1227e-12" min="475e-12"/>
                  <!-- Internal output timing -->
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.dataout" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.dataout" value="48e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator_chain_out.dataout" max="430e-12" min="277e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator_chain_out.overflow" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator_chain_out.saturatechainoutoverflow" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator_chain_out.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_accumulator_chain_out.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_comb_reg" in_port="mac_out.data_in[0]" out_port="mac_out_accumulator_chain_out.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_comb_reg" in_port="mac_out.data_in[0]" out_port="mac_out_accumulator_chain_out.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_accumulator_chain_out.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_comb_reg" in_port="mac_out.data_in[36]" out_port="mac_out_accumulator_chain_out.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_comb_reg" in_port="mac_out.data_in[36]" out_port="mac_out_accumulator_chain_out.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_accumulator_chain_out.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_comb_reg" in_port="mac_out.data_in[72]" out_port="mac_out_accumulator_chain_out.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_comb_reg" in_port="mac_out.data_in[72]" out_port="mac_out_accumulator_chain_out.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_accumulator_chain_out.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_comb_reg" in_port="mac_out.data_in[108]" out_port="mac_out_accumulator_chain_out.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_comb_reg" in_port="mac_out.data_in[108]" out_port="mac_out_accumulator_chain_out.datad[0]"/>
                  </direct>
                  <!-- Arithmetic chain input -->
                  <direct name="data_c5" input="mac_out.chain_in" output="mac_out_accumulator_chain_out.chainin"/>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_accumulator_chain_out.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_accumulator_chain_out.signb"/>
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_accumulator_chain_out.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_accumulator_chain_out.saturate"/>
                  <direct name="control_in_c_4" input="mac_out.control_in[4]" output="mac_out_accumulator_chain_out.zeroacc"/>
                  <direct name="control_in_c_5" input="mac_out.control_in[5]" output="mac_out_accumulator_chain_out.roundchainout"/>
                  <direct name="control_in_c_6" input="mac_out.control_in[6]" output="mac_out_accumulator_chain_out.saturatechainout"/>
                  <direct name="control_in_c_7" input="mac_out.control_in[7]" output="mac_out_accumulator_chain_out.zerochainout"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_accumulator_chain_out.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_accumulator_chain_out.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_accumulator_chain_out.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_accumulator_chain_out.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 44 (dataa width + 8) in this mode -->
                  <direct name="out_c2" input="mac_out_accumulator_chain_out.dataout" output="mac_out.data_out[43:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_1" input="mac_out_accumulator_chain_out.overflow" output="mac_out.signal_out[0]"/>
                  <direct name="signal_2" input="mac_out_accumulator_chain_out.saturatechainoutoverflow" output="mac_out.signal_out[1]"/>
                  <direct name="signal_3" input="mac_out_accumulator_chain_out.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_accumulator_chain_out.clk"/>
                </interconnect>
              </mode>
              <!-- accumulator_chain_out -->
              <mode name="accumulator_chain_out.input_type{reg}.output_type{reg}">
                <pb_type name="mac_out_accumulator_chain_out" blif_model=".subckt stratixiv_mac_out.opmode{accumulator_chain_out}.input_type{reg}.output_type{reg}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="chainin" num_pins="44"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="zeroacc" num_pins="1"/>
                  <input name="roundchainout" num_pins="1"/>
                  <input name="saturatechainout" num_pins="1"/>
                  <input name="zerochainout" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="44"/>
                  <output name="overflow" num_pins="1"/>
                  <output name="saturatechainoutoverflow" num_pins="1"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has a registered input and a registered out.  
                       We model the combinational input delay as part of the setup time, and
                       the combinational output delay as part of the clock to q time.

                       Note that there may or may not actually have been additional pipelining
                       inside the DSP block, so in this case we are not cycle accurate to Stratix IV.
                       Since Stratix IV DSP blocks are practically limited to an speed of 510MHz,
                       we create an internal combinational path which models ths limit.

                       Measuring with QII in 'two level adder chain out' we arrived at the following values:
                          Input/Output Register Setup Time (iTsu/oTsu):      99ps
                          Input/Output Register Hold Time (uTh):			 48ps
                       We arrived at the following maximum values using QII:
                          Input/Output Register Clock-to-Q Time (iTcq/oTcq): 97ps
                          Combinational Output delay to dataout (oTd):      333ps
                          Input delay to the input registers (iTd):         213ps
                       Also the following minimum values using QII:
                          Input/Output Register Clock-to-Q Time (iTcq/oTcq): 97ps
                          Combinational Output delay to dataout (oTd):      180ps
                          Input delay to the input registers (iTd):          44ps
                          Minimum comb delay:                              456 ps

                       This results in the following Tsu, uTh, and Tcq times:
                          'data*' Tsu        : iTsu + iTd  = 	   312ps
                          'data*' uTh        : uTh - iTd   = 	     4ps 
                          'dataout' Tcq      : oTcq + oTd  =  max: 430ps  |  min: 277ps
                          All others Tcq     : oTcq        =  max:  97ps  |  min: 97ps
                          All others Tsu     : iTsu        = 		99ps
                          All others uTh     : uTh         = 		48ps

                          Internal Tsu: iTsu               =        99ps
                          Internal uTh:  uTh               =        48ps
                          Internal Tcq: iTcq               =        97ps

                          Maximum comb delay  : (1 / 510MHz) - iTsu - iTcq = 1765ps
                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.dataa" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.datab" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.datac" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.datad" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.chainin" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.round" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.saturate" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.zeroacc" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.roundchainout" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.saturatechainout" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.zerochainout" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.dataa" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.datab" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.datac" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.datad" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.chainin" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.round" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.saturate" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.zeroacc" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.roundchainout" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.saturatechainout" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.zerochainout" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.ena" value="48e-12"/>
                  <!-- Internal input timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator_chain_out.dataa" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator_chain_out.datab" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator_chain_out.datac" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator_chain_out.datad" max="97e-12" min="97e-12"/>
                  <!-- Internal combinational delay -->
                  <delay_constant in_port="mac_out_accumulator_chain_out.dataa" out_port="mac_out_accumulator_chain_out.dataout" max="1765e-12" min="456e-12"/>
                  <delay_constant in_port="mac_out_accumulator_chain_out.datab" out_port="mac_out_accumulator_chain_out.dataout" max="1765e-12" min="456e-12"/>
                  <delay_constant in_port="mac_out_accumulator_chain_out.datac" out_port="mac_out_accumulator_chain_out.dataout" max="1765e-12" min="456e-12"/>
                  <delay_constant in_port="mac_out_accumulator_chain_out.datad" out_port="mac_out_accumulator_chain_out.dataout" max="1765e-12" min="456e-12"/>
                  <!-- Internal output timing -->
                  <T_setup clock="clk" port="mac_out_accumulator_chain_out.dataout" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_accumulator_chain_out.dataout" value="48e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator_chain_out.dataout" max="430e-12" min="277e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator_chain_out.overflow" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator_chain_out.saturatechainoutoverflow" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_accumulator_chain_out.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_accumulator_chain_out.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_reg_reg" in_port="mac_out.data_in[0]" out_port="mac_out_accumulator_chain_out.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_reg_reg" in_port="mac_out.data_in[0]" out_port="mac_out_accumulator_chain_out.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_accumulator_chain_out.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_reg_reg" in_port="mac_out.data_in[36]" out_port="mac_out_accumulator_chain_out.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_reg_reg" in_port="mac_out.data_in[36]" out_port="mac_out_accumulator_chain_out.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_accumulator_chain_out.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_reg_reg" in_port="mac_out.data_in[72]" out_port="mac_out_accumulator_chain_out.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_reg_reg" in_port="mac_out.data_in[72]" out_port="mac_out_accumulator_chain_out.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_accumulator_chain_out.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_reg_reg" in_port="mac_out.data_in[108]" out_port="mac_out_accumulator_chain_out.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_reg_reg" in_port="mac_out.data_in[108]" out_port="mac_out_accumulator_chain_out.datad[0]"/>
                  </direct>
                  <!-- Arithmetic chain input -->
                  <direct name="data_c5" input="mac_out.chain_in" output="mac_out_accumulator_chain_out.chainin"/>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_accumulator_chain_out.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_accumulator_chain_out.signb"/>
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_accumulator_chain_out.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_accumulator_chain_out.saturate"/>
                  <direct name="control_in_c_4" input="mac_out.control_in[4]" output="mac_out_accumulator_chain_out.zeroacc"/>
                  <direct name="control_in_c_5" input="mac_out.control_in[5]" output="mac_out_accumulator_chain_out.roundchainout"/>
                  <direct name="control_in_c_6" input="mac_out.control_in[6]" output="mac_out_accumulator_chain_out.saturatechainout"/>
                  <direct name="control_in_c_7" input="mac_out.control_in[7]" output="mac_out_accumulator_chain_out.zerochainout"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_accumulator_chain_out.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_accumulator_chain_out.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_accumulator_chain_out.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_accumulator_chain_out.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 44 (dataa width + 8) in this mode -->
                  <direct name="out_c2" input="mac_out_accumulator_chain_out.dataout" output="mac_out.data_out[43:0]"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_1" input="mac_out_accumulator_chain_out.overflow" output="mac_out.signal_out[0]"/>
                  <direct name="signal_2" input="mac_out_accumulator_chain_out.saturatechainoutoverflow" output="mac_out.signal_out[1]"/>
                  <direct name="signal_3" input="mac_out_accumulator_chain_out.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_accumulator_chain_out.clk"/>
                </interconnect>
              </mode>
              <!-- accumulator_chain_out -->
              <mode name="shift.input_type{comb}.output_type{comb}">
                <pb_type name="mac_out_shift" blif_model=".subckt stratixiv_mac_out.opmode{shift}.input_type{comb}.output_type{comb}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="rotate" num_pins="1"/>
                  <input name="shiftright" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <output name="dataout" num_pins="72"/>
                  <output name="dftout" num_pins="1"/>
                  <!-- 
                       In this mode the block is purely combinational. We model only the main data path, but add 
                       zero delay edges to other possible timing paths through the block.  It is very unlikely 
                       that the non-datapath signals would every end up on the critical path.

                       Maximum delay through the mac_out in this mode is 1765ps, and minimum delay is 763ps,
					   as measured using the 'two level chain out' mode in QII.
                       -->
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_shift.dataa" out_port="mac_out_shift.dataout"/>
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_shift.datab" out_port="mac_out_shift.dataout"/>
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_shift.datac" out_port="mac_out_shift.dataout"/>
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_shift.datad" out_port="mac_out_shift.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_shift.signa" out_port="mac_out_shift.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_shift.signb" out_port="mac_out_shift.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_shift.rotate" out_port="mac_out_shift.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_shift.shiftright" out_port="mac_out_shift.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_shift.devclrn" out_port="mac_out_shift.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_shift.devpor" out_port="mac_out_shift.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_shift.aclr" out_port="mac_out_shift.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_shift.ena" out_port="mac_out_shift.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_shift.dataa" out_port="mac_out_shift.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_shift.datab" out_port="mac_out_shift.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_shift.datac" out_port="mac_out_shift.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_shift.datad" out_port="mac_out_shift.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_shift.signa" out_port="mac_out_shift.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_shift.signb" out_port="mac_out_shift.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_shift.rotate" out_port="mac_out_shift.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_shift.shiftright" out_port="mac_out_shift.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_shift.devclrn" out_port="mac_out_shift.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_shift.devpor" out_port="mac_out_shift.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_shift.ena" out_port="mac_out_shift.dftout"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_shift.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_shift_comb_comb" in_port="mac_out.data_in[0]" out_port="mac_out_shift.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_shift_comb_comb" in_port="mac_out.data_in[0]" out_port="mac_out_shift.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_shift.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_shift_comb_comb" in_port="mac_out.data_in[36]" out_port="mac_out_shift.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_shift_comb_comb" in_port="mac_out.data_in[36]" out_port="mac_out_shift.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_shift.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_shift_comb_comb" in_port="mac_out.data_in[72]" out_port="mac_out_shift.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_shift_comb_comb" in_port="mac_out.data_in[72]" out_port="mac_out_shift.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_shift.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_shift_comb_comb" in_port="mac_out.data_in[108]" out_port="mac_out_shift.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_shift_comb_comb" in_port="mac_out.data_in[108]" out_port="mac_out_shift.datad[0]"/>
                  </direct>
                  <!-- control inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_shift.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_shift.signb"/>
                  <direct name="control_in_c_9" input="mac_out.control_in[9]" output="mac_out_shift.rotate"/>
                  <direct name="control_in_c_10" input="mac_out.control_in[10]" output="mac_out_shift.shiftright"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_shift.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_shift.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_shift.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_shift.ena"/>
                  <!-- data output -->
                  <!-- Max output width of 72 (dataa width + datab width) in this mode -->
                  <direct name="out_c2" input="mac_out_shift.dataout" output="mac_out.data_out"/>
                  <!-- signal outputs -->
                  <direct name="signal_3" input="mac_out_shift.dftout" output="mac_out.signal_out[2]"/>
                </interconnect>
              </mode>
              <!-- shift-->
              <mode name="shift.input_type{reg}.output_type{comb}">
                <pb_type name="mac_out_shift" blif_model=".subckt stratixiv_mac_out.opmode{shift}.input_type{reg}.output_type{comb}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="rotate" num_pins="1"/>
                  <input name="shiftright" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="72"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has input registers with a combinational output.  

                       Measuring with QII in 'two level adder chain out mode' we arrived at the following values:
                          Input Register Setup Time (iTsu):              99ps
                          Input Register Hold Time (uTh):     	         48ps
					            The following maximum delays through setup analysis in QII:
                          Input Register Clock-to-Q Time (iTcq):         97ps
                          Input delay to the input registers (iTd):     213ps
                          Combinational Output delay to dataout (oTd): 1689ps
					            The following minimum delays through setup analysis in QII:
                          Input Register Clock-to-Q Time (iTcq):         97ps
                          Input delay to the input registers (iTd):      44ps
                          Combinational Output delay to dataout (oTd):  806ps
					   

                       This results in the following Tsu and Tcq times:
                          'data*' Tsu        : iTsu + iTd  =         312 ps
                          'data*' uTh        : uTh - iTd   =           4 ps
                          All other Tsu      : iTsu        =          99 ps
                          All other uTh      : uTh         =          48 ps
                          'data*' Tcq        : iTcq        =   max:   97 ps  |	min: 97 ps
                          'data*' comb delay : oTd         =   max: 1689 ps  | 	min: 806 ps
                          All other Tcq      : iTcq        =   max:   97 ps  |	min: 97 ps
                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_shift.dataa" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.datab" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.datac" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.datad" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.rotate" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.shiftright" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_shift.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.dataa" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.datab" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.datac" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.datad" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.rotate" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.shiftright" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_shift.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.ena" value="48e-12"/>
                  <!-- Internal input timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_shift.dataa" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_shift.datab" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_shift.datac" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_shift.datad" max="97e-12" min="97e-12"/>
                  <!-- Output combinational delay -->
                  <delay_constant in_port="mac_out_shift.dataa" out_port="mac_out_shift.dataout" max="1689e-12" min="806e-12"/>
                  <delay_constant in_port="mac_out_shift.datab" out_port="mac_out_shift.dataout" max="1689e-12" min="806e-12"/>
                  <delay_constant in_port="mac_out_shift.datac" out_port="mac_out_shift.dataout" max="1689e-12" min="806e-12"/>
                  <delay_constant in_port="mac_out_shift.datad" out_port="mac_out_shift.dataout" max="1689e-12" min="806e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_shift.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_shift.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_shift_reg_comb" in_port="mac_out.data_in[0]" out_port="mac_out_shift.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_shift_reg_comb" in_port="mac_out.data_in[0]" out_port="mac_out_shift.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_shift.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_shift_reg_comb" in_port="mac_out.data_in[36]" out_port="mac_out_shift.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_shift_reg_comb" in_port="mac_out.data_in[36]" out_port="mac_out_shift.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_shift.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_shift_reg_comb" in_port="mac_out.data_in[72]" out_port="mac_out_shift.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_shift_reg_comb" in_port="mac_out.data_in[72]" out_port="mac_out_shift.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_shift.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_shift_reg_comb" in_port="mac_out.data_in[108]" out_port="mac_out_shift.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_shift_reg_comb" in_port="mac_out.data_in[108]" out_port="mac_out_shift.datad[0]"/>
                  </direct>
                  <!-- control inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_shift.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_shift.signb"/>
                  <direct name="control_in_c_9" input="mac_out.control_in[9]" output="mac_out_shift.rotate"/>
                  <direct name="control_in_c_10" input="mac_out.control_in[10]" output="mac_out_shift.shiftright"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_shift.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_shift.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_shift.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_shift.ena"/>
                  <!-- data output -->
                  <!-- Max output width of 72 (dataa width + datab width) in this mode -->
                  <direct name="out_c2" input="mac_out_shift.dataout" output="mac_out.data_out"/>
                  <!-- signal outputs -->
                  <direct name="signal_3" input="mac_out_shift.dftout" output="mac_out.signal_out[2]"/>
                  <!-- clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_shift.clk"/>
                </interconnect>
              </mode>
              <!-- shift-->
              <mode name="shift.input_type{comb}.output_type{reg}">
                <pb_type name="mac_out_shift" blif_model=".subckt stratixiv_mac_out.opmode{shift}.input_type{comb}.output_type{reg}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="rotate" num_pins="1"/>
                  <input name="shiftright" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="72"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has a combinational input with a registered out.  

                       Measuring with QII in 'two level adder chain out' mode we arrived at the following values:
                          Output Register Setup Time (oTsu):              99 ps
                          Output Register Hold Time (uTh):                48 ps
					   The following maximum values:
                          Output Register Clock-to-Q Time (oTcq):         97 ps
                          Combinational Output delay to dataout (oTd):   333 ps
                          Input delay to the output registers (iTd):    1227 ps
					   The following minimum values:
                          Output Register Clock-to-Q Time (oTcq):         97 ps
                          Combinational Output delay to dataout (oTd):   180 ps
                          Input delay to the output registers (iTd):     475 ps


                       This results in the following Tsu and Tcq times:
                          'data*' comb delay : iTd         =   max: 1227 ps	 |  min: 475 ps
                          'dataout' Tsu      : oTsu        = 		  99 ps   
                          'dataout' uTh      : uTh         =  		  48 ps   
                          'dataout' Tcq      : oTcq + oTd  =   max:  430 ps	 |  min: 277 ps
                          All others Tcq     : oTcq        =   max:   97 ps	 |  min:  97 ps
                          All others Tsu     : oTsu        = 		  99 ps
                          All others uTh     : uTh         = 		  48 ps
                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_shift.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.rotate" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.shiftright" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_shift.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.rotate" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.shiftright" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_shift.ena" value="48e-12"/>
                  <!-- Input combinational delay -->
                  <delay_constant in_port="mac_out_shift.dataa" out_port="mac_out_shift.dataout" max="1227e-12" min="475e-12"/>
                  <delay_constant in_port="mac_out_shift.datab" out_port="mac_out_shift.dataout" max="1227e-12" min="475e-12"/>
                  <delay_constant in_port="mac_out_shift.datac" out_port="mac_out_shift.dataout" max="1227e-12" min="475e-12"/>
                  <delay_constant in_port="mac_out_shift.datad" out_port="mac_out_shift.dataout" max="1227e-12" min="475e-12"/>
                  <!-- Internal output timing -->
                  <T_setup clock="clk" port="mac_out_shift.dataout" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.dataout" value="48e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_shift.dataout" max="430e-12" min="277e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_shift.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_shift.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_shift_comb_reg" in_port="mac_out.data_in[0]" out_port="mac_out_shift.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_shift_comb_reg" in_port="mac_out.data_in[0]" out_port="mac_out_shift.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_shift.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_shift_comb_reg" in_port="mac_out.data_in[36]" out_port="mac_out_shift.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_shift_comb_reg" in_port="mac_out.data_in[36]" out_port="mac_out_shift.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_shift.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_shift_comb_reg" in_port="mac_out.data_in[72]" out_port="mac_out_shift.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_shift_comb_reg" in_port="mac_out.data_in[72]" out_port="mac_out_shift.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_shift.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_shift_comb_reg" in_port="mac_out.data_in[108]" out_port="mac_out_shift.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_shift_comb_reg" in_port="mac_out.data_in[108]" out_port="mac_out_shift.datad[0]"/>
                  </direct>
                  <!-- control inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_shift.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_shift.signb"/>
                  <direct name="control_in_c_9" input="mac_out.control_in[9]" output="mac_out_shift.rotate"/>
                  <direct name="control_in_c_10" input="mac_out.control_in[10]" output="mac_out_shift.shiftright"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_shift.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_shift.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_shift.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_shift.ena"/>
                  <!-- data output -->
                  <!-- Max output width of 72 (dataa width + datab width) in this mode -->
                  <direct name="out_c2" input="mac_out_shift.dataout" output="mac_out.data_out"/>
                  <!-- signal outputs -->
                  <direct name="signal_3" input="mac_out_shift.dftout" output="mac_out.signal_out[2]"/>
                  <!-- clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_shift.clk"/>
                </interconnect>
              </mode>
              <!-- shift-->
              <mode name="shift.input_type{reg}.output_type{reg}">
                <pb_type name="mac_out_shift" blif_model=".subckt stratixiv_mac_out.opmode{shift}.input_type{reg}.output_type{reg}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="datac" num_pins="36"/>
                  <input name="datad" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="rotate" num_pins="1"/>
                  <input name="shiftright" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="dataout" num_pins="72"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has a registered input and a registered out.  
                       We model the combinational input delay as part of the setup time, and
                       the combinational output delay as part of the clock to q time.

                       Note that there may or may not actually have been additional pipelining
                       inside the DSP block, so in this case we are not cycle accurate to Stratix IV.
                       Since Stratix IV DSP blocks are practically limited to an speed of 510MHz,
                       we create an internal combinational path which models ths limit.

                       Measuring with QII in 'two level adder chain out' we arrived at the following values:
                          Input/Output Register Setup Time (iTsu/oTsu):      99ps
                          Input/Output Register Hold Time (uTh):			 48ps
                       We arrived at the following maximum values using QII:
                          Input/Output Register Clock-to-Q Time (iTcq/oTcq): 97ps
                          Combinational Output delay to dataout (oTd):      333ps
                          Input delay to the input registers (iTd):         213ps
                       Also the following minimum values using QII:
                          Input/Output Register Clock-to-Q Time (iTcq/oTcq): 97ps
                          Combinational Output delay to dataout (oTd):      180ps
                          Input delay to the input registers (iTd):          44ps
                          Minimum comb delay:                              456 ps

                       This results in the following Tsu, uTh, and Tcq times:
                          'data*' Tsu        : iTsu + iTd  = 	   312ps
                          'data*' uTh        : uTh - iTd   = 	     4ps 
                          'dataout' Tcq      : oTcq + oTd  =  max: 430ps  |  min: 277ps
                          All others Tcq     : oTcq        =  max:  97ps  |  min: 97ps
                          All others Tsu     : iTsu        = 		99ps
                          All others uTh     : uTh         = 		8ps

                          Internal Tsu: iTsu               =        99ps
                          Internal uTh:  uTh               =        48ps
                          Internal Tcq: iTcq               =        97ps

                          Maximum comb delay  : (1 / 510MHz) - iTsu - iTcq = 1765ps

                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_shift.dataa" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.datab" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.datac" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.datad" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.rotate" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.shiftright" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_shift.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_shift.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.dataa" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.datab" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.datac" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.datad" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.rotate" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.shiftright" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_shift.ena" value="48e-12"/>
                  <!-- Internal input timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_shift.dataa" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_shift.datab" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_shift.datac" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_shift.datad" max="97e-12" min="97e-12"/>
                  <!-- Internal combinational delay -->
                  <delay_constant in_port="mac_out_shift.dataa" out_port="mac_out_shift.dataout" max="1765e-12" min="456e-12"/>
                  <delay_constant in_port="mac_out_shift.datab" out_port="mac_out_shift.dataout" max="1765e-12" min="456e-12"/>
                  <delay_constant in_port="mac_out_shift.datac" out_port="mac_out_shift.dataout" max="1765e-12" min="456e-12"/>
                  <delay_constant in_port="mac_out_shift.datad" out_port="mac_out_shift.dataout" max="1765e-12" min="456e-12"/>
                  <!-- Internal output timing -->
                  <T_setup clock="clk" port="mac_out_shift.dataout" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_shift.dataout" value="48e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_shift.dataout" max="430e-12" min="277e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_shift.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_shift.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_shift_reg_reg" in_port="mac_out.data_in[0]" out_port="mac_out_shift.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_shift_reg_reg" in_port="mac_out.data_in[0]" out_port="mac_out_shift.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_shift.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_shift_reg_reg" in_port="mac_out.data_in[36]" out_port="mac_out_shift.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_shift_reg_reg" in_port="mac_out.data_in[36]" out_port="mac_out_shift.datab[0]"/>
                  </direct>
                  <direct name="datac_in" input="mac_out.data_in[107:72]" output="mac_out_shift.datac">
                    <pack_pattern name="mac_mult_reg_to_mac_out_shift_reg_reg" in_port="mac_out.data_in[72]" out_port="mac_out_shift.datac[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_shift_reg_reg" in_port="mac_out.data_in[72]" out_port="mac_out_shift.datac[0]"/>
                  </direct>
                  <direct name="datad_in" input="mac_out.data_in[143:108]" output="mac_out_shift.datad">
                    <pack_pattern name="mac_mult_reg_to_mac_out_shift_reg_reg" in_port="mac_out.data_in[108]" out_port="mac_out_shift.datad[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_shift_reg_reg" in_port="mac_out.data_in[108]" out_port="mac_out_shift.datad[0]"/>
                  </direct>
                  <!-- control inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_shift.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_shift.signb"/>
                  <direct name="control_in_c_9" input="mac_out.control_in[9]" output="mac_out_shift.rotate"/>
                  <direct name="control_in_c_10" input="mac_out.control_in[10]" output="mac_out_shift.shiftright"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_shift.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_shift.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_shift.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_shift.ena"/>
                  <!-- data output -->
                  <!-- Max output width of 72 (dataa width + datab width) in this mode -->
                  <direct name="out_c2" input="mac_out_shift.dataout" output="mac_out.data_out"/>
                  <!-- signal outputs -->
                  <direct name="signal_3" input="mac_out_shift.dftout" output="mac_out.signal_out[2]"/>
                  <!-- clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_shift.clk"/>
                </interconnect>
              </mode>
              <!-- shift-->
              <mode name="loopback.input_type{comb}.output_type{comb}">
                <pb_type name="mac_out_loopback" blif_model=".subckt stratixiv_mac_out.opmode{loopback}.input_type{comb}.output_type{comb}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="zeroloopback" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <output name="loopbackout" num_pins="18"/>
                  <output name="dataout" num_pins="36"/>
                  <output name="dftout" num_pins="1"/>
                  <!-- 
                       In this mode the block is purely combinational. We model only the main data path, but add 
                       zero delay edges to other possible timing paths through the block.  It is very unlikely 
                       that the non-datapath signals would every end up on the critical path.

                       Maximum delay through the mac_out in this mode is 1765ps, and minimum delay is 763ps,
					   as measured using the 'two level chain out' mode in QII.
                       -->
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_loopback.dataa" out_port="mac_out_loopback.dataout"/>
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_loopback.datab" out_port="mac_out_loopback.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.signa" out_port="mac_out_loopback.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.signb" out_port="mac_out_loopback.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.round" out_port="mac_out_loopback.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.saturate" out_port="mac_out_loopback.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.zeroloopback" out_port="mac_out_loopback.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.devclrn" out_port="mac_out_loopback.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.devpor" out_port="mac_out_loopback.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.aclr" out_port="mac_out_loopback.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.ena" out_port="mac_out_loopback.dataout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.dataa" out_port="mac_out_loopback.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.datab" out_port="mac_out_loopback.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.signa" out_port="mac_out_loopback.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.signb" out_port="mac_out_loopback.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.round" out_port="mac_out_loopback.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.saturate" out_port="mac_out_loopback.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.zeroloopback" out_port="mac_out_loopback.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.devclrn" out_port="mac_out_loopback.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.devpor" out_port="mac_out_loopback.dftout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.ena" out_port="mac_out_loopback.dftout"/>
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_loopback.dataa" out_port="mac_out_loopback.loopbackout"/>
                  <delay_constant max="1765e-12" min="763e-12" in_port="mac_out_loopback.datab" out_port="mac_out_loopback.loopbackout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.signa" out_port="mac_out_loopback.loopbackout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.signb" out_port="mac_out_loopback.loopbackout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.round" out_port="mac_out_loopback.loopbackout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.saturate" out_port="mac_out_loopback.loopbackout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.zeroloopback" out_port="mac_out_loopback.loopbackout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.devclrn" out_port="mac_out_loopback.loopbackout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.devpor" out_port="mac_out_loopback.loopbackout"/>
                  <delay_constant max="0e-12" min="0e-12" in_port="mac_out_loopback.ena" out_port="mac_out_loopback.loopbackout"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_loopback.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_loopback_comb_comb" in_port="mac_out.data_in[0]" out_port="mac_out_loopback.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_loopback_comb_comb" in_port="mac_out.data_in[0]" out_port="mac_out_loopback.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_loopback.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_loopback_comb_comb" in_port="mac_out.data_in[36]" out_port="mac_out_loopback.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_loopback_comb_comb" in_port="mac_out.data_in[36]" out_port="mac_out_loopback.datab[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_loopback.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_loopback.signb"/>
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_loopback.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_loopback.saturate"/>
                  <direct name="control_in_c_8" input="mac_out.control_in[8]" output="mac_out_loopback.zeroloopback"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_loopback.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_loopback.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_loopback.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_loopback.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 36 (dataa width, NOT dataa width + 1) in this mode -->
                  <direct name="out_c2" input="mac_out_loopback.dataout" output="mac_out.data_out[35:0]"/>
                  <!-- Loopback Output -->
                  <direct name="loopback_out" input="mac_out_loopback.loopbackout" output="mac_out.loopback_out"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_3" input="mac_out_loopback.dftout" output="mac_out.signal_out[2]"/>
                </interconnect>
              </mode>
              <!-- loopback-->
              <mode name="loopback.input_type{reg}.output_type{comb}">
                <pb_type name="mac_out_loopback" blif_model=".subckt stratixiv_mac_out.opmode{loopback}.input_type{reg}.output_type{comb}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="zeroloopback" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="loopbackout" num_pins="18"/>
                  <output name="dataout" num_pins="36"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has input registers with a combinational output.  

                       Measuring with QII in 'two level adder chain out mode' we arrived at the following values:
                          Input Register Setup Time (iTsu):              99ps
                          Input Register Hold Time (uTh):     	         48ps
					            The following maximum delays through setup analysis in QII:
                          Input Register Clock-to-Q Time (iTcq):         97ps
                          Input delay to the input registers (iTd):     213ps
                          Combinational Output delay to dataout (oTd): 1689ps
					            The following minimum delays through setup analysis in QII:
                          Input Register Clock-to-Q Time (iTcq):         97ps
                          Input delay to the input registers (iTd):      44ps
                          Combinational Output delay to dataout (oTd):  806ps
					   

                       This results in the following Tsu and Tcq times:
                          'data*' Tsu        : iTsu + iTd  =         312 ps
                          'data*' uTh        : uTh - iTd   =           4 ps
                          All other Tsu      : iTsu        =          99 ps
                          All other uTh      : uTh         =          48 ps
                          'data*' Tcq        : iTcq        =   max:   97 ps  |	min: 97 ps
                          'data*' comb delay : oTd         =   max: 1689 ps  | 	min: 806 ps
                          All other Tcq      : iTcq        =   max:   97 ps  |	min: 97 ps
                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_loopback.dataa" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.datab" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.round" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.saturate" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.zeroloopback" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_loopback.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.dataa" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.datab" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.round" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.saturate" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.zeroloopback" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_loopback.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.ena" value="48e-12"/>
                  <!-- Internal input timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_loopback.dataa" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_loopback.datab" max="97e-12" min="97e-12"/>
                  <!-- Output combinational delay -->
                  <delay_constant in_port="mac_out_loopback.dataa" out_port="mac_out_loopback.dataout" max="1689e-12" min="806e-12"/>
                  <delay_constant in_port="mac_out_loopback.datab" out_port="mac_out_loopback.dataout" max="1689e-12" min="806e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_loopback.loopbackout" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_loopback.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_loopback.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_loopback_reg_comb" in_port="mac_out.data_in[0]" out_port="mac_out_loopback.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_loopback_reg_comb" in_port="mac_out.data_in[0]" out_port="mac_out_loopback.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_loopback.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_loopback_reg_comb" in_port="mac_out.data_in[36]" out_port="mac_out_loopback.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_loopback_reg_comb" in_port="mac_out.data_in[36]" out_port="mac_out_loopback.datab[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_loopback.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_loopback.signb"/>
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_loopback.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_loopback.saturate"/>
                  <direct name="control_in_c_8" input="mac_out.control_in[8]" output="mac_out_loopback.zeroloopback"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_loopback.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_loopback.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_loopback.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_loopback.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 36 (dataa width, NOT dataa width + 1) in this mode -->
                  <direct name="out_c2" input="mac_out_loopback.dataout" output="mac_out.data_out[35:0]"/>
                  <!-- Loopback Output -->
                  <direct name="loopback_out" input="mac_out_loopback.loopbackout" output="mac_out.loopback_out"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_3" input="mac_out_loopback.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_loopback.clk"/>
                </interconnect>
              </mode>
              <!-- loopback-->
              <mode name="loopback.input_type{comb}.output_type{reg}">
                <pb_type name="mac_out_loopback" blif_model=".subckt stratixiv_mac_out.opmode{loopback}.input_type{comb}.output_type{reg}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="zeroloopback" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="loopbackout" num_pins="18"/>
                  <output name="dataout" num_pins="36"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has a combinational input with a registered out.  

                       Measuring with QII in 'two level adder chain out' mode we arrived at the following values:
                          Output Register Setup Time (oTsu):              99 ps
                          Output Register Hold Time (uTh):                48 ps
					   The following maximum values:
                          Output Register Clock-to-Q Time (oTcq):         97 ps
                          Combinational Output delay to dataout (oTd):   333 ps
                          Input delay to the output registers (iTd):    1227 ps
					   The following minimum values:
                          Output Register Clock-to-Q Time (oTcq):         97 ps
                          Combinational Output delay to dataout (oTd):   180 ps
                          Input delay to the output registers (iTd):     475 ps


                       This results in the following Tsu and Tcq times:
                          'data*' comb delay : iTd         =   max: 1227 ps	 |  min: 475 ps
                          'dataout' Tsu      : oTsu        = 		  99 ps   
                          'dataout' uTh      : uTh         =  		  48 ps   
                          'dataout' Tcq      : oTcq + oTd  =   max:  430 ps	 |  min: 277 ps
                          All others Tcq     : oTcq        =   max:   97 ps	 |  min:  97 ps
                          All others Tsu     : oTsu        = 		  99 ps
                          All others uTh     : uTh         = 		  48 ps
                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_loopback.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.round" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.saturate" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.zeroloopback" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_loopback.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.round" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.saturate" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.zeroloopback" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_loopback.ena" value="48e-12"/>
                  <!-- Input combinational delay -->
                  <delay_constant in_port="mac_out_loopback.dataa" out_port="mac_out_loopback.dataout" max="1227e-12" min="475e-12"/>
                  <delay_constant in_port="mac_out_loopback.datab" out_port="mac_out_loopback.dataout" max="1227e-12" min="475e-12"/>
                  <!-- Internal output timing -->
                  <T_setup clock="clk" port="mac_out_loopback.dataout" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.dataout" value="48e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_loopback.dataout" max="430e-12" min="277e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_loopback.loopbackout" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_loopback.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_loopback.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_loopback_comb_reg" in_port="mac_out.data_in[0]" out_port="mac_out_loopback.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_loopback_comb_reg" in_port="mac_out.data_in[0]" out_port="mac_out_loopback.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_loopback.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_loopback_comb_reg" in_port="mac_out.data_in[36]" out_port="mac_out_loopback.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_loopback_comb_reg" in_port="mac_out.data_in[36]" out_port="mac_out_loopback.datab[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_loopback.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_loopback.signb"/>
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_loopback.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_loopback.saturate"/>
                  <direct name="control_in_c_8" input="mac_out.control_in[8]" output="mac_out_loopback.zeroloopback"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_loopback.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_loopback.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_loopback.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_loopback.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 36 (dataa width, NOT dataa width + 1) in this mode -->
                  <direct name="out_c2" input="mac_out_loopback.dataout" output="mac_out.data_out[35:0]"/>
                  <!-- Loopback Output -->
                  <direct name="loopback_out" input="mac_out_loopback.loopbackout" output="mac_out.loopback_out"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_3" input="mac_out_loopback.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_loopback.clk"/>
                </interconnect>
              </mode>
              <!-- loopback-->
              <mode name="loopback.input_type{reg}.output_type{reg}">
                <pb_type name="mac_out_loopback" blif_model=".subckt stratixiv_mac_out.opmode{loopback}.input_type{reg}.output_type{reg}" num_pb="1">
                  <input name="dataa" num_pins="36"/>
                  <input name="datab" num_pins="36"/>
                  <input name="signa" num_pins="1"/>
                  <input name="signb" num_pins="1"/>
                  <input name="round" num_pins="1"/>
                  <input name="saturate" num_pins="1"/>
                  <input name="zeroloopback" num_pins="1"/>
                  <input name="devclrn" num_pins="1"/>
                  <input name="devpor" num_pins="1"/>
                  <input name="aclr" num_pins="4"/>
                  <input name="ena" num_pins="4"/>
                  <clock name="clk" num_pins="1"/>
                  <output name="loopbackout" num_pins="18"/>
                  <output name="dataout" num_pins="36"/>
                  <output name="dftout" num_pins="1"/>
                  <!--
                       In this mode the mac_out has a registered input and a registered out.  
                       We model the combinational input delay as part of the setup time, and
                       the combinational output delay as part of the clock to q time.

                       Note that there may or may not actually have been additional pipelining
                       inside the DSP block, so in this case we are not cycle accurate to Stratix IV.
                       Since Stratix IV DSP blocks are practically limited to an speed of 510MHz,
                       we create an internal combinational path which models ths limit.

                       Measuring with QII in 'two level adder chain out' we arrived at the following values:
                          Input/Output Register Setup Time (iTsu/oTsu):      99ps
                          Input/Output Register Hold Time (uTh):			 48ps
                       We arrived at the following maximum values using QII:
                          Input/Output Register Clock-to-Q Time (iTcq/oTcq): 97ps
                          Combinational Output delay to dataout (oTd):      333ps
                          Input delay to the input registers (iTd):         213ps
                       Also the following minimum values using QII:
                          Input/Output Register Clock-to-Q Time (iTcq/oTcq): 97ps
                          Combinational Output delay to dataout (oTd):      180ps
                          Input delay to the input registers (iTd):          44ps
                          Minimum comb delay:                              456 ps

                       This results in the following Tsu, uTh, and Tcq times:
                          'data*' Tsu        : iTsu + iTd  = 	   312ps
                          'data*' uTh        : uTh - iTd   = 	     4ps 
                          'dataout' Tcq      : oTcq + oTd  =  max: 430ps  |  min: 277ps
                          All others Tcq     : oTcq        =  max:  97ps  |  min: 97ps
                          All others Tsu     : iTsu        = 		99ps
                          All others uTh     : uTh         = 		48ps

                          Internal Tsu: iTsu               =        99ps
                          Internal uTh:  uTh               =        48ps
                          Internal Tcq: iTcq               =        97ps

                          Maximum comb delay  : (1 / 510MHz) - iTsu - iTcq = 1765ps

                       -->
                  <!-- External input timing -->
                  <T_setup clock="clk" port="mac_out_loopback.dataa" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.datab" value="312e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.signa" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.signb" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.round" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.saturate" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.zeroloopback" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.devclrn" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.devpor" value="99e-12"/>
                  <T_setup clock="clk" port="mac_out_loopback.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_setup clock="clk" port="mac_out_loopback.ena" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.dataa" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.datab" value="4e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.signa" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.signb" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.round" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.saturate" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.zeroloopback" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.devclrn" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.devpor" value="48e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.aclr" value="0e-12"/>
                  <!-- Should really be recovery/removal for async signal -->
                  <T_hold clock="clk" port="mac_out_loopback.ena" value="48e-12"/>
                  <!-- Internal input timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_loopback.dataa" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_loopback.datab" max="97e-12" min="97e-12"/>
                  <!-- Internal combinational delay -->
                  <delay_constant in_port="mac_out_loopback.dataa" out_port="mac_out_loopback.dataout" max="1765e-12" min="456e-12"/>
                  <delay_constant in_port="mac_out_loopback.datab" out_port="mac_out_loopback.dataout" max="1765e-12" min="456e-12"/>
                  <!-- Internal output timing -->
                  <T_setup clock="clk" port="mac_out_loopback.dataout" value="99e-12"/>
                  <T_hold clock="clk" port="mac_out_loopback.dataout" value="48e-12"/>
                  <!-- External output timing -->
                  <T_clock_to_Q clock="clk" port="mac_out_loopback.dataout" max="430e-12" min="277e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_loopback.loopbackout" max="97e-12" min="97e-12"/>
                  <T_clock_to_Q clock="clk" port="mac_out_loopback.dftout" max="97e-12" min="97e-12"/>
                </pb_type>
                <!-- mac_out -->
                <interconnect>
                  <!-- Data inputs -->
                  <direct name="dataa_in" input="mac_out.data_in[35:0]" output="mac_out_loopback.dataa">
                    <pack_pattern name="mac_mult_reg_to_mac_out_loopback_reg_reg" in_port="mac_out.data_in[0]" out_port="mac_out_loopback.dataa[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_loopback_reg_reg" in_port="mac_out.data_in[0]" out_port="mac_out_loopback.dataa[0]"/>
                  </direct>
                  <direct name="datab_in" input="mac_out.data_in[71:36]" output="mac_out_loopback.datab">
                    <pack_pattern name="mac_mult_reg_to_mac_out_loopback_reg_reg" in_port="mac_out.data_in[36]" out_port="mac_out_loopback.datab[0]"/>
                    <pack_pattern name="mac_mult_comb_to_mac_out_loopback_reg_reg" in_port="mac_out.data_in[36]" out_port="mac_out_loopback.datab[0]"/>
                  </direct>
                  <!-- Control Inputs -->
                  <direct name="control_in_c_0" input="mac_out.control_in[0]" output="mac_out_loopback.signa"/>
                  <direct name="control_in_c_1" input="mac_out.control_in[1]" output="mac_out_loopback.signb"/>
                  <direct name="control_in_c_2" input="mac_out.control_in[2]" output="mac_out_loopback.round"/>
                  <direct name="control_in_c_3" input="mac_out.control_in[3]" output="mac_out_loopback.saturate"/>
                  <direct name="control_in_c_8" input="mac_out.control_in[8]" output="mac_out_loopback.zeroloopback"/>
                  <direct name="control_in_c_11" input="mac_out.control_in[11]" output="mac_out_loopback.devclrn"/>
                  <direct name="control_in_c_12" input="mac_out.control_in[12]" output="mac_out_loopback.devpor"/>
                  <direct name="control_in_c_13" input="mac_out.control_in[16:13]" output="mac_out_loopback.aclr"/>
                  <direct name="control_in_c_14" input="mac_out.control_in[20:17]" output="mac_out_loopback.ena"/>
                  <!-- Data output -->
                  <!-- Max output width of 36 (dataa width, NOT dataa width + 1) in this mode -->
                  <direct name="out_c2" input="mac_out_loopback.dataout" output="mac_out.data_out[35:0]"/>
                  <!-- Loopback Output -->
                  <direct name="loopback_out" input="mac_out_loopback.loopbackout" output="mac_out.loopback_out"/>
                  <!-- Signal Outputs -->
                  <direct name="signal_3" input="mac_out_loopback.dftout" output="mac_out.signal_out[2]"/>
                  <!-- Clock -->
                  <complete name="clock_c1" input="mac_out.clk" output="mac_out_loopback.clk"/>
                </interconnect>
              </mode>
              <!-- loopback-->
            </pb_type>
            <!-- mac_output -->
            <interconnect>
              <!-- half_DSP-mac_mult-mac_out interconnect -->
              <!-- INPUT SIGNALS -->
              <!-- mac_mult Data A Inputs (includes Scan A) -->
              <!--<mux name="data_mult0_a" input="half_DSP.data_in[143:126] half_DSP.scan_a_in"   output="mac_mult[0].dataa"/>-->
              <mux name="data_mult0_a_bit0" input="half_DSP.data_in[126] half_DSP.scan_a_in[0]" output="mac_mult[0].dataa[0]"/>
              <mux name="data_mult0_a_bit1" input="half_DSP.data_in[127] half_DSP.scan_a_in[1]" output="mac_mult[0].dataa[1]"/>
              <mux name="data_mult0_a_bit2" input="half_DSP.data_in[128] half_DSP.scan_a_in[2]" output="mac_mult[0].dataa[2]"/>
              <mux name="data_mult0_a_bit3" input="half_DSP.data_in[129] half_DSP.scan_a_in[3]" output="mac_mult[0].dataa[3]"/>
              <mux name="data_mult0_a_bit4" input="half_DSP.data_in[130] half_DSP.scan_a_in[4]" output="mac_mult[0].dataa[4]"/>
              <mux name="data_mult0_a_bit5" input="half_DSP.data_in[131] half_DSP.scan_a_in[5]" output="mac_mult[0].dataa[5]"/>
              <mux name="data_mult0_a_bit6" input="half_DSP.data_in[132] half_DSP.scan_a_in[6]" output="mac_mult[0].dataa[6]"/>
              <mux name="data_mult0_a_bit7" input="half_DSP.data_in[133] half_DSP.scan_a_in[7]" output="mac_mult[0].dataa[7]"/>
              <mux name="data_mult0_a_bit8" input="half_DSP.data_in[134] half_DSP.scan_a_in[8]" output="mac_mult[0].dataa[8]"/>
              <mux name="data_mult0_a_bit9" input="half_DSP.data_in[135] half_DSP.scan_a_in[9]" output="mac_mult[0].dataa[9]"/>
              <mux name="data_mult0_a_bit10" input="half_DSP.data_in[136] half_DSP.scan_a_in[10]" output="mac_mult[0].dataa[10]"/>
              <mux name="data_mult0_a_bit11" input="half_DSP.data_in[137] half_DSP.scan_a_in[11]" output="mac_mult[0].dataa[11]"/>
              <mux name="data_mult0_a_bit12" input="half_DSP.data_in[138] half_DSP.scan_a_in[12]" output="mac_mult[0].dataa[12]"/>
              <mux name="data_mult0_a_bit13" input="half_DSP.data_in[139] half_DSP.scan_a_in[13]" output="mac_mult[0].dataa[13]"/>
              <mux name="data_mult0_a_bit14" input="half_DSP.data_in[140] half_DSP.scan_a_in[14]" output="mac_mult[0].dataa[14]"/>
              <mux name="data_mult0_a_bit15" input="half_DSP.data_in[141] half_DSP.scan_a_in[15]" output="mac_mult[0].dataa[15]"/>
              <mux name="data_mult0_a_bit16" input="half_DSP.data_in[142] half_DSP.scan_a_in[16]" output="mac_mult[0].dataa[16]"/>
              <mux name="data_mult0_a_bit17" input="half_DSP.data_in[143] half_DSP.scan_a_in[17]" output="mac_mult[0].dataa[17]"/>
              <!--<mux name="data_mult1_a" input="half_DSP.data_in[107:90]  mac_mult[0].scanouta" output="mac_mult[1].dataa"/>-->
              <mux name="data_mult1_a_bit0" input="half_DSP.data_in[90]  mac_mult[0].scanouta[0]" output="mac_mult[1].dataa[0]"/>
              <mux name="data_mult1_a_bit1" input="half_DSP.data_in[91]  mac_mult[0].scanouta[1]" output="mac_mult[1].dataa[1]"/>
              <mux name="data_mult1_a_bit2" input="half_DSP.data_in[92]  mac_mult[0].scanouta[2]" output="mac_mult[1].dataa[2]"/>
              <mux name="data_mult1_a_bit3" input="half_DSP.data_in[93]  mac_mult[0].scanouta[3]" output="mac_mult[1].dataa[3]"/>
              <mux name="data_mult1_a_bit4" input="half_DSP.data_in[94]  mac_mult[0].scanouta[4]" output="mac_mult[1].dataa[4]"/>
              <mux name="data_mult1_a_bit5" input="half_DSP.data_in[95]  mac_mult[0].scanouta[5]" output="mac_mult[1].dataa[5]"/>
              <mux name="data_mult1_a_bit6" input="half_DSP.data_in[96]  mac_mult[0].scanouta[6]" output="mac_mult[1].dataa[6]"/>
              <mux name="data_mult1_a_bit7" input="half_DSP.data_in[97]  mac_mult[0].scanouta[7]" output="mac_mult[1].dataa[7]"/>
              <mux name="data_mult1_a_bit8" input="half_DSP.data_in[98]  mac_mult[0].scanouta[8]" output="mac_mult[1].dataa[8]"/>
              <mux name="data_mult1_a_bit9" input="half_DSP.data_in[99]  mac_mult[0].scanouta[9]" output="mac_mult[1].dataa[9]"/>
              <mux name="data_mult1_a_bit10" input="half_DSP.data_in[100]  mac_mult[0].scanouta[10]" output="mac_mult[1].dataa[10]"/>
              <mux name="data_mult1_a_bit11" input="half_DSP.data_in[101]  mac_mult[0].scanouta[11]" output="mac_mult[1].dataa[11]"/>
              <mux name="data_mult1_a_bit12" input="half_DSP.data_in[102]  mac_mult[0].scanouta[12]" output="mac_mult[1].dataa[12]"/>
              <mux name="data_mult1_a_bit13" input="half_DSP.data_in[103]  mac_mult[0].scanouta[13]" output="mac_mult[1].dataa[13]"/>
              <mux name="data_mult1_a_bit14" input="half_DSP.data_in[104]  mac_mult[0].scanouta[14]" output="mac_mult[1].dataa[14]"/>
              <mux name="data_mult1_a_bit15" input="half_DSP.data_in[105]  mac_mult[0].scanouta[15]" output="mac_mult[1].dataa[15]"/>
              <mux name="data_mult1_a_bit16" input="half_DSP.data_in[106]  mac_mult[0].scanouta[16]" output="mac_mult[1].dataa[16]"/>
              <mux name="data_mult1_a_bit17" input="half_DSP.data_in[107]  mac_mult[0].scanouta[17]" output="mac_mult[1].dataa[17]"/>
              <!--<mux name="data_mult2_a" input="half_DSP.data_in[71:54]   mac_mult[1].scanouta" output="mac_mult[2].dataa"/>-->
              <mux name="data_mult2_a_bit0" input="half_DSP.data_in[54]   mac_mult[1].scanouta[0]" output="mac_mult[2].dataa[0]"/>
              <mux name="data_mult2_a_bit1" input="half_DSP.data_in[55]   mac_mult[1].scanouta[1]" output="mac_mult[2].dataa[1]"/>
              <mux name="data_mult2_a_bit2" input="half_DSP.data_in[56]   mac_mult[1].scanouta[2]" output="mac_mult[2].dataa[2]"/>
              <mux name="data_mult2_a_bit3" input="half_DSP.data_in[57]   mac_mult[1].scanouta[3]" output="mac_mult[2].dataa[3]"/>
              <mux name="data_mult2_a_bit4" input="half_DSP.data_in[58]   mac_mult[1].scanouta[4]" output="mac_mult[2].dataa[4]"/>
              <mux name="data_mult2_a_bit5" input="half_DSP.data_in[59]   mac_mult[1].scanouta[5]" output="mac_mult[2].dataa[5]"/>
              <mux name="data_mult2_a_bit6" input="half_DSP.data_in[60]   mac_mult[1].scanouta[6]" output="mac_mult[2].dataa[6]"/>
              <mux name="data_mult2_a_bit7" input="half_DSP.data_in[61]   mac_mult[1].scanouta[7]" output="mac_mult[2].dataa[7]"/>
              <mux name="data_mult2_a_bit8" input="half_DSP.data_in[62]   mac_mult[1].scanouta[8]" output="mac_mult[2].dataa[8]"/>
              <mux name="data_mult2_a_bit9" input="half_DSP.data_in[63]   mac_mult[1].scanouta[9]" output="mac_mult[2].dataa[9]"/>
              <mux name="data_mult2_a_bit10" input="half_DSP.data_in[64]   mac_mult[1].scanouta[10]" output="mac_mult[2].dataa[10]"/>
              <mux name="data_mult2_a_bit11" input="half_DSP.data_in[65]   mac_mult[1].scanouta[11]" output="mac_mult[2].dataa[11]"/>
              <mux name="data_mult2_a_bit12" input="half_DSP.data_in[66]   mac_mult[1].scanouta[12]" output="mac_mult[2].dataa[12]"/>
              <mux name="data_mult2_a_bit13" input="half_DSP.data_in[67]   mac_mult[1].scanouta[13]" output="mac_mult[2].dataa[13]"/>
              <mux name="data_mult2_a_bit14" input="half_DSP.data_in[68]   mac_mult[1].scanouta[14]" output="mac_mult[2].dataa[14]"/>
              <mux name="data_mult2_a_bit15" input="half_DSP.data_in[69]   mac_mult[1].scanouta[15]" output="mac_mult[2].dataa[15]"/>
              <mux name="data_mult2_a_bit16" input="half_DSP.data_in[70]   mac_mult[1].scanouta[16]" output="mac_mult[2].dataa[16]"/>
              <mux name="data_mult2_a_bit17" input="half_DSP.data_in[71]   mac_mult[1].scanouta[17]" output="mac_mult[2].dataa[17]"/>
              <!--<mux name="data_mult3_a" input="half_DSP.data_in[35:18]   mac_mult[2].scanouta" output="mac_mult[3].dataa"/>-->
              <mux name="data_mult3_a_bit0" input="half_DSP.data_in[18]   mac_mult[2].scanouta[0]" output="mac_mult[3].dataa[0]"/>
              <mux name="data_mult3_a_bit1" input="half_DSP.data_in[19]   mac_mult[2].scanouta[1]" output="mac_mult[3].dataa[1]"/>
              <mux name="data_mult3_a_bit2" input="half_DSP.data_in[20]   mac_mult[2].scanouta[2]" output="mac_mult[3].dataa[2]"/>
              <mux name="data_mult3_a_bit3" input="half_DSP.data_in[21]   mac_mult[2].scanouta[3]" output="mac_mult[3].dataa[3]"/>
              <mux name="data_mult3_a_bit4" input="half_DSP.data_in[22]   mac_mult[2].scanouta[4]" output="mac_mult[3].dataa[4]"/>
              <mux name="data_mult3_a_bit5" input="half_DSP.data_in[23]   mac_mult[2].scanouta[5]" output="mac_mult[3].dataa[5]"/>
              <mux name="data_mult3_a_bit6" input="half_DSP.data_in[24]   mac_mult[2].scanouta[6]" output="mac_mult[3].dataa[6]"/>
              <mux name="data_mult3_a_bit7" input="half_DSP.data_in[25]   mac_mult[2].scanouta[7]" output="mac_mult[3].dataa[7]"/>
              <mux name="data_mult3_a_bit8" input="half_DSP.data_in[26]   mac_mult[2].scanouta[8]" output="mac_mult[3].dataa[8]"/>
              <mux name="data_mult3_a_bit9" input="half_DSP.data_in[27]   mac_mult[2].scanouta[9]" output="mac_mult[3].dataa[9]"/>
              <mux name="data_mult3_a_bit10" input="half_DSP.data_in[28]   mac_mult[2].scanouta[10]" output="mac_mult[3].dataa[10]"/>
              <mux name="data_mult3_a_bit11" input="half_DSP.data_in[29]   mac_mult[2].scanouta[11]" output="mac_mult[3].dataa[11]"/>
              <mux name="data_mult3_a_bit12" input="half_DSP.data_in[30]   mac_mult[2].scanouta[12]" output="mac_mult[3].dataa[12]"/>
              <mux name="data_mult3_a_bit13" input="half_DSP.data_in[31]   mac_mult[2].scanouta[13]" output="mac_mult[3].dataa[13]"/>
              <mux name="data_mult3_a_bit14" input="half_DSP.data_in[32]   mac_mult[2].scanouta[14]" output="mac_mult[3].dataa[14]"/>
              <mux name="data_mult3_a_bit15" input="half_DSP.data_in[33]   mac_mult[2].scanouta[15]" output="mac_mult[3].dataa[15]"/>
              <mux name="data_mult3_a_bit16" input="half_DSP.data_in[34]   mac_mult[2].scanouta[16]" output="mac_mult[3].dataa[16]"/>
              <mux name="data_mult3_a_bit17" input="half_DSP.data_in[35]   mac_mult[2].scanouta[17]" output="mac_mult[3].dataa[17]"/>
              <!-- mac_mult Data B Inputs -->
              <!-- NOTE: in the real startixiv the loopback only connects to mac_mult[0], however we must connect it to all the mac_mults to ensure the packer will succeed -->
              <!--<mux name="data_mult0_b" input="half_DSP.data_in[125:108] mac_output.loopback_out" output="mac_mult[0].datab"/>-->
              <mux name="data_mult0_b_bit0" input="half_DSP.data_in[108] mac_out.loopback_out[0]" output="mac_mult[0].datab[0]"/>
              <mux name="data_mult0_b_bit1" input="half_DSP.data_in[109] mac_out.loopback_out[1]" output="mac_mult[0].datab[1]"/>
              <mux name="data_mult0_b_bit2" input="half_DSP.data_in[110] mac_out.loopback_out[2]" output="mac_mult[0].datab[2]"/>
              <mux name="data_mult0_b_bit3" input="half_DSP.data_in[111] mac_out.loopback_out[3]" output="mac_mult[0].datab[3]"/>
              <mux name="data_mult0_b_bit4" input="half_DSP.data_in[112] mac_out.loopback_out[4]" output="mac_mult[0].datab[4]"/>
              <mux name="data_mult0_b_bit5" input="half_DSP.data_in[113] mac_out.loopback_out[5]" output="mac_mult[0].datab[5]"/>
              <mux name="data_mult0_b_bit6" input="half_DSP.data_in[114] mac_out.loopback_out[6]" output="mac_mult[0].datab[6]"/>
              <mux name="data_mult0_b_bit7" input="half_DSP.data_in[115] mac_out.loopback_out[7]" output="mac_mult[0].datab[7]"/>
              <mux name="data_mult0_b_bit8" input="half_DSP.data_in[116] mac_out.loopback_out[8]" output="mac_mult[0].datab[8]"/>
              <mux name="data_mult0_b_bit9" input="half_DSP.data_in[117] mac_out.loopback_out[9]" output="mac_mult[0].datab[9]"/>
              <mux name="data_mult0_b_bit10" input="half_DSP.data_in[118] mac_out.loopback_out[10]" output="mac_mult[0].datab[10]"/>
              <mux name="data_mult0_b_bit11" input="half_DSP.data_in[119] mac_out.loopback_out[11]" output="mac_mult[0].datab[11]"/>
              <mux name="data_mult0_b_bit12" input="half_DSP.data_in[120] mac_out.loopback_out[12]" output="mac_mult[0].datab[12]"/>
              <mux name="data_mult0_b_bit13" input="half_DSP.data_in[121] mac_out.loopback_out[13]" output="mac_mult[0].datab[13]"/>
              <mux name="data_mult0_b_bit14" input="half_DSP.data_in[122] mac_out.loopback_out[14]" output="mac_mult[0].datab[14]"/>
              <mux name="data_mult0_b_bit15" input="half_DSP.data_in[123] mac_out.loopback_out[15]" output="mac_mult[0].datab[15]"/>
              <mux name="data_mult0_b_bit16" input="half_DSP.data_in[124] mac_out.loopback_out[16]" output="mac_mult[0].datab[16]"/>
              <mux name="data_mult0_b_bit17" input="half_DSP.data_in[125] mac_out.loopback_out[17]" output="mac_mult[0].datab[17]"/>
              <!--<direct name="data_mult1_b" input="half_DSP.data_in[89:72]"                           output="mac_mult[1].datab"/>-->
              <mux name="data_mult1_b_bit0" input="half_DSP.data_in[72] mac_out.loopback_out[0]" output="mac_mult[1].datab[0]"/>
              <mux name="data_mult1_b_bit1" input="half_DSP.data_in[73] mac_out.loopback_out[1]" output="mac_mult[1].datab[1]"/>
              <mux name="data_mult1_b_bit2" input="half_DSP.data_in[74] mac_out.loopback_out[2]" output="mac_mult[1].datab[2]"/>
              <mux name="data_mult1_b_bit3" input="half_DSP.data_in[75] mac_out.loopback_out[3]" output="mac_mult[1].datab[3]"/>
              <mux name="data_mult1_b_bit4" input="half_DSP.data_in[76] mac_out.loopback_out[4]" output="mac_mult[1].datab[4]"/>
              <mux name="data_mult1_b_bit5" input="half_DSP.data_in[77] mac_out.loopback_out[5]" output="mac_mult[1].datab[5]"/>
              <mux name="data_mult1_b_bit6" input="half_DSP.data_in[78] mac_out.loopback_out[6]" output="mac_mult[1].datab[6]"/>
              <mux name="data_mult1_b_bit7" input="half_DSP.data_in[79] mac_out.loopback_out[7]" output="mac_mult[1].datab[7]"/>
              <mux name="data_mult1_b_bit8" input="half_DSP.data_in[80] mac_out.loopback_out[8]" output="mac_mult[1].datab[8]"/>
              <mux name="data_mult1_b_bit9" input="half_DSP.data_in[81] mac_out.loopback_out[9]" output="mac_mult[1].datab[9]"/>
              <mux name="data_mult1_b_bit10" input="half_DSP.data_in[82] mac_out.loopback_out[10]" output="mac_mult[1].datab[10]"/>
              <mux name="data_mult1_b_bit11" input="half_DSP.data_in[83] mac_out.loopback_out[11]" output="mac_mult[1].datab[11]"/>
              <mux name="data_mult1_b_bit12" input="half_DSP.data_in[84] mac_out.loopback_out[12]" output="mac_mult[1].datab[12]"/>
              <mux name="data_mult1_b_bit13" input="half_DSP.data_in[85] mac_out.loopback_out[13]" output="mac_mult[1].datab[13]"/>
              <mux name="data_mult1_b_bit14" input="half_DSP.data_in[86] mac_out.loopback_out[14]" output="mac_mult[1].datab[14]"/>
              <mux name="data_mult1_b_bit15" input="half_DSP.data_in[87] mac_out.loopback_out[15]" output="mac_mult[1].datab[15]"/>
              <mux name="data_mult1_b_bit16" input="half_DSP.data_in[88] mac_out.loopback_out[16]" output="mac_mult[1].datab[16]"/>
              <mux name="data_mult1_b_bit17" input="half_DSP.data_in[89] mac_out.loopback_out[17]" output="mac_mult[1].datab[17]"/>
              <!--<direct name="data_mult2_b" input="half_DSP.data_in[53:36]"                           output="mac_mult[2].datab"/>-->
              <mux name="data_mult2_b_bit0" input="half_DSP.data_in[36] mac_out.loopback_out[0]" output="mac_mult[2].datab[0]"/>
              <mux name="data_mult2_b_bit1" input="half_DSP.data_in[37] mac_out.loopback_out[1]" output="mac_mult[2].datab[1]"/>
              <mux name="data_mult2_b_bit2" input="half_DSP.data_in[38] mac_out.loopback_out[2]" output="mac_mult[2].datab[2]"/>
              <mux name="data_mult2_b_bit3" input="half_DSP.data_in[39] mac_out.loopback_out[3]" output="mac_mult[2].datab[3]"/>
              <mux name="data_mult2_b_bit4" input="half_DSP.data_in[40] mac_out.loopback_out[4]" output="mac_mult[2].datab[4]"/>
              <mux name="data_mult2_b_bit5" input="half_DSP.data_in[41] mac_out.loopback_out[5]" output="mac_mult[2].datab[5]"/>
              <mux name="data_mult2_b_bit6" input="half_DSP.data_in[42] mac_out.loopback_out[6]" output="mac_mult[2].datab[6]"/>
              <mux name="data_mult2_b_bit7" input="half_DSP.data_in[43] mac_out.loopback_out[7]" output="mac_mult[2].datab[7]"/>
              <mux name="data_mult2_b_bit8" input="half_DSP.data_in[44] mac_out.loopback_out[8]" output="mac_mult[2].datab[8]"/>
              <mux name="data_mult2_b_bit9" input="half_DSP.data_in[45] mac_out.loopback_out[9]" output="mac_mult[2].datab[9]"/>
              <mux name="data_mult2_b_bit10" input="half_DSP.data_in[46] mac_out.loopback_out[10]" output="mac_mult[2].datab[10]"/>
              <mux name="data_mult2_b_bit11" input="half_DSP.data_in[47] mac_out.loopback_out[11]" output="mac_mult[2].datab[11]"/>
              <mux name="data_mult2_b_bit12" input="half_DSP.data_in[48] mac_out.loopback_out[12]" output="mac_mult[2].datab[12]"/>
              <mux name="data_mult2_b_bit13" input="half_DSP.data_in[49] mac_out.loopback_out[13]" output="mac_mult[2].datab[13]"/>
              <mux name="data_mult2_b_bit14" input="half_DSP.data_in[50] mac_out.loopback_out[14]" output="mac_mult[2].datab[14]"/>
              <mux name="data_mult2_b_bit15" input="half_DSP.data_in[51] mac_out.loopback_out[15]" output="mac_mult[2].datab[15]"/>
              <mux name="data_mult2_b_bit16" input="half_DSP.data_in[52] mac_out.loopback_out[16]" output="mac_mult[2].datab[16]"/>
              <mux name="data_mult2_b_bit17" input="half_DSP.data_in[53] mac_out.loopback_out[17]" output="mac_mult[2].datab[17]"/>
              <!--<direct name="data_mult3_b" input="half_DSP.data_in[17:0]"                            output="mac_mult[3].datab"/>-->
              <mux name="data_mult3_b_bit0" input="half_DSP.data_in[0] mac_out.loopback_out[0]" output="mac_mult[3].datab[0]"/>
              <mux name="data_mult3_b_bit1" input="half_DSP.data_in[1] mac_out.loopback_out[1]" output="mac_mult[3].datab[1]"/>
              <mux name="data_mult3_b_bit2" input="half_DSP.data_in[2] mac_out.loopback_out[2]" output="mac_mult[3].datab[2]"/>
              <mux name="data_mult3_b_bit3" input="half_DSP.data_in[3] mac_out.loopback_out[3]" output="mac_mult[3].datab[3]"/>
              <mux name="data_mult3_b_bit4" input="half_DSP.data_in[4] mac_out.loopback_out[4]" output="mac_mult[3].datab[4]"/>
              <mux name="data_mult3_b_bit5" input="half_DSP.data_in[5] mac_out.loopback_out[5]" output="mac_mult[3].datab[5]"/>
              <mux name="data_mult3_b_bit6" input="half_DSP.data_in[6] mac_out.loopback_out[6]" output="mac_mult[3].datab[6]"/>
              <mux name="data_mult3_b_bit7" input="half_DSP.data_in[7] mac_out.loopback_out[7]" output="mac_mult[3].datab[7]"/>
              <mux name="data_mult3_b_bit8" input="half_DSP.data_in[8] mac_out.loopback_out[8]" output="mac_mult[3].datab[8]"/>
              <mux name="data_mult3_b_bit9" input="half_DSP.data_in[9] mac_out.loopback_out[9]" output="mac_mult[3].datab[9]"/>
              <mux name="data_mult3_b_bit10" input="half_DSP.data_in[10] mac_out.loopback_out[10]" output="mac_mult[3].datab[10]"/>
              <mux name="data_mult3_b_bit11" input="half_DSP.data_in[11] mac_out.loopback_out[11]" output="mac_mult[3].datab[11]"/>
              <mux name="data_mult3_b_bit12" input="half_DSP.data_in[12] mac_out.loopback_out[12]" output="mac_mult[3].datab[12]"/>
              <mux name="data_mult3_b_bit13" input="half_DSP.data_in[13] mac_out.loopback_out[13]" output="mac_mult[3].datab[13]"/>
              <mux name="data_mult3_b_bit14" input="half_DSP.data_in[14] mac_out.loopback_out[14]" output="mac_mult[3].datab[14]"/>
              <mux name="data_mult3_b_bit15" input="half_DSP.data_in[15] mac_out.loopback_out[15]" output="mac_mult[3].datab[15]"/>
              <mux name="data_mult3_b_bit16" input="half_DSP.data_in[16] mac_out.loopback_out[16]" output="mac_mult[3].datab[16]"/>
              <mux name="data_mult3_b_bit17" input="half_DSP.data_in[17] mac_out.loopback_out[17]" output="mac_mult[3].datab[17]"/>
              <!-- Scan out -->
              <direct name="half_DSP_scan_a_out" input="mac_mult[3].scanouta" output="half_DSP.scan_a_out"/>
              <!-- mac_output Data Inputs -->
              <!-- NOTE: this does not exist in the actual stratixiv, but is required to pack successfully: it allows mac_output acess to signals from general routing -->
              <direct name="data_mac_output_in" input="half_DSP.data_in" output="mac_out.data_in"/>
              <!-- MAC_OUTPUT Data In -->
              <!--<complete name="data_mac_mult_out_to_mac_output_in" input="mac_mult[3:0].dataout" output="mac_out.data_in"/>-->
              <direct name="data_mac_mult0_out_to_mac_output_in" input="mac_mult[0].dataout" output="mac_out.data_in[35:0]">
                <!-- Output only patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_output_only_comb_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_output_only_reg_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_output_only_comb_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_output_only_reg_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_output_only_comb_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_output_only_reg_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_output_only_comb_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_output_only_reg_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <!-- 36-bit multiply patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_comb_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_reg_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_comb_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_reg_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_comb_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_reg_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_comb_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_reg_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <!-- One Level Adder patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_one_level_adder_comb_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_one_level_adder_reg_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_one_level_adder_comb_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_one_level_adder_reg_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_one_level_adder_comb_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_one_level_adder_reg_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_one_level_adder_comb_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_one_level_adder_reg_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <!-- Double patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_double_comb_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_double_reg_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_double_comb_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_double_reg_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_double_comb_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_double_reg_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_double_comb_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_double_reg_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <!-- Two Level Adder patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_comb_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_reg_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_comb_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_reg_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_comb_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_reg_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_comb_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_reg_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <!-- Two-Level Adder Chain Out multiply patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_comb_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_reg_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_comb_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_reg_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_comb_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_reg_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_comb_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_reg_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <!-- Accmulator patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_comb_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_reg_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_comb_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_reg_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_comb_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_reg_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_comb_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_reg_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <!-- Accmulator chain out patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_comb_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_reg_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_comb_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_reg_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_comb_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_reg_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_comb_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_reg_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <!-- Shift patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_shift_comb_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_shift_reg_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_shift_comb_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_shift_reg_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_shift_comb_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_shift_reg_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_shift_comb_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_shift_reg_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <!-- Loopback patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_loopback_comb_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_loopback_reg_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_loopback_comb_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_loopback_reg_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_loopback_comb_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_loopback_reg_comb" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_loopback_comb_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_loopback_reg_reg" in_port="mac_mult[0].dataout[0]" out_port="mac_out.data_in[0]"/>
              </direct>
              <direct name="data_mac_mult1_out_to_mac_output_in" input="mac_mult[1].dataout" output="mac_out.data_in[71:36]">
                <!-- Output only patterns -->
                <!-- Note: no output_only patterns since it only uses mac_mult[0] -->
                <!-- 36-bit multiply patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_comb_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_reg_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_comb_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_reg_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_comb_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_reg_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_comb_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_reg_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <!-- One Level Adder patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_one_level_adder_comb_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_one_level_adder_reg_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_one_level_adder_comb_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_one_level_adder_reg_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_one_level_adder_comb_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_one_level_adder_reg_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_one_level_adder_comb_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_one_level_adder_reg_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <!-- Double patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_double_comb_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_double_reg_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_double_comb_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_double_reg_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_double_comb_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_double_reg_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_double_comb_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_double_reg_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <!-- Two Level Adder patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_comb_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_reg_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_comb_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_reg_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_comb_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_reg_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_comb_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_reg_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <!-- Two-Level Adder Chain Out multiply patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_comb_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_reg_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_comb_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_reg_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_comb_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_reg_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_comb_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_reg_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <!-- Accmulator patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_comb_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_reg_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_comb_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_reg_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_comb_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_reg_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_comb_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_reg_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <!-- Accmulator chain out patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_comb_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_reg_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_comb_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_reg_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_comb_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_reg_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_comb_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_reg_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <!-- Shift patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_shift_comb_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_shift_reg_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_shift_comb_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_shift_reg_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_shift_comb_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_shift_reg_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_shift_comb_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_shift_reg_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <!-- Loopback patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_loopback_comb_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_loopback_reg_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_loopback_comb_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_loopback_reg_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_loopback_comb_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_loopback_reg_comb" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_loopback_comb_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_loopback_reg_reg" in_port="mac_mult[1].dataout[0]" out_port="mac_out.data_in[36]"/>
              </direct>
              <direct name="data_mac_mult2_out_to_mac_output_in" input="mac_mult[2].dataout" output="mac_out.data_in[107:72]">
                <!-- Output only patterns -->
                <!-- Note: no output_only patterns since it only uses mac_mult[0] -->
                <!-- 36-bit multiply patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_comb_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_reg_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_comb_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_reg_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_comb_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_reg_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_comb_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_reg_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <!-- One Level Adder patterns -->
                <!-- Note: no one_leve_adder patterns since it only uses mac_mult[0] and mac_mult[1] -->
                <!-- Double patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_double_comb_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_double_reg_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_double_comb_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_double_reg_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_double_comb_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_double_reg_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_double_comb_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_double_reg_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <!-- Two Level Adder patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_comb_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_reg_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_comb_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_reg_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_comb_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_reg_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_comb_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_reg_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <!-- Two-Level Adder Chain Out multiply patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_comb_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_reg_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_comb_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_reg_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_comb_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_reg_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_comb_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_reg_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <!-- Accmulator patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_comb_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_reg_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_comb_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_reg_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_comb_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_reg_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_comb_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_reg_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <!-- Accmulator chain out patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_comb_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_reg_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_comb_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_reg_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_comb_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_reg_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_comb_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_reg_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <!-- Shift patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_shift_comb_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_shift_reg_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_shift_comb_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_shift_reg_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_shift_comb_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_shift_reg_comb" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_shift_comb_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_shift_reg_reg" in_port="mac_mult[2].dataout[0]" out_port="mac_out.data_in[72]"/>
                <!-- Loopback patterns -->
                <!-- Note: no loopback patterns since it only uses mac_mult[0] and mac_mult[1] -->
              </direct>
              <direct name="data_mac_mult3_out_to_mac_output_in" input="mac_mult[3].dataout" output="mac_out.data_in[143:108]">
                <!-- Output only patterns -->
                <!-- Note: no output_only patterns since it only uses mac_mult[0] -->
                <!-- 36-bit multiply patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_comb_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_reg_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_comb_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_36_bit_multiply_reg_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_comb_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_reg_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_comb_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_36_bit_multiply_reg_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <!-- One Level Adder patterns -->
                <!-- Note: no one_leve_adder patterns since it only uses mac_mult[0] and mac_mult[1] -->
                <!-- Double patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_double_comb_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_double_reg_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_double_comb_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_double_reg_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_double_comb_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_double_reg_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_double_comb_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_double_reg_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <!-- Two Level Adder patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_comb_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_reg_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_comb_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_reg_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_comb_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_reg_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_comb_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_reg_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <!-- Two-Level Adder Chain Out multiply patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_comb_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_reg_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_comb_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_two_level_adder_chain_out_reg_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_comb_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_reg_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_comb_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_two_level_adder_chain_out_reg_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <!-- Accmulator patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_comb_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_reg_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_comb_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_reg_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_comb_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_reg_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_comb_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_reg_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <!-- Accmulator chain out patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_comb_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_reg_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_comb_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_accumulator_chain_out_reg_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_comb_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_reg_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_comb_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_accumulator_chain_out_reg_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <!-- Shift patterns -->
                <pack_pattern name="mac_mult_comb_to_mac_out_shift_comb_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_shift_reg_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_shift_comb_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_comb_to_mac_out_shift_reg_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_shift_comb_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_shift_reg_comb" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_shift_comb_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <pack_pattern name="mac_mult_reg_to_mac_out_shift_reg_reg" in_port="mac_mult[3].dataout[0]" out_port="mac_out.data_in[108]"/>
                <!-- Loopback patterns -->
                <!-- Note: no loopback patterns since it only uses mac_mult[0] and mac_mult[1] -->
              </direct>
              <!-- mac_mult control in -->
              <!--<complete name="mac_control_in_0" input="half_DSP.control_in[0]"     output="mac_mult[3:0].signa"/>-->
              <direct name="mac_control_in_0_mult0" input="half_DSP.control_in[0]" output="mac_mult[0].signa"/>
              <direct name="mac_control_in_0_mult1" input="half_DSP.control_in[0]" output="mac_mult[1].signa"/>
              <direct name="mac_control_in_0_mult2" input="half_DSP.control_in[0]" output="mac_mult[2].signa"/>
              <direct name="mac_control_in_0_mult3" input="half_DSP.control_in[0]" output="mac_mult[3].signa"/>
              <!--<complete name="mac_control_in_1" input="half_DSP.control_in[1]"     output="mac_mult[3:0].signb"/>-->
              <direct name="mac_control_in_1_mult0" input="half_DSP.control_in[1]" output="mac_mult[0].signb"/>
              <direct name="mac_control_in_1_mult1" input="half_DSP.control_in[1]" output="mac_mult[1].signb"/>
              <direct name="mac_control_in_1_mult2" input="half_DSP.control_in[1]" output="mac_mult[2].signb"/>
              <direct name="mac_control_in_1_mult3" input="half_DSP.control_in[1]" output="mac_mult[3].signb"/>
              <!--<complete name="mac_control_in_4" input="half_DSP.control_in[11]"    output="mac_mult[3:0].devclrn"/>-->
              <direct name="mac_control_in_4_mult0" input="half_DSP.control_in[11]" output="mac_mult[0].devclrn"/>
              <direct name="mac_control_in_4_mult1" input="half_DSP.control_in[11]" output="mac_mult[1].devclrn"/>
              <direct name="mac_control_in_4_mult2" input="half_DSP.control_in[11]" output="mac_mult[2].devclrn"/>
              <direct name="mac_control_in_4_mult3" input="half_DSP.control_in[11]" output="mac_mult[3].devclrn"/>
              <!--<complete name="mac_control_in_5" input="half_DSP.control_in[12]"    output="mac_mult[3:0].devpor"/>-->
              <direct name="mac_control_in_5_mult0" input="half_DSP.control_in[12]" output="mac_mult[0].devpor"/>
              <direct name="mac_control_in_5_mult1" input="half_DSP.control_in[12]" output="mac_mult[1].devpor"/>
              <direct name="mac_control_in_5_mult2" input="half_DSP.control_in[12]" output="mac_mult[2].devpor"/>
              <direct name="mac_control_in_5_mult3" input="half_DSP.control_in[12]" output="mac_mult[3].devpor"/>
              <!--<complete name="mac_control_in_2" input="half_DSP.control_in[16:13]" output="mac_mult[3:0].aclr"/>-->
              <direct name="mac_control_in_2_mult0" input="half_DSP.control_in[16:13]" output="mac_mult[0].aclr"/>
              <direct name="mac_control_in_2_mult1" input="half_DSP.control_in[16:13]" output="mac_mult[1].aclr"/>
              <direct name="mac_control_in_2_mult2" input="half_DSP.control_in[16:13]" output="mac_mult[2].aclr"/>
              <direct name="mac_control_in_2_mult3" input="half_DSP.control_in[16:13]" output="mac_mult[3].aclr"/>
              <!--<complete name="mac_control_in_3" input="half_DSP.control_in[20:17]" output="mac_mult[3:0].ena"/>-->
              <direct name="mac_control_in_3_mult0" input="half_DSP.control_in[20:17]" output="mac_mult[0].ena"/>
              <direct name="mac_control_in_3_mult1" input="half_DSP.control_in[20:17]" output="mac_mult[1].ena"/>
              <direct name="mac_control_in_3_mult2" input="half_DSP.control_in[20:17]" output="mac_mult[2].ena"/>
              <direct name="mac_control_in_3_mult3" input="half_DSP.control_in[20:17]" output="mac_mult[3].ena"/>
              <!-- Clocks -->
              <!--<complete name="clock_c1" input="half_DSP.clk" output="mac_mult[3:0].clk"/>-->
              <direct name="clock_c1_mult0" input="half_DSP.clk" output="mac_mult[0].clk"/>
              <direct name="clock_c1_mult1" input="half_DSP.clk" output="mac_mult[1].clk"/>
              <direct name="clock_c1_mult2" input="half_DSP.clk" output="mac_mult[2].clk"/>
              <direct name="clock_c1_mult3" input="half_DSP.clk" output="mac_mult[3].clk"/>
              <direct name="clock_c2_output" input="half_DSP.clk" output="mac_out.clk"/>
              <!-- OUTPUT SIGNALS -->
              <!-- Signal Outputs -->
              <direct name="signal_output" input="mac_out.signal_out" output="half_DSP.signal_out"/>
              <!-- Arithmetic Chain -->
              <direct name="chain_in" input="half_DSP.chain_in" output="mac_out.chain_in"/>
              <!-- Chain out is the lower 44 bits of the data output -->
              <direct name="chain_out" input="mac_out.data_out[43:0]" output="half_DSP.chain_out"/>
              <!-- mac_out control in -->
              <direct name="mac_out_control_in" input="half_DSP.control_in" output="mac_out.control_in"/>
              <!-- mac_mult data outputs -->
              <!-- NOTE: this does not exist in the actual stratixiv, but is required to pack successfully: it allows mac_mults access to signals from general routing -->
              <complete name="out_c2" input="mac_mult[3:0].dataout" output="half_DSP.data_out"/>
              <!-- mac_out data outputs, includeing extra flexibility for loopback -->
              <complete name="out_c3" input="mac_out.data_out mac_out.loopback_out" output="half_DSP.data_out"/>
            </interconnect>
          </mode>
          <!-- half_DSP_normal -->
        </pb_type>
        <!-- half_DSP -->
        <interconnect>
          <!-- DSP-half_DSP interconnect -->
          <!-- DSP Arithmetic chain -->
          <!-- Real DSP chain connectivity 
          <direct name="chain_top" input="DSP.chain_in" output="half_DSP[0].chain_in"/>
          <direct name="chain_mid" input="half_DSP[0].chain_out" output="half_DSP[1].chain_in"/>
          <direct name="chain_bot" input="half_DSP[1].chain_out" output="DSP.chain_out"/> -->
          <!-- Extra DSP chain connectivity to route during packing -->
          <complete name="chain_top" input="DSP.chain_in half_DSP[1].chain_out" output="half_DSP[0].chain_in"/>
          <complete name="chain_mid" input="DSP.chain_in half_DSP[0].chain_out" output="half_DSP[1].chain_in"/>
          <complete name="chain_bot" input="half_DSP[0].chain_out half_DSP[1].chain_out" output="DSP.chain_out"/>
          <!-- INPUT SIGNALS -->
          <!-- Data Inputs, split betweent the two halves of the DSP block 
               
               From Quartus II the maximum LAB_LINE delay from global routing innto the inputs is 239ps on average.
               Similarly, the minimum LAB_LINE delay is 132ps.
               -->
          <direct input="DSP.data_in[287:144]" name="data_in_bot" output="half_DSP[1].data_in">
            <delay_constant max="239e-12" min="132e-12" in_port="DSP.data_in[287:144]" out_port="half_DSP[1].data_in"/>
          </direct>
          <direct input="DSP.data_in[143:0]" name="data_in_top" output="half_DSP[0].data_in">
            <delay_constant max="239e-12" min="132e-12" in_port="DSP.data_in[143:0]" out_port="half_DSP[0].data_in"/>
          </direct>
          <!-- scan_a chain (shift chain) -->
          <direct name="scan_a_top" input="DSP.scan_a_in" output="half_DSP[0].scan_a_in"/>
          <direct name="scan_a_mid" input="half_DSP[0].scan_a_out" output="half_DSP[1].scan_a_in"/>
          <direct name="scan_a_bot" input="half_DSP[1].scan_a_out" output="DSP.scan_a_out"/>
          <!-- Control -->
          <direct name="control_top" input="DSP.control_in" output="half_DSP[0].control_in"/>
          <direct name="control_bot" input="DSP.control_in" output="half_DSP[1].control_in"/>
          <!-- Clock -->
          <direct name="clk_top" input="DSP.clk" output="half_DSP[0].clk"/>
          <direct name="clk_bot" input="DSP.clk" output="half_DSP[1].clk"/>
          <!-- OUTPUT SIGNALS -->
          <!-- Data Outputs, split betweent the two halves of the DSP block 
               From QII the maximum MAC_BUFFER has a delay of 28ps and the minimum MAC_BUFFER has a delay of 27 ps
               -->
          <direct name="data_out_top" input="half_DSP[0].data_out" output="DSP.data_out_top">
            <delay_constant max="28e-12" min="27e-12" in_port="half_DSP[0].data_out" out_port="DSP.data_out_top"/>
          </direct>
          <direct name="data_out_bot" input="half_DSP[1].data_out" output="DSP.data_out_bot">
            <delay_constant max="28e-12" min="27e-12" in_port="half_DSP[1].data_out" out_port="DSP.data_out_bot"/>
          </direct>
          <!-- Signal/Control Outputs -->
          <direct name="signal_out_top" input="half_DSP[0].signal_out" output="DSP.signal_out[2:0]"/>
          <direct name="signal_out_bot" input="half_DSP[1].signal_out" output="DSP.signal_out[5:3]"/>
        </interconnect>
      </mode>
      <!-- DSP_normal -->
    </pb_type>
    <!-- DSP -->
    <!-- See comments in scripts/gen_stratixiv_memories_class.py for details on how these
         memory blocks were generated -->
    <pb_type name="M9K">
      <input name="data_addr_control_in" num_pins="104"/>
      <output name="data_out" num_pins="36"/>
      <output name="control_out" num_pins="3"/>
      <clock name="clk_in" num_pins="2"/>
      <mode name="ram">
        <pb_type name="ram_block_M9K" num_pb="1">
          <input name="control_in" num_pins="28"/>
          <input name="data_b_in" num_pins="18"/>
          <input name="data_a_in" num_pins="36"/>
          <input name="addr_a_in" num_pins="13"/>
          <input name="addr_b_in" num_pins="13"/>
          <output name="control_out" num_pins="3"/>
          <output name="data_out" num_pins="36"/>
          <clock name="clk_in" num_pins="2"/>
          <mode name="dual_port_reg-out_class_size_9K_A1Kx9_B1Kx9_composite_prim_ram_1x(A1Kx9_B1Kx9)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{10}.port_b_address_width{10}" class="memory" name="prim_ram_A1Kx9_B1Kx9" num_pb="1">
              <input name="portadatain" num_pins="9" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="10" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="10" port_class="address2"/>
              <output name="portbdataout" num_pins="9" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A1Kx9_B1Kx9.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A1Kx9_B1Kx9.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portbaddr"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A1Kx9_B1Kx9.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A1Kx9_B1Kx9.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A1Kx9_B1Kx9[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A1Kx9_B1Kx9[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A1Kx9_B1Kx9[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A1Kx9_B1Kx9[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A1Kx9_B1Kx9[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A1Kx9_B1Kx9[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A1Kx9_B1Kx9[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A1Kx9_B1Kx9[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A1Kx9_B1Kx9[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A1Kx9_B1Kx9[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A1Kx9_B1Kx9[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A1Kx9_B1Kx9[0].clk_portbin[0] prim_ram_A1Kx9_B1Kx9[0].clk_portain[0] prim_ram_A1Kx9_B1Kx9[0].clk_portaout[0] prim_ram_A1Kx9_B1Kx9[0].clk_portbout[0] "/>
              <complete input="prim_ram_A1Kx9_B1Kx9[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[9:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[9:0]" output="prim_ram_A1Kx9_B1Kx9[0].portaaddr[9:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[9:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portaaddr[9:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[9:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[9:0]" output="prim_ram_A1Kx9_B1Kx9[0].portbaddr[9:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[9:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portbaddr[9:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[8:0]" name="interconnect_split_ram_block_M9K_data_a_in_[8:0]" output="prim_ram_A1Kx9_B1Kx9[0].portadatain[8:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[8:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portadatain[8:0]"/>
              </direct>
              <direct input="prim_ram_A1Kx9_B1Kx9[0].portbdataout[8:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[8:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_9K_A1Kx9_B1Kx9_composite_prim_ram_1x(A1Kx9_B1Kx9)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{10}.port_b_address_width{10}" class="memory" name="prim_ram_A1Kx9_B1Kx9" num_pb="1">
              <input name="portadatain" num_pins="9" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="10" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="10" port_class="address2"/>
              <output name="portbdataout" num_pins="9" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portbaddr"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A1Kx9_B1Kx9[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A1Kx9_B1Kx9[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A1Kx9_B1Kx9[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A1Kx9_B1Kx9[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A1Kx9_B1Kx9[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A1Kx9_B1Kx9[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A1Kx9_B1Kx9[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A1Kx9_B1Kx9[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A1Kx9_B1Kx9[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A1Kx9_B1Kx9[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A1Kx9_B1Kx9[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A1Kx9_B1Kx9[0].clk_portbin[0] prim_ram_A1Kx9_B1Kx9[0].clk_portain[0] prim_ram_A1Kx9_B1Kx9[0].clk_portaout[0] prim_ram_A1Kx9_B1Kx9[0].clk_portbout[0] "/>
              <complete input="prim_ram_A1Kx9_B1Kx9[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[9:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[9:0]" output="prim_ram_A1Kx9_B1Kx9[0].portaaddr[9:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[9:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portaaddr[9:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[9:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[9:0]" output="prim_ram_A1Kx9_B1Kx9[0].portbaddr[9:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[9:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portbaddr[9:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[8:0]" name="interconnect_split_ram_block_M9K_data_a_in_[8:0]" output="prim_ram_A1Kx9_B1Kx9[0].portadatain[8:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[8:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portadatain[8:0]"/>
              </direct>
              <direct input="prim_ram_A1Kx9_B1Kx9[0].portbdataout[8:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[8:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_9K_A512x18_B512x18_composite_prim_ram_1x(A512x18_B512x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{9}.port_b_address_width{9}" class="memory" name="prim_ram_A512x18_B512x18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="9" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="9" port_class="address2"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A512x18_B512x18.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A512x18_B512x18.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portbaddr"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A512x18_B512x18.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A512x18_B512x18.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A512x18_B512x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A512x18_B512x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A512x18_B512x18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A512x18_B512x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A512x18_B512x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A512x18_B512x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A512x18_B512x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A512x18_B512x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A512x18_B512x18[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A512x18_B512x18[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A512x18_B512x18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A512x18_B512x18[0].clk_portbin[0] prim_ram_A512x18_B512x18[0].clk_portain[0] prim_ram_A512x18_B512x18[0].clk_portaout[0] prim_ram_A512x18_B512x18[0].clk_portbout[0] "/>
              <complete input="prim_ram_A512x18_B512x18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[8:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[8:0]" output="prim_ram_A512x18_B512x18[0].portaaddr[8:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[8:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portaaddr[8:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[8:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[8:0]" output="prim_ram_A512x18_B512x18[0].portbaddr[8:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[8:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portbaddr[8:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[17:0]" name="interconnect_split_ram_block_M9K_data_a_in_[17:0]" output="prim_ram_A512x18_B512x18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A512x18_B512x18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_9K_A512x18_B512x18_composite_prim_ram_1x(A512x18_B512x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{9}.port_b_address_width{9}" class="memory" name="prim_ram_A512x18_B512x18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="9" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="9" port_class="address2"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portbaddr"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A512x18_B512x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A512x18_B512x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A512x18_B512x18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A512x18_B512x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A512x18_B512x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A512x18_B512x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A512x18_B512x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A512x18_B512x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A512x18_B512x18[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A512x18_B512x18[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A512x18_B512x18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A512x18_B512x18[0].clk_portbin[0] prim_ram_A512x18_B512x18[0].clk_portain[0] prim_ram_A512x18_B512x18[0].clk_portaout[0] prim_ram_A512x18_B512x18[0].clk_portbout[0] "/>
              <complete input="prim_ram_A512x18_B512x18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[8:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[8:0]" output="prim_ram_A512x18_B512x18[0].portaaddr[8:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[8:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portaaddr[8:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[8:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[8:0]" output="prim_ram_A512x18_B512x18[0].portbaddr[8:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[8:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portbaddr[8:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[17:0]" name="interconnect_split_ram_block_M9K_data_a_in_[17:0]" output="prim_ram_A512x18_B512x18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A512x18_B512x18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_9K_A256x36_B256x36_composite_prim_ram_1x(A256x36_B256x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{8}.port_b_address_width{8}" class="memory" name="prim_ram_A256x36_B256x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="8" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="8" port_class="address2"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A256x36_B256x36.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A256x36_B256x36.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.portbaddr"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A256x36_B256x36.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A256x36_B256x36.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A256x36_B256x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A256x36_B256x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A256x36_B256x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A256x36_B256x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A256x36_B256x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A256x36_B256x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A256x36_B256x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A256x36_B256x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A256x36_B256x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A256x36_B256x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A256x36_B256x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A256x36_B256x36[0].clk_portbin[0] prim_ram_A256x36_B256x36[0].clk_portain[0] prim_ram_A256x36_B256x36[0].clk_portaout[0] prim_ram_A256x36_B256x36[0].clk_portbout[0] "/>
              <complete input="prim_ram_A256x36_B256x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[7:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[7:0]" output="prim_ram_A256x36_B256x36[0].portaaddr[7:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[7:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].portaaddr[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[7:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[7:0]" output="prim_ram_A256x36_B256x36[0].portbaddr[7:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[7:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].portbaddr[7:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_A256x36_B256x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A256x36_B256x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_9K_A256x36_B256x36_composite_prim_ram_1x(A256x36_B256x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{8}.port_b_address_width{8}" class="memory" name="prim_ram_A256x36_B256x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="8" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="8" port_class="address2"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x36_B256x36.portbaddr"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A256x36_B256x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A256x36_B256x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A256x36_B256x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A256x36_B256x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A256x36_B256x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A256x36_B256x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A256x36_B256x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A256x36_B256x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A256x36_B256x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A256x36_B256x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A256x36_B256x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A256x36_B256x36[0].clk_portbin[0] prim_ram_A256x36_B256x36[0].clk_portain[0] prim_ram_A256x36_B256x36[0].clk_portaout[0] prim_ram_A256x36_B256x36[0].clk_portbout[0] "/>
              <complete input="prim_ram_A256x36_B256x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[7:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[7:0]" output="prim_ram_A256x36_B256x36[0].portaaddr[7:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[7:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].portaaddr[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[7:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[7:0]" output="prim_ram_A256x36_B256x36[0].portbaddr[7:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[7:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].portbaddr[7:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_A256x36_B256x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x36_B256x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A256x36_B256x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_8K_A8Kx1_B8Kx1_composite_prim_ram_1x(A8Kx1_B8Kx1)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{13}.port_b_address_width{13}" class="memory" name="prim_ram_A8Kx1_B8Kx1" num_pb="1">
              <input name="portadatain" num_pins="1" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="13" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="13" port_class="address2"/>
              <output name="portbdataout" num_pins="1" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A8Kx1_B8Kx1.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A8Kx1_B8Kx1.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portbaddr"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A8Kx1_B8Kx1.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A8Kx1_B8Kx1.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A8Kx1_B8Kx1[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A8Kx1_B8Kx1[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A8Kx1_B8Kx1[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A8Kx1_B8Kx1[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A8Kx1_B8Kx1[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A8Kx1_B8Kx1[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A8Kx1_B8Kx1[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A8Kx1_B8Kx1[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A8Kx1_B8Kx1[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A8Kx1_B8Kx1[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A8Kx1_B8Kx1[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A8Kx1_B8Kx1[0].clk_portbin[0] prim_ram_A8Kx1_B8Kx1[0].clk_portain[0] prim_ram_A8Kx1_B8Kx1[0].clk_portaout[0] prim_ram_A8Kx1_B8Kx1[0].clk_portbout[0] "/>
              <complete input="prim_ram_A8Kx1_B8Kx1[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]" output="prim_ram_A8Kx1_B8Kx1[0].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portaaddr[12:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]" output="prim_ram_A8Kx1_B8Kx1[0].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portbaddr[12:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[0]" name="interconnect_split_ram_block_M9K_data_a_in_[0]" output="prim_ram_A8Kx1_B8Kx1[0].portadatain[0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portadatain[0]"/>
              </direct>
              <direct input="prim_ram_A8Kx1_B8Kx1[0].portbdataout[0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_8K_A8Kx1_B8Kx1_composite_prim_ram_1x(A8Kx1_B8Kx1)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{13}.port_b_address_width{13}" class="memory" name="prim_ram_A8Kx1_B8Kx1" num_pb="1">
              <input name="portadatain" num_pins="1" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="13" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="13" port_class="address2"/>
              <output name="portbdataout" num_pins="1" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portbaddr"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A8Kx1_B8Kx1[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A8Kx1_B8Kx1[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A8Kx1_B8Kx1[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A8Kx1_B8Kx1[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A8Kx1_B8Kx1[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A8Kx1_B8Kx1[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A8Kx1_B8Kx1[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A8Kx1_B8Kx1[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A8Kx1_B8Kx1[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A8Kx1_B8Kx1[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A8Kx1_B8Kx1[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A8Kx1_B8Kx1[0].clk_portbin[0] prim_ram_A8Kx1_B8Kx1[0].clk_portain[0] prim_ram_A8Kx1_B8Kx1[0].clk_portaout[0] prim_ram_A8Kx1_B8Kx1[0].clk_portbout[0] "/>
              <complete input="prim_ram_A8Kx1_B8Kx1[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]" output="prim_ram_A8Kx1_B8Kx1[0].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portaaddr[12:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]" output="prim_ram_A8Kx1_B8Kx1[0].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portbaddr[12:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[0]" name="interconnect_split_ram_block_M9K_data_a_in_[0]" output="prim_ram_A8Kx1_B8Kx1[0].portadatain[0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portadatain[0]"/>
              </direct>
              <direct input="prim_ram_A8Kx1_B8Kx1[0].portbdataout[0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_8K_A4Kx2_B4Kx2_composite_prim_ram_1x(A4Kx2_B4Kx2)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{12}.port_b_address_width{12}" class="memory" name="prim_ram_A4Kx2_B4Kx2" num_pb="1">
              <input name="portadatain" num_pins="2" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="12" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="12" port_class="address2"/>
              <output name="portbdataout" num_pins="2" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A4Kx2_B4Kx2.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A4Kx2_B4Kx2.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portbaddr"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A4Kx2_B4Kx2.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A4Kx2_B4Kx2.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A4Kx2_B4Kx2[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A4Kx2_B4Kx2[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A4Kx2_B4Kx2[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A4Kx2_B4Kx2[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A4Kx2_B4Kx2[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A4Kx2_B4Kx2[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A4Kx2_B4Kx2[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A4Kx2_B4Kx2[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A4Kx2_B4Kx2[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A4Kx2_B4Kx2[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A4Kx2_B4Kx2[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A4Kx2_B4Kx2[0].clk_portbin[0] prim_ram_A4Kx2_B4Kx2[0].clk_portain[0] prim_ram_A4Kx2_B4Kx2[0].clk_portaout[0] prim_ram_A4Kx2_B4Kx2[0].clk_portbout[0] "/>
              <complete input="prim_ram_A4Kx2_B4Kx2[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[11:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[11:0]" output="prim_ram_A4Kx2_B4Kx2[0].portaaddr[11:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[11:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portaaddr[11:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[11:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[11:0]" output="prim_ram_A4Kx2_B4Kx2[0].portbaddr[11:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[11:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portbaddr[11:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[1:0]" name="interconnect_split_ram_block_M9K_data_a_in_[1:0]" output="prim_ram_A4Kx2_B4Kx2[0].portadatain[1:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[1:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portadatain[1:0]"/>
              </direct>
              <direct input="prim_ram_A4Kx2_B4Kx2[0].portbdataout[1:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[1:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_8K_A4Kx2_B4Kx2_composite_prim_ram_1x(A4Kx2_B4Kx2)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{12}.port_b_address_width{12}" class="memory" name="prim_ram_A4Kx2_B4Kx2" num_pb="1">
              <input name="portadatain" num_pins="2" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="12" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="12" port_class="address2"/>
              <output name="portbdataout" num_pins="2" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portbaddr"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A4Kx2_B4Kx2[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A4Kx2_B4Kx2[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A4Kx2_B4Kx2[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A4Kx2_B4Kx2[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A4Kx2_B4Kx2[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A4Kx2_B4Kx2[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A4Kx2_B4Kx2[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A4Kx2_B4Kx2[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A4Kx2_B4Kx2[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A4Kx2_B4Kx2[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A4Kx2_B4Kx2[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A4Kx2_B4Kx2[0].clk_portbin[0] prim_ram_A4Kx2_B4Kx2[0].clk_portain[0] prim_ram_A4Kx2_B4Kx2[0].clk_portaout[0] prim_ram_A4Kx2_B4Kx2[0].clk_portbout[0] "/>
              <complete input="prim_ram_A4Kx2_B4Kx2[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[11:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[11:0]" output="prim_ram_A4Kx2_B4Kx2[0].portaaddr[11:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[11:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portaaddr[11:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[11:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[11:0]" output="prim_ram_A4Kx2_B4Kx2[0].portbaddr[11:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[11:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portbaddr[11:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[1:0]" name="interconnect_split_ram_block_M9K_data_a_in_[1:0]" output="prim_ram_A4Kx2_B4Kx2[0].portadatain[1:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[1:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portadatain[1:0]"/>
              </direct>
              <direct input="prim_ram_A4Kx2_B4Kx2[0].portbdataout[1:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[1:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_8K_A2Kx4_B2Kx4_composite_prim_ram_1x(A2Kx4_B2Kx4)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{11}.port_b_address_width{11}" class="memory" name="prim_ram_A2Kx4_B2Kx4" num_pb="1">
              <input name="portadatain" num_pins="4" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="11" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="11" port_class="address2"/>
              <output name="portbdataout" num_pins="4" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A2Kx4_B2Kx4.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A2Kx4_B2Kx4.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portbaddr"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A2Kx4_B2Kx4.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A2Kx4_B2Kx4.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A2Kx4_B2Kx4[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A2Kx4_B2Kx4[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A2Kx4_B2Kx4[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A2Kx4_B2Kx4[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A2Kx4_B2Kx4[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A2Kx4_B2Kx4[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A2Kx4_B2Kx4[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A2Kx4_B2Kx4[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A2Kx4_B2Kx4[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A2Kx4_B2Kx4[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A2Kx4_B2Kx4[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A2Kx4_B2Kx4[0].clk_portbin[0] prim_ram_A2Kx4_B2Kx4[0].clk_portain[0] prim_ram_A2Kx4_B2Kx4[0].clk_portaout[0] prim_ram_A2Kx4_B2Kx4[0].clk_portbout[0] "/>
              <complete input="prim_ram_A2Kx4_B2Kx4[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[10:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[10:0]" output="prim_ram_A2Kx4_B2Kx4[0].portaaddr[10:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[10:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portaaddr[10:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[10:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[10:0]" output="prim_ram_A2Kx4_B2Kx4[0].portbaddr[10:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[10:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portbaddr[10:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[3:0]" name="interconnect_split_ram_block_M9K_data_a_in_[3:0]" output="prim_ram_A2Kx4_B2Kx4[0].portadatain[3:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[3:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portadatain[3:0]"/>
              </direct>
              <direct input="prim_ram_A2Kx4_B2Kx4[0].portbdataout[3:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[3:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_8K_A2Kx4_B2Kx4_composite_prim_ram_1x(A2Kx4_B2Kx4)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{11}.port_b_address_width{11}" class="memory" name="prim_ram_A2Kx4_B2Kx4" num_pb="1">
              <input name="portadatain" num_pins="4" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="11" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="11" port_class="address2"/>
              <output name="portbdataout" num_pins="4" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portbaddr"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A2Kx4_B2Kx4[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A2Kx4_B2Kx4[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A2Kx4_B2Kx4[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A2Kx4_B2Kx4[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A2Kx4_B2Kx4[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A2Kx4_B2Kx4[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A2Kx4_B2Kx4[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A2Kx4_B2Kx4[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A2Kx4_B2Kx4[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A2Kx4_B2Kx4[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A2Kx4_B2Kx4[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A2Kx4_B2Kx4[0].clk_portbin[0] prim_ram_A2Kx4_B2Kx4[0].clk_portain[0] prim_ram_A2Kx4_B2Kx4[0].clk_portaout[0] prim_ram_A2Kx4_B2Kx4[0].clk_portbout[0] "/>
              <complete input="prim_ram_A2Kx4_B2Kx4[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[10:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[10:0]" output="prim_ram_A2Kx4_B2Kx4[0].portaaddr[10:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[10:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portaaddr[10:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[10:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[10:0]" output="prim_ram_A2Kx4_B2Kx4[0].portbaddr[10:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[10:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portbaddr[10:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[3:0]" name="interconnect_split_ram_block_M9K_data_a_in_[3:0]" output="prim_ram_A2Kx4_B2Kx4[0].portadatain[3:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[3:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portadatain[3:0]"/>
              </direct>
              <direct input="prim_ram_A2Kx4_B2Kx4[0].portbdataout[3:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[3:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_4K_A128x36_B128x36_composite_prim_ram_1x(A128x36_B128x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{7}.port_b_address_width{7}" class="memory" name="prim_ram_A128x36_B128x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="7" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="7" port_class="address2"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A128x36_B128x36.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A128x36_B128x36.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.portbaddr"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A128x36_B128x36.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A128x36_B128x36.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A128x36_B128x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A128x36_B128x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A128x36_B128x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A128x36_B128x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A128x36_B128x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A128x36_B128x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A128x36_B128x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A128x36_B128x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A128x36_B128x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A128x36_B128x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A128x36_B128x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A128x36_B128x36[0].clk_portbin[0] prim_ram_A128x36_B128x36[0].clk_portain[0] prim_ram_A128x36_B128x36[0].clk_portaout[0] prim_ram_A128x36_B128x36[0].clk_portbout[0] "/>
              <complete input="prim_ram_A128x36_B128x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[6:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[6:0]" output="prim_ram_A128x36_B128x36[0].portaaddr[6:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[6:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].portaaddr[6:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[6:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[6:0]" output="prim_ram_A128x36_B128x36[0].portbaddr[6:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[6:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].portbaddr[6:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_A128x36_B128x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A128x36_B128x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_4K_A128x36_B128x36_composite_prim_ram_1x(A128x36_B128x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{7}.port_b_address_width{7}" class="memory" name="prim_ram_A128x36_B128x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="7" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="7" port_class="address2"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x36_B128x36.portbaddr"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A128x36_B128x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A128x36_B128x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A128x36_B128x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A128x36_B128x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A128x36_B128x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A128x36_B128x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A128x36_B128x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A128x36_B128x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A128x36_B128x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A128x36_B128x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A128x36_B128x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A128x36_B128x36[0].clk_portbin[0] prim_ram_A128x36_B128x36[0].clk_portain[0] prim_ram_A128x36_B128x36[0].clk_portaout[0] prim_ram_A128x36_B128x36[0].clk_portbout[0] "/>
              <complete input="prim_ram_A128x36_B128x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[6:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[6:0]" output="prim_ram_A128x36_B128x36[0].portaaddr[6:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[6:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].portaaddr[6:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[6:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[6:0]" output="prim_ram_A128x36_B128x36[0].portbaddr[6:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[6:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].portbaddr[6:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_A128x36_B128x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x36_B128x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A128x36_B128x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_2K_A64x36_B64x36_composite_prim_ram_1x(A64x36_B64x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{6}.port_b_address_width{6}" class="memory" name="prim_ram_A64x36_B64x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="6" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="6" port_class="address2"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A64x36_B64x36.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A64x36_B64x36.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.portbaddr"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A64x36_B64x36.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A64x36_B64x36.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A64x36_B64x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A64x36_B64x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A64x36_B64x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A64x36_B64x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A64x36_B64x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A64x36_B64x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A64x36_B64x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A64x36_B64x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A64x36_B64x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A64x36_B64x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A64x36_B64x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A64x36_B64x36[0].clk_portbin[0] prim_ram_A64x36_B64x36[0].clk_portain[0] prim_ram_A64x36_B64x36[0].clk_portaout[0] prim_ram_A64x36_B64x36[0].clk_portbout[0] "/>
              <complete input="prim_ram_A64x36_B64x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[5:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[5:0]" output="prim_ram_A64x36_B64x36[0].portaaddr[5:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[5:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].portaaddr[5:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[5:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[5:0]" output="prim_ram_A64x36_B64x36[0].portbaddr[5:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[5:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].portbaddr[5:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_A64x36_B64x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A64x36_B64x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_2K_A64x36_B64x36_composite_prim_ram_1x(A64x36_B64x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{6}.port_b_address_width{6}" class="memory" name="prim_ram_A64x36_B64x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="6" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="6" port_class="address2"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x36_B64x36.portbaddr"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A64x36_B64x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A64x36_B64x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A64x36_B64x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A64x36_B64x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A64x36_B64x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A64x36_B64x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A64x36_B64x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A64x36_B64x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A64x36_B64x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A64x36_B64x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A64x36_B64x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A64x36_B64x36[0].clk_portbin[0] prim_ram_A64x36_B64x36[0].clk_portain[0] prim_ram_A64x36_B64x36[0].clk_portaout[0] prim_ram_A64x36_B64x36[0].clk_portbout[0] "/>
              <complete input="prim_ram_A64x36_B64x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[5:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[5:0]" output="prim_ram_A64x36_B64x36[0].portaaddr[5:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[5:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].portaaddr[5:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[5:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[5:0]" output="prim_ram_A64x36_B64x36[0].portbaddr[5:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[5:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].portbaddr[5:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_A64x36_B64x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x36_B64x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A64x36_B64x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_1K_A32x36_B32x36_composite_prim_ram_1x(A32x36_B32x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{5}.port_b_address_width{5}" class="memory" name="prim_ram_A32x36_B32x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="5" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="5" port_class="address2"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A32x36_B32x36.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A32x36_B32x36.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.portbaddr"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A32x36_B32x36.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A32x36_B32x36.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A32x36_B32x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A32x36_B32x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A32x36_B32x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A32x36_B32x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A32x36_B32x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A32x36_B32x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A32x36_B32x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A32x36_B32x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A32x36_B32x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A32x36_B32x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A32x36_B32x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A32x36_B32x36[0].clk_portbin[0] prim_ram_A32x36_B32x36[0].clk_portain[0] prim_ram_A32x36_B32x36[0].clk_portaout[0] prim_ram_A32x36_B32x36[0].clk_portbout[0] "/>
              <complete input="prim_ram_A32x36_B32x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[4:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[4:0]" output="prim_ram_A32x36_B32x36[0].portaaddr[4:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[4:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].portaaddr[4:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[4:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[4:0]" output="prim_ram_A32x36_B32x36[0].portbaddr[4:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[4:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].portbaddr[4:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_A32x36_B32x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A32x36_B32x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_1K_A32x36_B32x36_composite_prim_ram_1x(A32x36_B32x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{5}.port_b_address_width{5}" class="memory" name="prim_ram_A32x36_B32x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="5" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="5" port_class="address2"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x36_B32x36.portbaddr"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A32x36_B32x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A32x36_B32x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A32x36_B32x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A32x36_B32x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A32x36_B32x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A32x36_B32x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A32x36_B32x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A32x36_B32x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A32x36_B32x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A32x36_B32x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A32x36_B32x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A32x36_B32x36[0].clk_portbin[0] prim_ram_A32x36_B32x36[0].clk_portain[0] prim_ram_A32x36_B32x36[0].clk_portaout[0] prim_ram_A32x36_B32x36[0].clk_portbout[0] "/>
              <complete input="prim_ram_A32x36_B32x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[4:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[4:0]" output="prim_ram_A32x36_B32x36[0].portaaddr[4:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[4:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].portaaddr[4:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[4:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[4:0]" output="prim_ram_A32x36_B32x36[0].portbaddr[4:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[4:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].portbaddr[4:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_A32x36_B32x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x36_B32x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A32x36_B32x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_576_A16x36_B16x36_composite_prim_ram_1x(A16x36_B16x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{4}.port_b_address_width{4}" class="memory" name="prim_ram_A16x36_B16x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="4" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="4" port_class="address2"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A16x36_B16x36.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A16x36_B16x36.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.portbaddr"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A16x36_B16x36.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A16x36_B16x36.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A16x36_B16x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A16x36_B16x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A16x36_B16x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A16x36_B16x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A16x36_B16x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A16x36_B16x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A16x36_B16x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A16x36_B16x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A16x36_B16x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A16x36_B16x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A16x36_B16x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A16x36_B16x36[0].clk_portbin[0] prim_ram_A16x36_B16x36[0].clk_portain[0] prim_ram_A16x36_B16x36[0].clk_portaout[0] prim_ram_A16x36_B16x36[0].clk_portbout[0] "/>
              <complete input="prim_ram_A16x36_B16x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[3:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[3:0]" output="prim_ram_A16x36_B16x36[0].portaaddr[3:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[3:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].portaaddr[3:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[3:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[3:0]" output="prim_ram_A16x36_B16x36[0].portbaddr[3:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[3:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].portbaddr[3:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_A16x36_B16x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A16x36_B16x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_576_A16x36_B16x36_composite_prim_ram_1x(A16x36_B16x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{4}.port_b_address_width{4}" class="memory" name="prim_ram_A16x36_B16x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="4" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="4" port_class="address2"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x36_B16x36.portbaddr"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A16x36_B16x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A16x36_B16x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A16x36_B16x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A16x36_B16x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A16x36_B16x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A16x36_B16x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A16x36_B16x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A16x36_B16x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A16x36_B16x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A16x36_B16x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A16x36_B16x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A16x36_B16x36[0].clk_portbin[0] prim_ram_A16x36_B16x36[0].clk_portain[0] prim_ram_A16x36_B16x36[0].clk_portaout[0] prim_ram_A16x36_B16x36[0].clk_portbout[0] "/>
              <complete input="prim_ram_A16x36_B16x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[3:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[3:0]" output="prim_ram_A16x36_B16x36[0].portaaddr[3:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[3:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].portaaddr[3:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[3:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[3:0]" output="prim_ram_A16x36_B16x36[0].portbaddr[3:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[3:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].portbaddr[3:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_A16x36_B16x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x36_B16x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A16x36_B16x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_288_A8x36_B8x36_composite_prim_ram_1x(A8x36_B8x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{3}.port_b_address_width{3}" class="memory" name="prim_ram_A8x36_B8x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="3" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="3" port_class="address2"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A8x36_B8x36.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A8x36_B8x36.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.portbaddr"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A8x36_B8x36.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A8x36_B8x36.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A8x36_B8x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A8x36_B8x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A8x36_B8x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A8x36_B8x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A8x36_B8x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A8x36_B8x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A8x36_B8x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A8x36_B8x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A8x36_B8x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A8x36_B8x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A8x36_B8x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A8x36_B8x36[0].clk_portbin[0] prim_ram_A8x36_B8x36[0].clk_portain[0] prim_ram_A8x36_B8x36[0].clk_portaout[0] prim_ram_A8x36_B8x36[0].clk_portbout[0] "/>
              <complete input="prim_ram_A8x36_B8x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[2:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[2:0]" output="prim_ram_A8x36_B8x36[0].portaaddr[2:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[2:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].portaaddr[2:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[2:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[2:0]" output="prim_ram_A8x36_B8x36[0].portbaddr[2:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[2:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].portbaddr[2:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_A8x36_B8x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A8x36_B8x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_288_A8x36_B8x36_composite_prim_ram_1x(A8x36_B8x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{3}.port_b_address_width{3}" class="memory" name="prim_ram_A8x36_B8x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="3" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="3" port_class="address2"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x36_B8x36.portbaddr"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A8x36_B8x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A8x36_B8x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A8x36_B8x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A8x36_B8x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A8x36_B8x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A8x36_B8x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A8x36_B8x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A8x36_B8x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A8x36_B8x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A8x36_B8x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A8x36_B8x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A8x36_B8x36[0].clk_portbin[0] prim_ram_A8x36_B8x36[0].clk_portain[0] prim_ram_A8x36_B8x36[0].clk_portaout[0] prim_ram_A8x36_B8x36[0].clk_portbout[0] "/>
              <complete input="prim_ram_A8x36_B8x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[2:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[2:0]" output="prim_ram_A8x36_B8x36[0].portaaddr[2:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[2:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].portaaddr[2:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[2:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[2:0]" output="prim_ram_A8x36_B8x36[0].portbaddr[2:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[2:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].portbaddr[2:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_A8x36_B8x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x36_B8x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A8x36_B8x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_144_A4x36_B4x36_composite_prim_ram_1x(A4x36_B4x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{2}.port_b_address_width{2}" class="memory" name="prim_ram_A4x36_B4x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="2" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="2" port_class="address2"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A4x36_B4x36.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A4x36_B4x36.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.portbaddr"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A4x36_B4x36.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A4x36_B4x36.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A4x36_B4x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A4x36_B4x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A4x36_B4x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A4x36_B4x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A4x36_B4x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A4x36_B4x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A4x36_B4x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A4x36_B4x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A4x36_B4x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A4x36_B4x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A4x36_B4x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A4x36_B4x36[0].clk_portbin[0] prim_ram_A4x36_B4x36[0].clk_portain[0] prim_ram_A4x36_B4x36[0].clk_portaout[0] prim_ram_A4x36_B4x36[0].clk_portbout[0] "/>
              <complete input="prim_ram_A4x36_B4x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[1:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[1:0]" output="prim_ram_A4x36_B4x36[0].portaaddr[1:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[1:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].portaaddr[1:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[1:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[1:0]" output="prim_ram_A4x36_B4x36[0].portbaddr[1:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[1:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].portbaddr[1:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_A4x36_B4x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A4x36_B4x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_144_A4x36_B4x36_composite_prim_ram_1x(A4x36_B4x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{2}.port_b_address_width{2}" class="memory" name="prim_ram_A4x36_B4x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="2" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="2" port_class="address2"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x36_B4x36.portbaddr"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A4x36_B4x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A4x36_B4x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A4x36_B4x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A4x36_B4x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A4x36_B4x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A4x36_B4x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A4x36_B4x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A4x36_B4x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A4x36_B4x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A4x36_B4x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A4x36_B4x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A4x36_B4x36[0].clk_portbin[0] prim_ram_A4x36_B4x36[0].clk_portain[0] prim_ram_A4x36_B4x36[0].clk_portaout[0] prim_ram_A4x36_B4x36[0].clk_portbout[0] "/>
              <complete input="prim_ram_A4x36_B4x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[1:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[1:0]" output="prim_ram_A4x36_B4x36[0].portaaddr[1:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[1:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].portaaddr[1:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[1:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[1:0]" output="prim_ram_A4x36_B4x36[0].portbaddr[1:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[1:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].portbaddr[1:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_A4x36_B4x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x36_B4x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A4x36_B4x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_72_A2x36_B2x36_composite_prim_ram_1x(A2x36_B2x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{1}.port_b_address_width{1}" class="memory" name="prim_ram_A2x36_B2x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="1" port_class="address2"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A2x36_B2x36.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A2x36_B2x36.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.portbaddr"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A2x36_B2x36.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A2x36_B2x36.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A2x36_B2x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A2x36_B2x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A2x36_B2x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A2x36_B2x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A2x36_B2x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A2x36_B2x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A2x36_B2x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A2x36_B2x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A2x36_B2x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A2x36_B2x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A2x36_B2x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A2x36_B2x36[0].clk_portbin[0] prim_ram_A2x36_B2x36[0].clk_portain[0] prim_ram_A2x36_B2x36[0].clk_portaout[0] prim_ram_A2x36_B2x36[0].clk_portbout[0] "/>
              <complete input="prim_ram_A2x36_B2x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[0]" name="interconnect_common_ram_block_M9K_addr_a_in_[0]" output="prim_ram_A2x36_B2x36[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].portaaddr[0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[0]" name="interconnect_common_ram_block_M9K_addr_b_in_[0]" output="prim_ram_A2x36_B2x36[0].portbaddr[0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].portbaddr[0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_A2x36_B2x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A2x36_B2x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_72_A2x36_B2x36_composite_prim_ram_1x(A2x36_B2x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{1}.port_b_address_width{1}" class="memory" name="prim_ram_A2x36_B2x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="1" port_class="address2"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x36_B2x36.portbaddr"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A2x36_B2x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A2x36_B2x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A2x36_B2x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A2x36_B2x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A2x36_B2x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A2x36_B2x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A2x36_B2x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A2x36_B2x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A2x36_B2x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A2x36_B2x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A2x36_B2x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A2x36_B2x36[0].clk_portbin[0] prim_ram_A2x36_B2x36[0].clk_portain[0] prim_ram_A2x36_B2x36[0].clk_portaout[0] prim_ram_A2x36_B2x36[0].clk_portbout[0] "/>
              <complete input="prim_ram_A2x36_B2x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[0]" name="interconnect_common_ram_block_M9K_addr_a_in_[0]" output="prim_ram_A2x36_B2x36[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].portaaddr[0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[0]" name="interconnect_common_ram_block_M9K_addr_b_in_[0]" output="prim_ram_A2x36_B2x36[0].portbaddr[0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].portbaddr[0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_A2x36_B2x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x36_B2x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A2x36_B2x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_36_A1x36_B1x36_composite_prim_ram_1x(A1x36_B1x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{0}.port_b_address_width{0}" class="memory" name="prim_ram_A1x36_B1x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="1" port_class="address2"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A1x36_B1x36.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A1x36_B1x36.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.portbaddr"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A1x36_B1x36.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A1x36_B1x36.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A1x36_B1x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A1x36_B1x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A1x36_B1x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A1x36_B1x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A1x36_B1x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A1x36_B1x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A1x36_B1x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A1x36_B1x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A1x36_B1x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A1x36_B1x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A1x36_B1x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A1x36_B1x36[0].clk_portbin[0] prim_ram_A1x36_B1x36[0].clk_portain[0] prim_ram_A1x36_B1x36[0].clk_portaout[0] prim_ram_A1x36_B1x36[0].clk_portbout[0] "/>
              <complete input="prim_ram_A1x36_B1x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[0]" name="interconnect_common_ram_block_M9K_addr_a_in_[0]" output="prim_ram_A1x36_B1x36[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].portaaddr[0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[0]" name="interconnect_common_ram_block_M9K_addr_b_in_[0]" output="prim_ram_A1x36_B1x36[0].portbaddr[0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].portbaddr[0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_A1x36_B1x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A1x36_B1x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_36_A1x36_B1x36_composite_prim_ram_1x(A1x36_B1x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{0}.port_b_address_width{0}" class="memory" name="prim_ram_A1x36_B1x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="1" port_class="address2"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x36_B1x36.portbaddr"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A1x36_B1x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A1x36_B1x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]" output="prim_ram_A1x36_B1x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_A1x36_B1x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_A1x36_B1x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_A1x36_B1x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A1x36_B1x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A1x36_B1x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A1x36_B1x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A1x36_B1x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A1x36_B1x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A1x36_B1x36[0].clk_portbin[0] prim_ram_A1x36_B1x36[0].clk_portain[0] prim_ram_A1x36_B1x36[0].clk_portaout[0] prim_ram_A1x36_B1x36[0].clk_portbout[0] "/>
              <complete input="prim_ram_A1x36_B1x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[0]" name="interconnect_common_ram_block_M9K_addr_a_in_[0]" output="prim_ram_A1x36_B1x36[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].portaaddr[0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[0]" name="interconnect_common_ram_block_M9K_addr_b_in_[0]" output="prim_ram_A1x36_B1x36[0].portbaddr[0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].portbaddr[0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_A1x36_B1x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x36_B1x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A1x36_B1x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_9K_A1Kx9_B1Kx9_composite_prim_ram_1x(A1Kx9_B1Kx9)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{10}.port_b_address_width{10}" class="memory" name="prim_ram_A1Kx9_B1Kx9" num_pb="1">
              <input name="portadatain" num_pins="9" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="10" port_class="address1"/>
              <input name="portbaddr" num_pins="10" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="9" port_class="data_in2"/>
              <output name="portadataout" num_pins="9" port_class="data_out1"/>
              <output name="portbdataout" num_pins="9" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A1Kx9_B1Kx9.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A1Kx9_B1Kx9.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A1Kx9_B1Kx9.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portbdatain"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_A1Kx9_B1Kx9.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A1Kx9_B1Kx9.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A1Kx9_B1Kx9.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A1Kx9_B1Kx9[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A1Kx9_B1Kx9[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A1Kx9_B1Kx9[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A1Kx9_B1Kx9[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A1Kx9_B1Kx9[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A1Kx9_B1Kx9[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A1Kx9_B1Kx9[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A1Kx9_B1Kx9[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A1Kx9_B1Kx9[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A1Kx9_B1Kx9[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A1Kx9_B1Kx9[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A1Kx9_B1Kx9[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A1Kx9_B1Kx9[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A1Kx9_B1Kx9[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A1Kx9_B1Kx9[0].clk_portbout[0] prim_ram_A1Kx9_B1Kx9[0].clk_portbin[0] prim_ram_A1Kx9_B1Kx9[0].clk_portain[0] prim_ram_A1Kx9_B1Kx9[0].clk_portaout[0] "/>
              <complete input="prim_ram_A1Kx9_B1Kx9[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[9:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[9:0]" output="prim_ram_A1Kx9_B1Kx9[0].portaaddr[9:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[9:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portaaddr[9:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[9:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[9:0]" output="prim_ram_A1Kx9_B1Kx9[0].portbaddr[9:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[9:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portbaddr[9:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[8:0]" name="interconnect_split_ram_block_M9K_data_b_in_[8:0]" output="prim_ram_A1Kx9_B1Kx9[0].portbdatain[8:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[8:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portbdatain[8:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[8:0]" name="interconnect_split_ram_block_M9K_data_a_in_[8:0]" output="prim_ram_A1Kx9_B1Kx9[0].portadatain[8:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[8:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portadatain[8:0]"/>
              </direct>
              <direct input="prim_ram_A1Kx9_B1Kx9[0].portadataout[8:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[8:0]"/>
              <direct input="prim_ram_A1Kx9_B1Kx9[0].portbdataout[8:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[17:9]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_9K_A1Kx9_B1Kx9_composite_prim_ram_1x(A1Kx9_B1Kx9)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{10}.port_b_address_width{10}" class="memory" name="prim_ram_A1Kx9_B1Kx9" num_pb="1">
              <input name="portadatain" num_pins="9" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="10" port_class="address1"/>
              <input name="portbaddr" num_pins="10" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="9" port_class="data_in2"/>
              <output name="portadataout" num_pins="9" port_class="data_out1"/>
              <output name="portbdataout" num_pins="9" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1Kx9_B1Kx9.portbdatain"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx9_B1Kx9.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1Kx9_B1Kx9.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx9_B1Kx9.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx9_B1Kx9.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A1Kx9_B1Kx9[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A1Kx9_B1Kx9[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A1Kx9_B1Kx9[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A1Kx9_B1Kx9[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A1Kx9_B1Kx9[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A1Kx9_B1Kx9[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A1Kx9_B1Kx9[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A1Kx9_B1Kx9[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A1Kx9_B1Kx9[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A1Kx9_B1Kx9[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A1Kx9_B1Kx9[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A1Kx9_B1Kx9[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A1Kx9_B1Kx9[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A1Kx9_B1Kx9[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A1Kx9_B1Kx9[0].clk_portbout[0] prim_ram_A1Kx9_B1Kx9[0].clk_portbin[0] prim_ram_A1Kx9_B1Kx9[0].clk_portain[0] prim_ram_A1Kx9_B1Kx9[0].clk_portaout[0] "/>
              <complete input="prim_ram_A1Kx9_B1Kx9[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[9:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[9:0]" output="prim_ram_A1Kx9_B1Kx9[0].portaaddr[9:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[9:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portaaddr[9:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[9:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[9:0]" output="prim_ram_A1Kx9_B1Kx9[0].portbaddr[9:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[9:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portbaddr[9:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[8:0]" name="interconnect_split_ram_block_M9K_data_b_in_[8:0]" output="prim_ram_A1Kx9_B1Kx9[0].portbdatain[8:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[8:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portbdatain[8:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[8:0]" name="interconnect_split_ram_block_M9K_data_a_in_[8:0]" output="prim_ram_A1Kx9_B1Kx9[0].portadatain[8:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[8:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1Kx9_B1Kx9[0].portadatain[8:0]"/>
              </direct>
              <direct input="prim_ram_A1Kx9_B1Kx9[0].portadataout[8:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[8:0]"/>
              <direct input="prim_ram_A1Kx9_B1Kx9[0].portbdataout[8:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[17:9]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_9K_A512x18_B512x18_composite_prim_ram_1x(A512x18_B512x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{9}.port_b_address_width{9}" class="memory" name="prim_ram_A512x18_B512x18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="9" port_class="address1"/>
              <input name="portbaddr" num_pins="9" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="18" port_class="data_in2"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A512x18_B512x18.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A512x18_B512x18.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A512x18_B512x18.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portbdatain"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_A512x18_B512x18.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A512x18_B512x18.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A512x18_B512x18.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A512x18_B512x18[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A512x18_B512x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A512x18_B512x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A512x18_B512x18[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A512x18_B512x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A512x18_B512x18[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A512x18_B512x18[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A512x18_B512x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A512x18_B512x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A512x18_B512x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A512x18_B512x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A512x18_B512x18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A512x18_B512x18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A512x18_B512x18[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A512x18_B512x18[0].clk_portbout[0] prim_ram_A512x18_B512x18[0].clk_portbin[0] prim_ram_A512x18_B512x18[0].clk_portain[0] prim_ram_A512x18_B512x18[0].clk_portaout[0] "/>
              <complete input="prim_ram_A512x18_B512x18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[8:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[8:0]" output="prim_ram_A512x18_B512x18[0].portaaddr[8:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[8:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portaaddr[8:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[8:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[8:0]" output="prim_ram_A512x18_B512x18[0].portbaddr[8:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[8:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portbaddr[8:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[17:0]" name="interconnect_split_ram_block_M9K_data_b_in_[17:0]" output="prim_ram_A512x18_B512x18[0].portbdatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portbdatain[17:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[17:0]" name="interconnect_split_ram_block_M9K_data_a_in_[17:0]" output="prim_ram_A512x18_B512x18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A512x18_B512x18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
              <direct input="prim_ram_A512x18_B512x18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[35:18]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_9K_A512x18_B512x18_composite_prim_ram_1x(A512x18_B512x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{9}.port_b_address_width{9}" class="memory" name="prim_ram_A512x18_B512x18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="9" port_class="address1"/>
              <input name="portbaddr" num_pins="9" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="18" port_class="data_in2"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x18_B512x18.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A512x18_B512x18.portbdatain"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portadataout"/>
              <delay_constant in_port="prim_ram_A512x18_B512x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A512x18_B512x18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x18_B512x18.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x18_B512x18.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A512x18_B512x18[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A512x18_B512x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A512x18_B512x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A512x18_B512x18[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A512x18_B512x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A512x18_B512x18[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A512x18_B512x18[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A512x18_B512x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A512x18_B512x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A512x18_B512x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A512x18_B512x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A512x18_B512x18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A512x18_B512x18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A512x18_B512x18[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A512x18_B512x18[0].clk_portbout[0] prim_ram_A512x18_B512x18[0].clk_portbin[0] prim_ram_A512x18_B512x18[0].clk_portain[0] prim_ram_A512x18_B512x18[0].clk_portaout[0] "/>
              <complete input="prim_ram_A512x18_B512x18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[8:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[8:0]" output="prim_ram_A512x18_B512x18[0].portaaddr[8:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[8:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portaaddr[8:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[8:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[8:0]" output="prim_ram_A512x18_B512x18[0].portbaddr[8:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[8:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portbaddr[8:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[17:0]" name="interconnect_split_ram_block_M9K_data_b_in_[17:0]" output="prim_ram_A512x18_B512x18[0].portbdatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portbdatain[17:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[17:0]" name="interconnect_split_ram_block_M9K_data_a_in_[17:0]" output="prim_ram_A512x18_B512x18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A512x18_B512x18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A512x18_B512x18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
              <direct input="prim_ram_A512x18_B512x18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[35:18]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_8K_A8Kx1_B8Kx1_composite_prim_ram_1x(A8Kx1_B8Kx1)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{13}.port_b_address_width{13}" class="memory" name="prim_ram_A8Kx1_B8Kx1" num_pb="1">
              <input name="portadatain" num_pins="1" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="13" port_class="address1"/>
              <input name="portbaddr" num_pins="13" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="1" port_class="data_in2"/>
              <output name="portadataout" num_pins="1" port_class="data_out1"/>
              <output name="portbdataout" num_pins="1" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A8Kx1_B8Kx1.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A8Kx1_B8Kx1.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A8Kx1_B8Kx1.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portbdatain"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_A8Kx1_B8Kx1.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A8Kx1_B8Kx1.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A8Kx1_B8Kx1.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A8Kx1_B8Kx1[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A8Kx1_B8Kx1[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A8Kx1_B8Kx1[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A8Kx1_B8Kx1[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A8Kx1_B8Kx1[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A8Kx1_B8Kx1[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A8Kx1_B8Kx1[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A8Kx1_B8Kx1[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A8Kx1_B8Kx1[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A8Kx1_B8Kx1[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A8Kx1_B8Kx1[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A8Kx1_B8Kx1[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A8Kx1_B8Kx1[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A8Kx1_B8Kx1[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A8Kx1_B8Kx1[0].clk_portbout[0] prim_ram_A8Kx1_B8Kx1[0].clk_portbin[0] prim_ram_A8Kx1_B8Kx1[0].clk_portain[0] prim_ram_A8Kx1_B8Kx1[0].clk_portaout[0] "/>
              <complete input="prim_ram_A8Kx1_B8Kx1[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]" output="prim_ram_A8Kx1_B8Kx1[0].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portaaddr[12:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]" output="prim_ram_A8Kx1_B8Kx1[0].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portbaddr[12:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[0]" name="interconnect_split_ram_block_M9K_data_b_in_[0]" output="prim_ram_A8Kx1_B8Kx1[0].portbdatain[0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portbdatain[0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[0]" name="interconnect_split_ram_block_M9K_data_a_in_[0]" output="prim_ram_A8Kx1_B8Kx1[0].portadatain[0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portadatain[0]"/>
              </direct>
              <direct input="prim_ram_A8Kx1_B8Kx1[0].portadataout[0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[0]"/>
              <direct input="prim_ram_A8Kx1_B8Kx1[0].portbdataout[0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[1]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_8K_A8Kx1_B8Kx1_composite_prim_ram_1x(A8Kx1_B8Kx1)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{13}.port_b_address_width{13}" class="memory" name="prim_ram_A8Kx1_B8Kx1" num_pb="1">
              <input name="portadatain" num_pins="1" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="13" port_class="address1"/>
              <input name="portbaddr" num_pins="13" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="1" port_class="data_in2"/>
              <output name="portadataout" num_pins="1" port_class="data_out1"/>
              <output name="portbdataout" num_pins="1" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8Kx1_B8Kx1.portbdatain"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx1_B8Kx1.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8Kx1_B8Kx1.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx1_B8Kx1.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx1_B8Kx1.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A8Kx1_B8Kx1[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A8Kx1_B8Kx1[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A8Kx1_B8Kx1[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A8Kx1_B8Kx1[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A8Kx1_B8Kx1[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A8Kx1_B8Kx1[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A8Kx1_B8Kx1[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A8Kx1_B8Kx1[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A8Kx1_B8Kx1[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A8Kx1_B8Kx1[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A8Kx1_B8Kx1[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A8Kx1_B8Kx1[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A8Kx1_B8Kx1[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A8Kx1_B8Kx1[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A8Kx1_B8Kx1[0].clk_portbout[0] prim_ram_A8Kx1_B8Kx1[0].clk_portbin[0] prim_ram_A8Kx1_B8Kx1[0].clk_portain[0] prim_ram_A8Kx1_B8Kx1[0].clk_portaout[0] "/>
              <complete input="prim_ram_A8Kx1_B8Kx1[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]" output="prim_ram_A8Kx1_B8Kx1[0].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portaaddr[12:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]" output="prim_ram_A8Kx1_B8Kx1[0].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portbaddr[12:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[0]" name="interconnect_split_ram_block_M9K_data_b_in_[0]" output="prim_ram_A8Kx1_B8Kx1[0].portbdatain[0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portbdatain[0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[0]" name="interconnect_split_ram_block_M9K_data_a_in_[0]" output="prim_ram_A8Kx1_B8Kx1[0].portadatain[0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8Kx1_B8Kx1[0].portadatain[0]"/>
              </direct>
              <direct input="prim_ram_A8Kx1_B8Kx1[0].portadataout[0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[0]"/>
              <direct input="prim_ram_A8Kx1_B8Kx1[0].portbdataout[0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[1]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_8K_A4Kx2_B4Kx2_composite_prim_ram_1x(A4Kx2_B4Kx2)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{12}.port_b_address_width{12}" class="memory" name="prim_ram_A4Kx2_B4Kx2" num_pb="1">
              <input name="portadatain" num_pins="2" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="12" port_class="address1"/>
              <input name="portbaddr" num_pins="12" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="2" port_class="data_in2"/>
              <output name="portadataout" num_pins="2" port_class="data_out1"/>
              <output name="portbdataout" num_pins="2" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A4Kx2_B4Kx2.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A4Kx2_B4Kx2.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A4Kx2_B4Kx2.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portbdatain"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_A4Kx2_B4Kx2.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A4Kx2_B4Kx2.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A4Kx2_B4Kx2.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A4Kx2_B4Kx2[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A4Kx2_B4Kx2[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A4Kx2_B4Kx2[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A4Kx2_B4Kx2[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A4Kx2_B4Kx2[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A4Kx2_B4Kx2[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A4Kx2_B4Kx2[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A4Kx2_B4Kx2[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A4Kx2_B4Kx2[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A4Kx2_B4Kx2[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A4Kx2_B4Kx2[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A4Kx2_B4Kx2[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A4Kx2_B4Kx2[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A4Kx2_B4Kx2[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A4Kx2_B4Kx2[0].clk_portbout[0] prim_ram_A4Kx2_B4Kx2[0].clk_portbin[0] prim_ram_A4Kx2_B4Kx2[0].clk_portain[0] prim_ram_A4Kx2_B4Kx2[0].clk_portaout[0] "/>
              <complete input="prim_ram_A4Kx2_B4Kx2[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[11:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[11:0]" output="prim_ram_A4Kx2_B4Kx2[0].portaaddr[11:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[11:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portaaddr[11:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[11:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[11:0]" output="prim_ram_A4Kx2_B4Kx2[0].portbaddr[11:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[11:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portbaddr[11:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[1:0]" name="interconnect_split_ram_block_M9K_data_b_in_[1:0]" output="prim_ram_A4Kx2_B4Kx2[0].portbdatain[1:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[1:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portbdatain[1:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[1:0]" name="interconnect_split_ram_block_M9K_data_a_in_[1:0]" output="prim_ram_A4Kx2_B4Kx2[0].portadatain[1:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[1:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portadatain[1:0]"/>
              </direct>
              <direct input="prim_ram_A4Kx2_B4Kx2[0].portadataout[1:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[1:0]"/>
              <direct input="prim_ram_A4Kx2_B4Kx2[0].portbdataout[1:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[3:2]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_8K_A4Kx2_B4Kx2_composite_prim_ram_1x(A4Kx2_B4Kx2)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{12}.port_b_address_width{12}" class="memory" name="prim_ram_A4Kx2_B4Kx2" num_pb="1">
              <input name="portadatain" num_pins="2" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="12" port_class="address1"/>
              <input name="portbaddr" num_pins="12" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="2" port_class="data_in2"/>
              <output name="portadataout" num_pins="2" port_class="data_out1"/>
              <output name="portbdataout" num_pins="2" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4Kx2_B4Kx2.portbdatain"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx2_B4Kx2.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4Kx2_B4Kx2.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx2_B4Kx2.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx2_B4Kx2.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A4Kx2_B4Kx2[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A4Kx2_B4Kx2[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A4Kx2_B4Kx2[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A4Kx2_B4Kx2[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A4Kx2_B4Kx2[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A4Kx2_B4Kx2[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A4Kx2_B4Kx2[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A4Kx2_B4Kx2[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A4Kx2_B4Kx2[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A4Kx2_B4Kx2[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A4Kx2_B4Kx2[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A4Kx2_B4Kx2[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A4Kx2_B4Kx2[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A4Kx2_B4Kx2[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A4Kx2_B4Kx2[0].clk_portbout[0] prim_ram_A4Kx2_B4Kx2[0].clk_portbin[0] prim_ram_A4Kx2_B4Kx2[0].clk_portain[0] prim_ram_A4Kx2_B4Kx2[0].clk_portaout[0] "/>
              <complete input="prim_ram_A4Kx2_B4Kx2[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[11:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[11:0]" output="prim_ram_A4Kx2_B4Kx2[0].portaaddr[11:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[11:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portaaddr[11:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[11:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[11:0]" output="prim_ram_A4Kx2_B4Kx2[0].portbaddr[11:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[11:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portbaddr[11:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[1:0]" name="interconnect_split_ram_block_M9K_data_b_in_[1:0]" output="prim_ram_A4Kx2_B4Kx2[0].portbdatain[1:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[1:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portbdatain[1:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[1:0]" name="interconnect_split_ram_block_M9K_data_a_in_[1:0]" output="prim_ram_A4Kx2_B4Kx2[0].portadatain[1:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[1:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4Kx2_B4Kx2[0].portadatain[1:0]"/>
              </direct>
              <direct input="prim_ram_A4Kx2_B4Kx2[0].portadataout[1:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[1:0]"/>
              <direct input="prim_ram_A4Kx2_B4Kx2[0].portbdataout[1:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[3:2]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_8K_A2Kx4_B2Kx4_composite_prim_ram_1x(A2Kx4_B2Kx4)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{11}.port_b_address_width{11}" class="memory" name="prim_ram_A2Kx4_B2Kx4" num_pb="1">
              <input name="portadatain" num_pins="4" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="11" port_class="address1"/>
              <input name="portbaddr" num_pins="11" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="4" port_class="data_in2"/>
              <output name="portadataout" num_pins="4" port_class="data_out1"/>
              <output name="portbdataout" num_pins="4" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A2Kx4_B2Kx4.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A2Kx4_B2Kx4.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A2Kx4_B2Kx4.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portbdatain"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_A2Kx4_B2Kx4.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A2Kx4_B2Kx4.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A2Kx4_B2Kx4.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A2Kx4_B2Kx4[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A2Kx4_B2Kx4[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A2Kx4_B2Kx4[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A2Kx4_B2Kx4[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A2Kx4_B2Kx4[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A2Kx4_B2Kx4[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A2Kx4_B2Kx4[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A2Kx4_B2Kx4[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A2Kx4_B2Kx4[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A2Kx4_B2Kx4[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A2Kx4_B2Kx4[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A2Kx4_B2Kx4[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A2Kx4_B2Kx4[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A2Kx4_B2Kx4[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A2Kx4_B2Kx4[0].clk_portbout[0] prim_ram_A2Kx4_B2Kx4[0].clk_portbin[0] prim_ram_A2Kx4_B2Kx4[0].clk_portain[0] prim_ram_A2Kx4_B2Kx4[0].clk_portaout[0] "/>
              <complete input="prim_ram_A2Kx4_B2Kx4[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[10:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[10:0]" output="prim_ram_A2Kx4_B2Kx4[0].portaaddr[10:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[10:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portaaddr[10:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[10:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[10:0]" output="prim_ram_A2Kx4_B2Kx4[0].portbaddr[10:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[10:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portbaddr[10:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[3:0]" name="interconnect_split_ram_block_M9K_data_b_in_[3:0]" output="prim_ram_A2Kx4_B2Kx4[0].portbdatain[3:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[3:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portbdatain[3:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[3:0]" name="interconnect_split_ram_block_M9K_data_a_in_[3:0]" output="prim_ram_A2Kx4_B2Kx4[0].portadatain[3:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[3:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portadatain[3:0]"/>
              </direct>
              <direct input="prim_ram_A2Kx4_B2Kx4[0].portadataout[3:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[3:0]"/>
              <direct input="prim_ram_A2Kx4_B2Kx4[0].portbdataout[3:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[7:4]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_8K_A2Kx4_B2Kx4_composite_prim_ram_1x(A2Kx4_B2Kx4)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{11}.port_b_address_width{11}" class="memory" name="prim_ram_A2Kx4_B2Kx4" num_pb="1">
              <input name="portadatain" num_pins="4" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="11" port_class="address1"/>
              <input name="portbaddr" num_pins="11" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="4" port_class="data_in2"/>
              <output name="portadataout" num_pins="4" port_class="data_out1"/>
              <output name="portbdataout" num_pins="4" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2Kx4_B2Kx4.portbdatain"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx4_B2Kx4.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2Kx4_B2Kx4.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx4_B2Kx4.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx4_B2Kx4.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A2Kx4_B2Kx4[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A2Kx4_B2Kx4[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A2Kx4_B2Kx4[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A2Kx4_B2Kx4[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A2Kx4_B2Kx4[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A2Kx4_B2Kx4[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A2Kx4_B2Kx4[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A2Kx4_B2Kx4[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A2Kx4_B2Kx4[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A2Kx4_B2Kx4[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A2Kx4_B2Kx4[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A2Kx4_B2Kx4[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A2Kx4_B2Kx4[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A2Kx4_B2Kx4[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A2Kx4_B2Kx4[0].clk_portbout[0] prim_ram_A2Kx4_B2Kx4[0].clk_portbin[0] prim_ram_A2Kx4_B2Kx4[0].clk_portain[0] prim_ram_A2Kx4_B2Kx4[0].clk_portaout[0] "/>
              <complete input="prim_ram_A2Kx4_B2Kx4[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[10:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[10:0]" output="prim_ram_A2Kx4_B2Kx4[0].portaaddr[10:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[10:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portaaddr[10:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[10:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[10:0]" output="prim_ram_A2Kx4_B2Kx4[0].portbaddr[10:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[10:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portbaddr[10:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[3:0]" name="interconnect_split_ram_block_M9K_data_b_in_[3:0]" output="prim_ram_A2Kx4_B2Kx4[0].portbdatain[3:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[3:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portbdatain[3:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[3:0]" name="interconnect_split_ram_block_M9K_data_a_in_[3:0]" output="prim_ram_A2Kx4_B2Kx4[0].portadatain[3:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[3:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2Kx4_B2Kx4[0].portadatain[3:0]"/>
              </direct>
              <direct input="prim_ram_A2Kx4_B2Kx4[0].portadataout[3:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[3:0]"/>
              <direct input="prim_ram_A2Kx4_B2Kx4[0].portbdataout[3:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[7:4]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_4K_A256x18_B256x18_composite_prim_ram_1x(A256x18_B256x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{8}.port_b_address_width{8}" class="memory" name="prim_ram_A256x18_B256x18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="8" port_class="address1"/>
              <input name="portbaddr" num_pins="8" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="18" port_class="data_in2"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x18_B256x18.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x18_B256x18.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A256x18_B256x18.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x18_B256x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x18_B256x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x18_B256x18.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x18_B256x18.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x18_B256x18.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x18_B256x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x18_B256x18.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x18_B256x18.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A256x18_B256x18.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x18_B256x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x18_B256x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x18_B256x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x18_B256x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x18_B256x18.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x18_B256x18.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A256x18_B256x18.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x18_B256x18.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x18_B256x18.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portbdatain"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x18_B256x18.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x18_B256x18.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_A256x18_B256x18.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x18_B256x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x18_B256x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x18_B256x18.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x18_B256x18.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x18_B256x18.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x18_B256x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x18_B256x18.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x18_B256x18.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A256x18_B256x18.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x18_B256x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x18_B256x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x18_B256x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x18_B256x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x18_B256x18.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x18_B256x18.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A256x18_B256x18.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x18_B256x18.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x18_B256x18.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A256x18_B256x18[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A256x18_B256x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A256x18_B256x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A256x18_B256x18[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A256x18_B256x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A256x18_B256x18[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A256x18_B256x18[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A256x18_B256x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A256x18_B256x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A256x18_B256x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A256x18_B256x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A256x18_B256x18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A256x18_B256x18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A256x18_B256x18[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A256x18_B256x18[0].clk_portbout[0] prim_ram_A256x18_B256x18[0].clk_portbin[0] prim_ram_A256x18_B256x18[0].clk_portain[0] prim_ram_A256x18_B256x18[0].clk_portaout[0] "/>
              <complete input="prim_ram_A256x18_B256x18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[7:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[7:0]" output="prim_ram_A256x18_B256x18[0].portaaddr[7:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[7:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].portaaddr[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[7:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[7:0]" output="prim_ram_A256x18_B256x18[0].portbaddr[7:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[7:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].portbaddr[7:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[17:0]" name="interconnect_split_ram_block_M9K_data_b_in_[17:0]" output="prim_ram_A256x18_B256x18[0].portbdatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].portbdatain[17:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[17:0]" name="interconnect_split_ram_block_M9K_data_a_in_[17:0]" output="prim_ram_A256x18_B256x18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A256x18_B256x18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
              <direct input="prim_ram_A256x18_B256x18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[35:18]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_4K_A256x18_B256x18_composite_prim_ram_1x(A256x18_B256x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{8}.port_b_address_width{8}" class="memory" name="prim_ram_A256x18_B256x18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="8" port_class="address1"/>
              <input name="portbaddr" num_pins="8" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="18" port_class="data_in2"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x18_B256x18.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x18_B256x18.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x18_B256x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x18_B256x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x18_B256x18.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x18_B256x18.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x18_B256x18.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x18_B256x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x18_B256x18.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x18_B256x18.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x18_B256x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x18_B256x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x18_B256x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x18_B256x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x18_B256x18.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x18_B256x18.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x18_B256x18.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x18_B256x18.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A256x18_B256x18.portbdatain"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portadataout"/>
              <delay_constant in_port="prim_ram_A256x18_B256x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A256x18_B256x18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x18_B256x18.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x18_B256x18.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x18_B256x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x18_B256x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x18_B256x18.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x18_B256x18.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x18_B256x18.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x18_B256x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x18_B256x18.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x18_B256x18.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x18_B256x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x18_B256x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x18_B256x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x18_B256x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x18_B256x18.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x18_B256x18.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x18_B256x18.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x18_B256x18.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A256x18_B256x18[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A256x18_B256x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A256x18_B256x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A256x18_B256x18[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A256x18_B256x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A256x18_B256x18[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A256x18_B256x18[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A256x18_B256x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A256x18_B256x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A256x18_B256x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A256x18_B256x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A256x18_B256x18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A256x18_B256x18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A256x18_B256x18[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A256x18_B256x18[0].clk_portbout[0] prim_ram_A256x18_B256x18[0].clk_portbin[0] prim_ram_A256x18_B256x18[0].clk_portain[0] prim_ram_A256x18_B256x18[0].clk_portaout[0] "/>
              <complete input="prim_ram_A256x18_B256x18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[7:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[7:0]" output="prim_ram_A256x18_B256x18[0].portaaddr[7:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[7:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].portaaddr[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[7:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[7:0]" output="prim_ram_A256x18_B256x18[0].portbaddr[7:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[7:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].portbaddr[7:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[17:0]" name="interconnect_split_ram_block_M9K_data_b_in_[17:0]" output="prim_ram_A256x18_B256x18[0].portbdatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].portbdatain[17:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[17:0]" name="interconnect_split_ram_block_M9K_data_a_in_[17:0]" output="prim_ram_A256x18_B256x18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A256x18_B256x18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A256x18_B256x18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
              <direct input="prim_ram_A256x18_B256x18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[35:18]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_2K_A128x18_B128x18_composite_prim_ram_1x(A128x18_B128x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{7}.port_b_address_width{7}" class="memory" name="prim_ram_A128x18_B128x18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="7" port_class="address1"/>
              <input name="portbaddr" num_pins="7" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="18" port_class="data_in2"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x18_B128x18.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x18_B128x18.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A128x18_B128x18.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x18_B128x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x18_B128x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x18_B128x18.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x18_B128x18.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x18_B128x18.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x18_B128x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x18_B128x18.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x18_B128x18.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A128x18_B128x18.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x18_B128x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x18_B128x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x18_B128x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x18_B128x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x18_B128x18.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x18_B128x18.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A128x18_B128x18.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x18_B128x18.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x18_B128x18.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portbdatain"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x18_B128x18.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x18_B128x18.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_A128x18_B128x18.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x18_B128x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x18_B128x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x18_B128x18.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x18_B128x18.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x18_B128x18.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x18_B128x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x18_B128x18.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x18_B128x18.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A128x18_B128x18.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x18_B128x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x18_B128x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x18_B128x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x18_B128x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x18_B128x18.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x18_B128x18.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A128x18_B128x18.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x18_B128x18.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x18_B128x18.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A128x18_B128x18[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A128x18_B128x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A128x18_B128x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A128x18_B128x18[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A128x18_B128x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A128x18_B128x18[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A128x18_B128x18[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A128x18_B128x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A128x18_B128x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A128x18_B128x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A128x18_B128x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A128x18_B128x18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A128x18_B128x18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A128x18_B128x18[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A128x18_B128x18[0].clk_portbout[0] prim_ram_A128x18_B128x18[0].clk_portbin[0] prim_ram_A128x18_B128x18[0].clk_portain[0] prim_ram_A128x18_B128x18[0].clk_portaout[0] "/>
              <complete input="prim_ram_A128x18_B128x18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[6:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[6:0]" output="prim_ram_A128x18_B128x18[0].portaaddr[6:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[6:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].portaaddr[6:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[6:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[6:0]" output="prim_ram_A128x18_B128x18[0].portbaddr[6:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[6:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].portbaddr[6:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[17:0]" name="interconnect_split_ram_block_M9K_data_b_in_[17:0]" output="prim_ram_A128x18_B128x18[0].portbdatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].portbdatain[17:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[17:0]" name="interconnect_split_ram_block_M9K_data_a_in_[17:0]" output="prim_ram_A128x18_B128x18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A128x18_B128x18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
              <direct input="prim_ram_A128x18_B128x18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[35:18]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_2K_A128x18_B128x18_composite_prim_ram_1x(A128x18_B128x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{7}.port_b_address_width{7}" class="memory" name="prim_ram_A128x18_B128x18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="7" port_class="address1"/>
              <input name="portbaddr" num_pins="7" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="18" port_class="data_in2"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x18_B128x18.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x18_B128x18.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x18_B128x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x18_B128x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x18_B128x18.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x18_B128x18.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x18_B128x18.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x18_B128x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x18_B128x18.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x18_B128x18.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x18_B128x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x18_B128x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x18_B128x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x18_B128x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x18_B128x18.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x18_B128x18.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x18_B128x18.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x18_B128x18.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A128x18_B128x18.portbdatain"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portadataout"/>
              <delay_constant in_port="prim_ram_A128x18_B128x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A128x18_B128x18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x18_B128x18.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x18_B128x18.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x18_B128x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x18_B128x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x18_B128x18.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x18_B128x18.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x18_B128x18.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x18_B128x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x18_B128x18.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x18_B128x18.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x18_B128x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x18_B128x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x18_B128x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x18_B128x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x18_B128x18.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x18_B128x18.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x18_B128x18.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x18_B128x18.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A128x18_B128x18[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A128x18_B128x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A128x18_B128x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A128x18_B128x18[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A128x18_B128x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A128x18_B128x18[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A128x18_B128x18[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A128x18_B128x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A128x18_B128x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A128x18_B128x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A128x18_B128x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A128x18_B128x18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A128x18_B128x18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A128x18_B128x18[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A128x18_B128x18[0].clk_portbout[0] prim_ram_A128x18_B128x18[0].clk_portbin[0] prim_ram_A128x18_B128x18[0].clk_portain[0] prim_ram_A128x18_B128x18[0].clk_portaout[0] "/>
              <complete input="prim_ram_A128x18_B128x18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[6:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[6:0]" output="prim_ram_A128x18_B128x18[0].portaaddr[6:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[6:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].portaaddr[6:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[6:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[6:0]" output="prim_ram_A128x18_B128x18[0].portbaddr[6:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[6:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].portbaddr[6:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[17:0]" name="interconnect_split_ram_block_M9K_data_b_in_[17:0]" output="prim_ram_A128x18_B128x18[0].portbdatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].portbdatain[17:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[17:0]" name="interconnect_split_ram_block_M9K_data_a_in_[17:0]" output="prim_ram_A128x18_B128x18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A128x18_B128x18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A128x18_B128x18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
              <direct input="prim_ram_A128x18_B128x18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[35:18]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_1K_A64x18_B64x18_composite_prim_ram_1x(A64x18_B64x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{6}.port_b_address_width{6}" class="memory" name="prim_ram_A64x18_B64x18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="6" port_class="address1"/>
              <input name="portbaddr" num_pins="6" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="18" port_class="data_in2"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x18_B64x18.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x18_B64x18.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A64x18_B64x18.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x18_B64x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x18_B64x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x18_B64x18.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x18_B64x18.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x18_B64x18.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x18_B64x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x18_B64x18.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x18_B64x18.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A64x18_B64x18.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x18_B64x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x18_B64x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x18_B64x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x18_B64x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x18_B64x18.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x18_B64x18.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A64x18_B64x18.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x18_B64x18.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x18_B64x18.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portbdatain"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x18_B64x18.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x18_B64x18.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_A64x18_B64x18.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x18_B64x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x18_B64x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x18_B64x18.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x18_B64x18.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x18_B64x18.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x18_B64x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x18_B64x18.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x18_B64x18.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A64x18_B64x18.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x18_B64x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x18_B64x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x18_B64x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x18_B64x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x18_B64x18.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x18_B64x18.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A64x18_B64x18.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x18_B64x18.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x18_B64x18.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A64x18_B64x18[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A64x18_B64x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A64x18_B64x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A64x18_B64x18[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A64x18_B64x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A64x18_B64x18[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A64x18_B64x18[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A64x18_B64x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A64x18_B64x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A64x18_B64x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A64x18_B64x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A64x18_B64x18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A64x18_B64x18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A64x18_B64x18[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A64x18_B64x18[0].clk_portbout[0] prim_ram_A64x18_B64x18[0].clk_portbin[0] prim_ram_A64x18_B64x18[0].clk_portain[0] prim_ram_A64x18_B64x18[0].clk_portaout[0] "/>
              <complete input="prim_ram_A64x18_B64x18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[5:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[5:0]" output="prim_ram_A64x18_B64x18[0].portaaddr[5:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[5:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].portaaddr[5:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[5:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[5:0]" output="prim_ram_A64x18_B64x18[0].portbaddr[5:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[5:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].portbaddr[5:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[17:0]" name="interconnect_split_ram_block_M9K_data_b_in_[17:0]" output="prim_ram_A64x18_B64x18[0].portbdatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].portbdatain[17:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[17:0]" name="interconnect_split_ram_block_M9K_data_a_in_[17:0]" output="prim_ram_A64x18_B64x18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A64x18_B64x18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
              <direct input="prim_ram_A64x18_B64x18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[35:18]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_1K_A64x18_B64x18_composite_prim_ram_1x(A64x18_B64x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{6}.port_b_address_width{6}" class="memory" name="prim_ram_A64x18_B64x18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="6" port_class="address1"/>
              <input name="portbaddr" num_pins="6" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="18" port_class="data_in2"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x18_B64x18.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x18_B64x18.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x18_B64x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x18_B64x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x18_B64x18.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x18_B64x18.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x18_B64x18.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x18_B64x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x18_B64x18.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x18_B64x18.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x18_B64x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x18_B64x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x18_B64x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x18_B64x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x18_B64x18.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x18_B64x18.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x18_B64x18.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x18_B64x18.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A64x18_B64x18.portbdatain"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portadataout"/>
              <delay_constant in_port="prim_ram_A64x18_B64x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A64x18_B64x18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x18_B64x18.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x18_B64x18.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x18_B64x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x18_B64x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x18_B64x18.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x18_B64x18.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x18_B64x18.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x18_B64x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x18_B64x18.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x18_B64x18.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x18_B64x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x18_B64x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x18_B64x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x18_B64x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x18_B64x18.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x18_B64x18.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x18_B64x18.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x18_B64x18.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A64x18_B64x18[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A64x18_B64x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A64x18_B64x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A64x18_B64x18[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A64x18_B64x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A64x18_B64x18[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A64x18_B64x18[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A64x18_B64x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A64x18_B64x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A64x18_B64x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A64x18_B64x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A64x18_B64x18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A64x18_B64x18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A64x18_B64x18[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A64x18_B64x18[0].clk_portbout[0] prim_ram_A64x18_B64x18[0].clk_portbin[0] prim_ram_A64x18_B64x18[0].clk_portain[0] prim_ram_A64x18_B64x18[0].clk_portaout[0] "/>
              <complete input="prim_ram_A64x18_B64x18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[5:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[5:0]" output="prim_ram_A64x18_B64x18[0].portaaddr[5:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[5:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].portaaddr[5:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[5:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[5:0]" output="prim_ram_A64x18_B64x18[0].portbaddr[5:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[5:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].portbaddr[5:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[17:0]" name="interconnect_split_ram_block_M9K_data_b_in_[17:0]" output="prim_ram_A64x18_B64x18[0].portbdatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].portbdatain[17:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[17:0]" name="interconnect_split_ram_block_M9K_data_a_in_[17:0]" output="prim_ram_A64x18_B64x18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A64x18_B64x18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A64x18_B64x18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
              <direct input="prim_ram_A64x18_B64x18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[35:18]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_576_A32x18_B32x18_composite_prim_ram_1x(A32x18_B32x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{5}.port_b_address_width{5}" class="memory" name="prim_ram_A32x18_B32x18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="5" port_class="address1"/>
              <input name="portbaddr" num_pins="5" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="18" port_class="data_in2"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x18_B32x18.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x18_B32x18.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A32x18_B32x18.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x18_B32x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x18_B32x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x18_B32x18.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x18_B32x18.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x18_B32x18.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x18_B32x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x18_B32x18.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x18_B32x18.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A32x18_B32x18.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x18_B32x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x18_B32x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x18_B32x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x18_B32x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x18_B32x18.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x18_B32x18.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A32x18_B32x18.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x18_B32x18.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x18_B32x18.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portbdatain"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x18_B32x18.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x18_B32x18.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_A32x18_B32x18.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x18_B32x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x18_B32x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x18_B32x18.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x18_B32x18.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x18_B32x18.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x18_B32x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x18_B32x18.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x18_B32x18.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A32x18_B32x18.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x18_B32x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x18_B32x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x18_B32x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x18_B32x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x18_B32x18.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x18_B32x18.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A32x18_B32x18.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x18_B32x18.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x18_B32x18.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A32x18_B32x18[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A32x18_B32x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A32x18_B32x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A32x18_B32x18[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A32x18_B32x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A32x18_B32x18[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A32x18_B32x18[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A32x18_B32x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A32x18_B32x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A32x18_B32x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A32x18_B32x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A32x18_B32x18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A32x18_B32x18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A32x18_B32x18[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A32x18_B32x18[0].clk_portbout[0] prim_ram_A32x18_B32x18[0].clk_portbin[0] prim_ram_A32x18_B32x18[0].clk_portain[0] prim_ram_A32x18_B32x18[0].clk_portaout[0] "/>
              <complete input="prim_ram_A32x18_B32x18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[4:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[4:0]" output="prim_ram_A32x18_B32x18[0].portaaddr[4:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[4:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].portaaddr[4:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[4:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[4:0]" output="prim_ram_A32x18_B32x18[0].portbaddr[4:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[4:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].portbaddr[4:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[17:0]" name="interconnect_split_ram_block_M9K_data_b_in_[17:0]" output="prim_ram_A32x18_B32x18[0].portbdatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].portbdatain[17:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[17:0]" name="interconnect_split_ram_block_M9K_data_a_in_[17:0]" output="prim_ram_A32x18_B32x18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A32x18_B32x18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
              <direct input="prim_ram_A32x18_B32x18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[35:18]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_576_A32x18_B32x18_composite_prim_ram_1x(A32x18_B32x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{5}.port_b_address_width{5}" class="memory" name="prim_ram_A32x18_B32x18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="5" port_class="address1"/>
              <input name="portbaddr" num_pins="5" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="18" port_class="data_in2"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x18_B32x18.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x18_B32x18.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x18_B32x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x18_B32x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x18_B32x18.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x18_B32x18.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x18_B32x18.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x18_B32x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x18_B32x18.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x18_B32x18.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x18_B32x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x18_B32x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x18_B32x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x18_B32x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x18_B32x18.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x18_B32x18.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x18_B32x18.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x18_B32x18.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A32x18_B32x18.portbdatain"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portadataout"/>
              <delay_constant in_port="prim_ram_A32x18_B32x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A32x18_B32x18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x18_B32x18.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x18_B32x18.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x18_B32x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x18_B32x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x18_B32x18.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x18_B32x18.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x18_B32x18.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x18_B32x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x18_B32x18.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x18_B32x18.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x18_B32x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x18_B32x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x18_B32x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x18_B32x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x18_B32x18.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x18_B32x18.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x18_B32x18.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x18_B32x18.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A32x18_B32x18[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A32x18_B32x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A32x18_B32x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A32x18_B32x18[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A32x18_B32x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A32x18_B32x18[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A32x18_B32x18[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A32x18_B32x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A32x18_B32x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A32x18_B32x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A32x18_B32x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A32x18_B32x18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A32x18_B32x18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A32x18_B32x18[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A32x18_B32x18[0].clk_portbout[0] prim_ram_A32x18_B32x18[0].clk_portbin[0] prim_ram_A32x18_B32x18[0].clk_portain[0] prim_ram_A32x18_B32x18[0].clk_portaout[0] "/>
              <complete input="prim_ram_A32x18_B32x18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[4:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[4:0]" output="prim_ram_A32x18_B32x18[0].portaaddr[4:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[4:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].portaaddr[4:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[4:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[4:0]" output="prim_ram_A32x18_B32x18[0].portbaddr[4:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[4:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].portbaddr[4:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[17:0]" name="interconnect_split_ram_block_M9K_data_b_in_[17:0]" output="prim_ram_A32x18_B32x18[0].portbdatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].portbdatain[17:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[17:0]" name="interconnect_split_ram_block_M9K_data_a_in_[17:0]" output="prim_ram_A32x18_B32x18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A32x18_B32x18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A32x18_B32x18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
              <direct input="prim_ram_A32x18_B32x18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[35:18]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_288_A16x18_B16x18_composite_prim_ram_1x(A16x18_B16x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{4}.port_b_address_width{4}" class="memory" name="prim_ram_A16x18_B16x18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="4" port_class="address1"/>
              <input name="portbaddr" num_pins="4" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="18" port_class="data_in2"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x18_B16x18.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x18_B16x18.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A16x18_B16x18.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x18_B16x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x18_B16x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x18_B16x18.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x18_B16x18.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x18_B16x18.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x18_B16x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x18_B16x18.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x18_B16x18.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A16x18_B16x18.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x18_B16x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x18_B16x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x18_B16x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x18_B16x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x18_B16x18.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x18_B16x18.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A16x18_B16x18.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x18_B16x18.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x18_B16x18.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portbdatain"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x18_B16x18.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x18_B16x18.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_A16x18_B16x18.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x18_B16x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x18_B16x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x18_B16x18.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x18_B16x18.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x18_B16x18.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x18_B16x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x18_B16x18.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x18_B16x18.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A16x18_B16x18.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x18_B16x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x18_B16x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x18_B16x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x18_B16x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x18_B16x18.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x18_B16x18.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A16x18_B16x18.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x18_B16x18.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x18_B16x18.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A16x18_B16x18[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A16x18_B16x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A16x18_B16x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A16x18_B16x18[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A16x18_B16x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A16x18_B16x18[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A16x18_B16x18[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A16x18_B16x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A16x18_B16x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A16x18_B16x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A16x18_B16x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A16x18_B16x18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A16x18_B16x18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A16x18_B16x18[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A16x18_B16x18[0].clk_portbout[0] prim_ram_A16x18_B16x18[0].clk_portbin[0] prim_ram_A16x18_B16x18[0].clk_portain[0] prim_ram_A16x18_B16x18[0].clk_portaout[0] "/>
              <complete input="prim_ram_A16x18_B16x18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[3:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[3:0]" output="prim_ram_A16x18_B16x18[0].portaaddr[3:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[3:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].portaaddr[3:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[3:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[3:0]" output="prim_ram_A16x18_B16x18[0].portbaddr[3:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[3:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].portbaddr[3:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[17:0]" name="interconnect_split_ram_block_M9K_data_b_in_[17:0]" output="prim_ram_A16x18_B16x18[0].portbdatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].portbdatain[17:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[17:0]" name="interconnect_split_ram_block_M9K_data_a_in_[17:0]" output="prim_ram_A16x18_B16x18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A16x18_B16x18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
              <direct input="prim_ram_A16x18_B16x18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[35:18]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_288_A16x18_B16x18_composite_prim_ram_1x(A16x18_B16x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{4}.port_b_address_width{4}" class="memory" name="prim_ram_A16x18_B16x18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="4" port_class="address1"/>
              <input name="portbaddr" num_pins="4" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="18" port_class="data_in2"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x18_B16x18.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x18_B16x18.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x18_B16x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x18_B16x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x18_B16x18.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x18_B16x18.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x18_B16x18.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x18_B16x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x18_B16x18.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x18_B16x18.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x18_B16x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x18_B16x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x18_B16x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x18_B16x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x18_B16x18.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x18_B16x18.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x18_B16x18.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x18_B16x18.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A16x18_B16x18.portbdatain"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portadataout"/>
              <delay_constant in_port="prim_ram_A16x18_B16x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A16x18_B16x18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x18_B16x18.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x18_B16x18.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x18_B16x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x18_B16x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x18_B16x18.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x18_B16x18.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x18_B16x18.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x18_B16x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x18_B16x18.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x18_B16x18.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x18_B16x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x18_B16x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x18_B16x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x18_B16x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x18_B16x18.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x18_B16x18.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x18_B16x18.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x18_B16x18.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A16x18_B16x18[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A16x18_B16x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A16x18_B16x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A16x18_B16x18[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A16x18_B16x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A16x18_B16x18[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A16x18_B16x18[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A16x18_B16x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A16x18_B16x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A16x18_B16x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A16x18_B16x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A16x18_B16x18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A16x18_B16x18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A16x18_B16x18[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A16x18_B16x18[0].clk_portbout[0] prim_ram_A16x18_B16x18[0].clk_portbin[0] prim_ram_A16x18_B16x18[0].clk_portain[0] prim_ram_A16x18_B16x18[0].clk_portaout[0] "/>
              <complete input="prim_ram_A16x18_B16x18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[3:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[3:0]" output="prim_ram_A16x18_B16x18[0].portaaddr[3:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[3:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].portaaddr[3:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[3:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[3:0]" output="prim_ram_A16x18_B16x18[0].portbaddr[3:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[3:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].portbaddr[3:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[17:0]" name="interconnect_split_ram_block_M9K_data_b_in_[17:0]" output="prim_ram_A16x18_B16x18[0].portbdatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].portbdatain[17:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[17:0]" name="interconnect_split_ram_block_M9K_data_a_in_[17:0]" output="prim_ram_A16x18_B16x18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A16x18_B16x18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A16x18_B16x18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
              <direct input="prim_ram_A16x18_B16x18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[35:18]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_144_A8x18_B8x18_composite_prim_ram_1x(A8x18_B8x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{3}.port_b_address_width{3}" class="memory" name="prim_ram_A8x18_B8x18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="3" port_class="address1"/>
              <input name="portbaddr" num_pins="3" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="18" port_class="data_in2"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x18_B8x18.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x18_B8x18.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A8x18_B8x18.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x18_B8x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x18_B8x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x18_B8x18.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x18_B8x18.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x18_B8x18.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x18_B8x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x18_B8x18.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x18_B8x18.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A8x18_B8x18.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x18_B8x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x18_B8x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x18_B8x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x18_B8x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x18_B8x18.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x18_B8x18.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A8x18_B8x18.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x18_B8x18.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x18_B8x18.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portbdatain"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x18_B8x18.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x18_B8x18.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_A8x18_B8x18.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x18_B8x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x18_B8x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x18_B8x18.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x18_B8x18.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x18_B8x18.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x18_B8x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x18_B8x18.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x18_B8x18.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A8x18_B8x18.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x18_B8x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x18_B8x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x18_B8x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x18_B8x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x18_B8x18.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x18_B8x18.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A8x18_B8x18.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x18_B8x18.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x18_B8x18.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A8x18_B8x18[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A8x18_B8x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A8x18_B8x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A8x18_B8x18[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A8x18_B8x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A8x18_B8x18[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A8x18_B8x18[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A8x18_B8x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A8x18_B8x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A8x18_B8x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A8x18_B8x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A8x18_B8x18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A8x18_B8x18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A8x18_B8x18[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A8x18_B8x18[0].clk_portbout[0] prim_ram_A8x18_B8x18[0].clk_portbin[0] prim_ram_A8x18_B8x18[0].clk_portain[0] prim_ram_A8x18_B8x18[0].clk_portaout[0] "/>
              <complete input="prim_ram_A8x18_B8x18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[2:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[2:0]" output="prim_ram_A8x18_B8x18[0].portaaddr[2:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[2:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].portaaddr[2:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[2:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[2:0]" output="prim_ram_A8x18_B8x18[0].portbaddr[2:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[2:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].portbaddr[2:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[17:0]" name="interconnect_split_ram_block_M9K_data_b_in_[17:0]" output="prim_ram_A8x18_B8x18[0].portbdatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].portbdatain[17:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[17:0]" name="interconnect_split_ram_block_M9K_data_a_in_[17:0]" output="prim_ram_A8x18_B8x18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A8x18_B8x18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
              <direct input="prim_ram_A8x18_B8x18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[35:18]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_144_A8x18_B8x18_composite_prim_ram_1x(A8x18_B8x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{3}.port_b_address_width{3}" class="memory" name="prim_ram_A8x18_B8x18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="3" port_class="address1"/>
              <input name="portbaddr" num_pins="3" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="18" port_class="data_in2"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x18_B8x18.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x18_B8x18.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x18_B8x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x18_B8x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x18_B8x18.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x18_B8x18.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x18_B8x18.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x18_B8x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x18_B8x18.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x18_B8x18.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x18_B8x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x18_B8x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x18_B8x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x18_B8x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x18_B8x18.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x18_B8x18.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x18_B8x18.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x18_B8x18.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A8x18_B8x18.portbdatain"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portadataout"/>
              <delay_constant in_port="prim_ram_A8x18_B8x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A8x18_B8x18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x18_B8x18.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x18_B8x18.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x18_B8x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x18_B8x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x18_B8x18.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x18_B8x18.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x18_B8x18.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x18_B8x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x18_B8x18.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x18_B8x18.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x18_B8x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x18_B8x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x18_B8x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x18_B8x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x18_B8x18.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x18_B8x18.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x18_B8x18.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x18_B8x18.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A8x18_B8x18[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A8x18_B8x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A8x18_B8x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A8x18_B8x18[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A8x18_B8x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A8x18_B8x18[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A8x18_B8x18[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A8x18_B8x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A8x18_B8x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A8x18_B8x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A8x18_B8x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A8x18_B8x18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A8x18_B8x18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A8x18_B8x18[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A8x18_B8x18[0].clk_portbout[0] prim_ram_A8x18_B8x18[0].clk_portbin[0] prim_ram_A8x18_B8x18[0].clk_portain[0] prim_ram_A8x18_B8x18[0].clk_portaout[0] "/>
              <complete input="prim_ram_A8x18_B8x18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[2:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[2:0]" output="prim_ram_A8x18_B8x18[0].portaaddr[2:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[2:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].portaaddr[2:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[2:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[2:0]" output="prim_ram_A8x18_B8x18[0].portbaddr[2:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[2:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].portbaddr[2:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[17:0]" name="interconnect_split_ram_block_M9K_data_b_in_[17:0]" output="prim_ram_A8x18_B8x18[0].portbdatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].portbdatain[17:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[17:0]" name="interconnect_split_ram_block_M9K_data_a_in_[17:0]" output="prim_ram_A8x18_B8x18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A8x18_B8x18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A8x18_B8x18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
              <direct input="prim_ram_A8x18_B8x18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[35:18]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_72_A4x18_B4x18_composite_prim_ram_1x(A4x18_B4x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{2}.port_b_address_width{2}" class="memory" name="prim_ram_A4x18_B4x18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="2" port_class="address1"/>
              <input name="portbaddr" num_pins="2" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="18" port_class="data_in2"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x18_B4x18.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x18_B4x18.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A4x18_B4x18.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x18_B4x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x18_B4x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x18_B4x18.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x18_B4x18.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x18_B4x18.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x18_B4x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x18_B4x18.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x18_B4x18.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A4x18_B4x18.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x18_B4x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x18_B4x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x18_B4x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x18_B4x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x18_B4x18.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x18_B4x18.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A4x18_B4x18.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x18_B4x18.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x18_B4x18.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portbdatain"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x18_B4x18.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x18_B4x18.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_A4x18_B4x18.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x18_B4x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x18_B4x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x18_B4x18.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x18_B4x18.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x18_B4x18.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x18_B4x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x18_B4x18.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x18_B4x18.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A4x18_B4x18.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x18_B4x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x18_B4x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x18_B4x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x18_B4x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x18_B4x18.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x18_B4x18.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A4x18_B4x18.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x18_B4x18.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x18_B4x18.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A4x18_B4x18[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A4x18_B4x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A4x18_B4x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A4x18_B4x18[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A4x18_B4x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A4x18_B4x18[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A4x18_B4x18[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A4x18_B4x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A4x18_B4x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A4x18_B4x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A4x18_B4x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A4x18_B4x18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A4x18_B4x18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A4x18_B4x18[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A4x18_B4x18[0].clk_portbout[0] prim_ram_A4x18_B4x18[0].clk_portbin[0] prim_ram_A4x18_B4x18[0].clk_portain[0] prim_ram_A4x18_B4x18[0].clk_portaout[0] "/>
              <complete input="prim_ram_A4x18_B4x18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[1:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[1:0]" output="prim_ram_A4x18_B4x18[0].portaaddr[1:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[1:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].portaaddr[1:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[1:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[1:0]" output="prim_ram_A4x18_B4x18[0].portbaddr[1:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[1:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].portbaddr[1:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[17:0]" name="interconnect_split_ram_block_M9K_data_b_in_[17:0]" output="prim_ram_A4x18_B4x18[0].portbdatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].portbdatain[17:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[17:0]" name="interconnect_split_ram_block_M9K_data_a_in_[17:0]" output="prim_ram_A4x18_B4x18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A4x18_B4x18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
              <direct input="prim_ram_A4x18_B4x18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[35:18]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_72_A4x18_B4x18_composite_prim_ram_1x(A4x18_B4x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{2}.port_b_address_width{2}" class="memory" name="prim_ram_A4x18_B4x18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="2" port_class="address1"/>
              <input name="portbaddr" num_pins="2" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="18" port_class="data_in2"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x18_B4x18.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x18_B4x18.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x18_B4x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x18_B4x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x18_B4x18.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x18_B4x18.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x18_B4x18.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x18_B4x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x18_B4x18.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x18_B4x18.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x18_B4x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x18_B4x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x18_B4x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x18_B4x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x18_B4x18.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x18_B4x18.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x18_B4x18.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x18_B4x18.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A4x18_B4x18.portbdatain"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portadataout"/>
              <delay_constant in_port="prim_ram_A4x18_B4x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A4x18_B4x18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x18_B4x18.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x18_B4x18.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x18_B4x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x18_B4x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x18_B4x18.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x18_B4x18.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x18_B4x18.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x18_B4x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x18_B4x18.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x18_B4x18.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x18_B4x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x18_B4x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x18_B4x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x18_B4x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x18_B4x18.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x18_B4x18.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x18_B4x18.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x18_B4x18.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A4x18_B4x18[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A4x18_B4x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A4x18_B4x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A4x18_B4x18[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A4x18_B4x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A4x18_B4x18[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A4x18_B4x18[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A4x18_B4x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A4x18_B4x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A4x18_B4x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A4x18_B4x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A4x18_B4x18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A4x18_B4x18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A4x18_B4x18[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A4x18_B4x18[0].clk_portbout[0] prim_ram_A4x18_B4x18[0].clk_portbin[0] prim_ram_A4x18_B4x18[0].clk_portain[0] prim_ram_A4x18_B4x18[0].clk_portaout[0] "/>
              <complete input="prim_ram_A4x18_B4x18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[1:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[1:0]" output="prim_ram_A4x18_B4x18[0].portaaddr[1:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[1:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].portaaddr[1:0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[1:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[1:0]" output="prim_ram_A4x18_B4x18[0].portbaddr[1:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[1:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].portbaddr[1:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[17:0]" name="interconnect_split_ram_block_M9K_data_b_in_[17:0]" output="prim_ram_A4x18_B4x18[0].portbdatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].portbdatain[17:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[17:0]" name="interconnect_split_ram_block_M9K_data_a_in_[17:0]" output="prim_ram_A4x18_B4x18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A4x18_B4x18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A4x18_B4x18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
              <direct input="prim_ram_A4x18_B4x18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[35:18]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_36_A2x18_B2x18_composite_prim_ram_1x(A2x18_B2x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{1}.port_b_address_width{1}" class="memory" name="prim_ram_A2x18_B2x18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <input name="portbaddr" num_pins="1" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="18" port_class="data_in2"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x18_B2x18.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x18_B2x18.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A2x18_B2x18.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x18_B2x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x18_B2x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x18_B2x18.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x18_B2x18.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x18_B2x18.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x18_B2x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x18_B2x18.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x18_B2x18.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A2x18_B2x18.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x18_B2x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x18_B2x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x18_B2x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x18_B2x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x18_B2x18.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x18_B2x18.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A2x18_B2x18.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x18_B2x18.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x18_B2x18.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portbdatain"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x18_B2x18.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x18_B2x18.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_A2x18_B2x18.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x18_B2x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x18_B2x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x18_B2x18.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x18_B2x18.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x18_B2x18.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x18_B2x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x18_B2x18.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x18_B2x18.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A2x18_B2x18.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x18_B2x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x18_B2x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x18_B2x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x18_B2x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x18_B2x18.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x18_B2x18.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A2x18_B2x18.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x18_B2x18.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x18_B2x18.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A2x18_B2x18[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A2x18_B2x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A2x18_B2x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A2x18_B2x18[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A2x18_B2x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A2x18_B2x18[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A2x18_B2x18[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A2x18_B2x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A2x18_B2x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A2x18_B2x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A2x18_B2x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A2x18_B2x18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A2x18_B2x18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A2x18_B2x18[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A2x18_B2x18[0].clk_portbout[0] prim_ram_A2x18_B2x18[0].clk_portbin[0] prim_ram_A2x18_B2x18[0].clk_portain[0] prim_ram_A2x18_B2x18[0].clk_portaout[0] "/>
              <complete input="prim_ram_A2x18_B2x18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[0]" name="interconnect_common_ram_block_M9K_addr_a_in_[0]" output="prim_ram_A2x18_B2x18[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].portaaddr[0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[0]" name="interconnect_common_ram_block_M9K_addr_b_in_[0]" output="prim_ram_A2x18_B2x18[0].portbaddr[0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].portbaddr[0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[17:0]" name="interconnect_split_ram_block_M9K_data_b_in_[17:0]" output="prim_ram_A2x18_B2x18[0].portbdatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].portbdatain[17:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[17:0]" name="interconnect_split_ram_block_M9K_data_a_in_[17:0]" output="prim_ram_A2x18_B2x18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A2x18_B2x18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
              <direct input="prim_ram_A2x18_B2x18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[35:18]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_36_A2x18_B2x18_composite_prim_ram_1x(A2x18_B2x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{1}.port_b_address_width{1}" class="memory" name="prim_ram_A2x18_B2x18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <input name="portbaddr" num_pins="1" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="18" port_class="data_in2"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x18_B2x18.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x18_B2x18.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x18_B2x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x18_B2x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x18_B2x18.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x18_B2x18.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x18_B2x18.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x18_B2x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x18_B2x18.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x18_B2x18.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x18_B2x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x18_B2x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x18_B2x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x18_B2x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x18_B2x18.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x18_B2x18.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x18_B2x18.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x18_B2x18.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A2x18_B2x18.portbdatain"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portadataout"/>
              <delay_constant in_port="prim_ram_A2x18_B2x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A2x18_B2x18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x18_B2x18.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x18_B2x18.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x18_B2x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x18_B2x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x18_B2x18.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x18_B2x18.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x18_B2x18.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x18_B2x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x18_B2x18.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x18_B2x18.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x18_B2x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x18_B2x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x18_B2x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x18_B2x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x18_B2x18.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x18_B2x18.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x18_B2x18.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x18_B2x18.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A2x18_B2x18[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A2x18_B2x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A2x18_B2x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A2x18_B2x18[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A2x18_B2x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A2x18_B2x18[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A2x18_B2x18[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A2x18_B2x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A2x18_B2x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A2x18_B2x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A2x18_B2x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A2x18_B2x18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A2x18_B2x18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A2x18_B2x18[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A2x18_B2x18[0].clk_portbout[0] prim_ram_A2x18_B2x18[0].clk_portbin[0] prim_ram_A2x18_B2x18[0].clk_portain[0] prim_ram_A2x18_B2x18[0].clk_portaout[0] "/>
              <complete input="prim_ram_A2x18_B2x18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[0]" name="interconnect_common_ram_block_M9K_addr_a_in_[0]" output="prim_ram_A2x18_B2x18[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].portaaddr[0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[0]" name="interconnect_common_ram_block_M9K_addr_b_in_[0]" output="prim_ram_A2x18_B2x18[0].portbaddr[0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].portbaddr[0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[17:0]" name="interconnect_split_ram_block_M9K_data_b_in_[17:0]" output="prim_ram_A2x18_B2x18[0].portbdatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].portbdatain[17:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[17:0]" name="interconnect_split_ram_block_M9K_data_a_in_[17:0]" output="prim_ram_A2x18_B2x18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A2x18_B2x18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A2x18_B2x18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
              <direct input="prim_ram_A2x18_B2x18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[35:18]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_18_A1x18_B1x18_composite_prim_ram_1x(A1x18_B1x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{0}.port_b_address_width{0}" class="memory" name="prim_ram_A1x18_B1x18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <input name="portbaddr" num_pins="1" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="18" port_class="data_in2"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x18_B1x18.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x18_B1x18.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A1x18_B1x18.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x18_B1x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x18_B1x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x18_B1x18.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x18_B1x18.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x18_B1x18.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x18_B1x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x18_B1x18.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x18_B1x18.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A1x18_B1x18.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x18_B1x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x18_B1x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x18_B1x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x18_B1x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x18_B1x18.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x18_B1x18.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A1x18_B1x18.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x18_B1x18.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x18_B1x18.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portbdatain"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x18_B1x18.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x18_B1x18.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_A1x18_B1x18.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x18_B1x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x18_B1x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x18_B1x18.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x18_B1x18.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x18_B1x18.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x18_B1x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x18_B1x18.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x18_B1x18.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A1x18_B1x18.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x18_B1x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x18_B1x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x18_B1x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x18_B1x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x18_B1x18.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x18_B1x18.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_A1x18_B1x18.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x18_B1x18.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x18_B1x18.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A1x18_B1x18[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A1x18_B1x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A1x18_B1x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A1x18_B1x18[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A1x18_B1x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A1x18_B1x18[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A1x18_B1x18[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A1x18_B1x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A1x18_B1x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A1x18_B1x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A1x18_B1x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A1x18_B1x18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A1x18_B1x18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A1x18_B1x18[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A1x18_B1x18[0].clk_portbout[0] prim_ram_A1x18_B1x18[0].clk_portbin[0] prim_ram_A1x18_B1x18[0].clk_portain[0] prim_ram_A1x18_B1x18[0].clk_portaout[0] "/>
              <complete input="prim_ram_A1x18_B1x18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[0]" name="interconnect_common_ram_block_M9K_addr_a_in_[0]" output="prim_ram_A1x18_B1x18[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].portaaddr[0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[0]" name="interconnect_common_ram_block_M9K_addr_b_in_[0]" output="prim_ram_A1x18_B1x18[0].portbaddr[0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].portbaddr[0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[17:0]" name="interconnect_split_ram_block_M9K_data_b_in_[17:0]" output="prim_ram_A1x18_B1x18[0].portbdatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].portbdatain[17:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[17:0]" name="interconnect_split_ram_block_M9K_data_a_in_[17:0]" output="prim_ram_A1x18_B1x18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A1x18_B1x18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
              <direct input="prim_ram_A1x18_B1x18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[35:18]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_18_A1x18_B1x18_composite_prim_ram_1x(A1x18_B1x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{0}.port_b_address_width{0}" class="memory" name="prim_ram_A1x18_B1x18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <input name="portbaddr" num_pins="1" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="18" port_class="data_in2"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x18_B1x18.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x18_B1x18.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x18_B1x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x18_B1x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x18_B1x18.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x18_B1x18.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x18_B1x18.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x18_B1x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x18_B1x18.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x18_B1x18.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x18_B1x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x18_B1x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x18_B1x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x18_B1x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x18_B1x18.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x18_B1x18.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x18_B1x18.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x18_B1x18.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_A1x18_B1x18.portbdatain"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portadataout"/>
              <delay_constant in_port="prim_ram_A1x18_B1x18.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_A1x18_B1x18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x18_B1x18.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x18_B1x18.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x18_B1x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x18_B1x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x18_B1x18.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x18_B1x18.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x18_B1x18.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x18_B1x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x18_B1x18.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x18_B1x18.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x18_B1x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x18_B1x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x18_B1x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x18_B1x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x18_B1x18.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x18_B1x18.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x18_B1x18.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x18_B1x18.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_A1x18_B1x18[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_A1x18_B1x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_A1x18_B1x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_A1x18_B1x18[0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_A1x18_B1x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]" output="prim_ram_A1x18_B1x18[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_A1x18_B1x18[0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_A1x18_B1x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_A1x18_B1x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_A1x18_B1x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_A1x18_B1x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_A1x18_B1x18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]" output="prim_ram_A1x18_B1x18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_A1x18_B1x18[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_A1x18_B1x18[0].clk_portbout[0] prim_ram_A1x18_B1x18[0].clk_portbin[0] prim_ram_A1x18_B1x18[0].clk_portain[0] prim_ram_A1x18_B1x18[0].clk_portaout[0] "/>
              <complete input="prim_ram_A1x18_B1x18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M9K_control_out_[2:0]" output="ram_block_M9K.control_out[2:0]"/>
              <complete input="ram_block_M9K.addr_a_in[0]" name="interconnect_common_ram_block_M9K_addr_a_in_[0]" output="prim_ram_A1x18_B1x18[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].portaaddr[0]"/>
              </complete>
              <complete input="ram_block_M9K.addr_b_in[0]" name="interconnect_common_ram_block_M9K_addr_b_in_[0]" output="prim_ram_A1x18_B1x18[0].portbaddr[0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].portbaddr[0]"/>
              </complete>
              <direct input="ram_block_M9K.data_b_in[17:0]" name="interconnect_split_ram_block_M9K_data_b_in_[17:0]" output="prim_ram_A1x18_B1x18[0].portbdatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_b_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].portbdatain[17:0]"/>
              </direct>
              <direct input="ram_block_M9K.data_a_in[17:0]" name="interconnect_split_ram_block_M9K_data_a_in_[17:0]" output="prim_ram_A1x18_B1x18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_A1x18_B1x18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A1x18_B1x18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
              <direct input="prim_ram_A1x18_B1x18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_2" output="ram_block_M9K.data_out[35:18]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_9K_1Kx9_composite_prim_ram_1x(1Kx9)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{10}" class="memory" name="prim_ram_1Kx9" num_pb="1">
              <input name="portadatain" num_pins="9" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="10" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="9" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_1Kx9.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_1Kx9.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.portawe"/>
              <delay_constant in_port="prim_ram_1Kx9.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_1Kx9.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_1Kx9[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_1Kx9[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_1Kx9[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_1Kx9[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_1Kx9[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_1Kx9[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_1Kx9[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_1Kx9[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_1Kx9[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_1Kx9[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_1Kx9[0].clk_portain[0] prim_ram_1Kx9[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[9:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[9:0]" output="prim_ram_1Kx9[0].portaaddr[9:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[9:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].portaaddr[9:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[8:0]" name="interconnect_split_ram_block_M9K_data_a_in_[8:0]" output="prim_ram_1Kx9[0].portadatain[8:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[8:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].portadatain[8:0]"/>
              </direct>
              <direct input="prim_ram_1Kx9[0].portadataout[8:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[8:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_9K_1Kx9_composite_prim_ram_1x(1Kx9)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{10}" class="memory" name="prim_ram_1Kx9" num_pb="1">
              <input name="portadatain" num_pins="9" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="10" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="9" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.portawe"/>
              <delay_constant in_port="prim_ram_1Kx9.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_1Kx9[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_1Kx9[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_1Kx9[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_1Kx9[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_1Kx9[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_1Kx9[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_1Kx9[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_1Kx9[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_1Kx9[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_1Kx9[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_1Kx9[0].clk_portain[0] prim_ram_1Kx9[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[9:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[9:0]" output="prim_ram_1Kx9[0].portaaddr[9:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[9:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].portaaddr[9:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[8:0]" name="interconnect_split_ram_block_M9K_data_a_in_[8:0]" output="prim_ram_1Kx9[0].portadatain[8:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[8:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].portadatain[8:0]"/>
              </direct>
              <direct input="prim_ram_1Kx9[0].portadataout[8:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[8:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_9K_512x18_composite_prim_ram_1x(512x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{9}" class="memory" name="prim_ram_512x18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="9" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_512x18.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_512x18.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.portawe"/>
              <delay_constant in_port="prim_ram_512x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_512x18.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_512x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_512x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_512x18[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_512x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_512x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_512x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_512x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_512x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_512x18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_512x18[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_512x18[0].clk_portain[0] prim_ram_512x18[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[8:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[8:0]" output="prim_ram_512x18[0].portaaddr[8:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[8:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].portaaddr[8:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[17:0]" name="interconnect_split_ram_block_M9K_data_a_in_[17:0]" output="prim_ram_512x18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_512x18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_9K_512x18_composite_prim_ram_1x(512x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{9}" class="memory" name="prim_ram_512x18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="9" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.portawe"/>
              <delay_constant in_port="prim_ram_512x18.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_512x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_512x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_512x18[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_512x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_512x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_512x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_512x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_512x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_512x18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_512x18[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_512x18[0].clk_portain[0] prim_ram_512x18[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[8:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[8:0]" output="prim_ram_512x18[0].portaaddr[8:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[8:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].portaaddr[8:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[17:0]" name="interconnect_split_ram_block_M9K_data_a_in_[17:0]" output="prim_ram_512x18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[17:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_512x18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_9K_256x36_composite_prim_ram_1x(256x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{8}" class="memory" name="prim_ram_256x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="8" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_256x36.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_256x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.portawe"/>
              <delay_constant in_port="prim_ram_256x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_256x36.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_256x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_256x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_256x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_256x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_256x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_256x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_256x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_256x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_256x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_256x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_256x36[0].clk_portain[0] prim_ram_256x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[7:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[7:0]" output="prim_ram_256x36[0].portaaddr[7:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[7:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].portaaddr[7:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_256x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_256x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_9K_256x36_composite_prim_ram_1x(256x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{8}" class="memory" name="prim_ram_256x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="8" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.portawe"/>
              <delay_constant in_port="prim_ram_256x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_256x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_256x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_256x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_256x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_256x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_256x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_256x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_256x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_256x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_256x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_256x36[0].clk_portain[0] prim_ram_256x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[7:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[7:0]" output="prim_ram_256x36[0].portaaddr[7:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[7:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].portaaddr[7:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_256x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_256x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_8K_8Kx1_composite_prim_ram_1x(8Kx1)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{13}" class="memory" name="prim_ram_8Kx1" num_pb="1">
              <input name="portadatain" num_pins="1" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="13" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="1" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_8Kx1.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_8Kx1.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.portawe"/>
              <delay_constant in_port="prim_ram_8Kx1.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_8Kx1.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_8Kx1[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_8Kx1[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_8Kx1[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_8Kx1[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_8Kx1[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_8Kx1[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_8Kx1[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_8Kx1[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_8Kx1[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_8Kx1[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_8Kx1[0].clk_portain[0] prim_ram_8Kx1[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]" output="prim_ram_8Kx1[0].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].portaaddr[12:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[0]" name="interconnect_split_ram_block_M9K_data_a_in_[0]" output="prim_ram_8Kx1[0].portadatain[0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].portadatain[0]"/>
              </direct>
              <direct input="prim_ram_8Kx1[0].portadataout[0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_8K_8Kx1_composite_prim_ram_1x(8Kx1)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{13}" class="memory" name="prim_ram_8Kx1" num_pb="1">
              <input name="portadatain" num_pins="1" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="13" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="1" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.portawe"/>
              <delay_constant in_port="prim_ram_8Kx1.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_8Kx1[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_8Kx1[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_8Kx1[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_8Kx1[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_8Kx1[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_8Kx1[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_8Kx1[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_8Kx1[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_8Kx1[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_8Kx1[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_8Kx1[0].clk_portain[0] prim_ram_8Kx1[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]" output="prim_ram_8Kx1[0].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].portaaddr[12:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[0]" name="interconnect_split_ram_block_M9K_data_a_in_[0]" output="prim_ram_8Kx1[0].portadatain[0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].portadatain[0]"/>
              </direct>
              <direct input="prim_ram_8Kx1[0].portadataout[0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_8K_4Kx2_composite_prim_ram_1x(4Kx2)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{12}" class="memory" name="prim_ram_4Kx2" num_pb="1">
              <input name="portadatain" num_pins="2" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="12" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="2" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_4Kx2.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_4Kx2.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.portawe"/>
              <delay_constant in_port="prim_ram_4Kx2.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_4Kx2.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_4Kx2[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_4Kx2[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_4Kx2[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_4Kx2[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_4Kx2[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_4Kx2[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_4Kx2[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_4Kx2[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_4Kx2[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_4Kx2[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_4Kx2[0].clk_portain[0] prim_ram_4Kx2[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[11:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[11:0]" output="prim_ram_4Kx2[0].portaaddr[11:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[11:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].portaaddr[11:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[1:0]" name="interconnect_split_ram_block_M9K_data_a_in_[1:0]" output="prim_ram_4Kx2[0].portadatain[1:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[1:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].portadatain[1:0]"/>
              </direct>
              <direct input="prim_ram_4Kx2[0].portadataout[1:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[1:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_8K_4Kx2_composite_prim_ram_1x(4Kx2)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{12}" class="memory" name="prim_ram_4Kx2" num_pb="1">
              <input name="portadatain" num_pins="2" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="12" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="2" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.portawe"/>
              <delay_constant in_port="prim_ram_4Kx2.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_4Kx2[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_4Kx2[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_4Kx2[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_4Kx2[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_4Kx2[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_4Kx2[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_4Kx2[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_4Kx2[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_4Kx2[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_4Kx2[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_4Kx2[0].clk_portain[0] prim_ram_4Kx2[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[11:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[11:0]" output="prim_ram_4Kx2[0].portaaddr[11:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[11:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].portaaddr[11:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[1:0]" name="interconnect_split_ram_block_M9K_data_a_in_[1:0]" output="prim_ram_4Kx2[0].portadatain[1:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[1:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].portadatain[1:0]"/>
              </direct>
              <direct input="prim_ram_4Kx2[0].portadataout[1:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[1:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_8K_2Kx4_composite_prim_ram_1x(2Kx4)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{11}" class="memory" name="prim_ram_2Kx4" num_pb="1">
              <input name="portadatain" num_pins="4" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="11" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="4" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_2Kx4.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_2Kx4.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.portawe"/>
              <delay_constant in_port="prim_ram_2Kx4.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_2Kx4.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_2Kx4[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_2Kx4[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_2Kx4[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_2Kx4[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_2Kx4[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_2Kx4[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_2Kx4[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_2Kx4[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_2Kx4[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_2Kx4[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_2Kx4[0].clk_portain[0] prim_ram_2Kx4[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[10:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[10:0]" output="prim_ram_2Kx4[0].portaaddr[10:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[10:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].portaaddr[10:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[3:0]" name="interconnect_split_ram_block_M9K_data_a_in_[3:0]" output="prim_ram_2Kx4[0].portadatain[3:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[3:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].portadatain[3:0]"/>
              </direct>
              <direct input="prim_ram_2Kx4[0].portadataout[3:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[3:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_8K_2Kx4_composite_prim_ram_1x(2Kx4)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{11}" class="memory" name="prim_ram_2Kx4" num_pb="1">
              <input name="portadatain" num_pins="4" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="11" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="4" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.portawe"/>
              <delay_constant in_port="prim_ram_2Kx4.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_2Kx4[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_2Kx4[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_2Kx4[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_2Kx4[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_2Kx4[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_2Kx4[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_2Kx4[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_2Kx4[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_2Kx4[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_2Kx4[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_2Kx4[0].clk_portain[0] prim_ram_2Kx4[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[10:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[10:0]" output="prim_ram_2Kx4[0].portaaddr[10:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[10:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].portaaddr[10:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[3:0]" name="interconnect_split_ram_block_M9K_data_a_in_[3:0]" output="prim_ram_2Kx4[0].portadatain[3:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[3:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].portadatain[3:0]"/>
              </direct>
              <direct input="prim_ram_2Kx4[0].portadataout[3:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[3:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_4K_128x36_composite_prim_ram_1x(128x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{7}" class="memory" name="prim_ram_128x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="7" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_128x36.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_128x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.portawe"/>
              <delay_constant in_port="prim_ram_128x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_128x36.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_128x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_128x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_128x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_128x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_128x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_128x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_128x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_128x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_128x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_128x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_128x36[0].clk_portain[0] prim_ram_128x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[6:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[6:0]" output="prim_ram_128x36[0].portaaddr[6:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[6:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].portaaddr[6:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_128x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_128x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_4K_128x36_composite_prim_ram_1x(128x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{7}" class="memory" name="prim_ram_128x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="7" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.portawe"/>
              <delay_constant in_port="prim_ram_128x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_128x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_128x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_128x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_128x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_128x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_128x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_128x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_128x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_128x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_128x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_128x36[0].clk_portain[0] prim_ram_128x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[6:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[6:0]" output="prim_ram_128x36[0].portaaddr[6:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[6:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].portaaddr[6:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_128x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_128x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_2K_64x36_composite_prim_ram_1x(64x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{6}" class="memory" name="prim_ram_64x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="6" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_64x36.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_64x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.portawe"/>
              <delay_constant in_port="prim_ram_64x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_64x36.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_64x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_64x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_64x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_64x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_64x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_64x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_64x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_64x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_64x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_64x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_64x36[0].clk_portain[0] prim_ram_64x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[5:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[5:0]" output="prim_ram_64x36[0].portaaddr[5:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[5:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].portaaddr[5:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_64x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_64x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_2K_64x36_composite_prim_ram_1x(64x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{6}" class="memory" name="prim_ram_64x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="6" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.portawe"/>
              <delay_constant in_port="prim_ram_64x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_64x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_64x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_64x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_64x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_64x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_64x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_64x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_64x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_64x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_64x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_64x36[0].clk_portain[0] prim_ram_64x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[5:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[5:0]" output="prim_ram_64x36[0].portaaddr[5:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[5:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].portaaddr[5:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_64x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_64x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_1K_32x36_composite_prim_ram_1x(32x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{5}" class="memory" name="prim_ram_32x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="5" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_32x36.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_32x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.portawe"/>
              <delay_constant in_port="prim_ram_32x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_32x36.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_32x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_32x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_32x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_32x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_32x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_32x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_32x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_32x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_32x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_32x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_32x36[0].clk_portain[0] prim_ram_32x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[4:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[4:0]" output="prim_ram_32x36[0].portaaddr[4:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[4:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].portaaddr[4:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_32x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_32x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_1K_32x36_composite_prim_ram_1x(32x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{5}" class="memory" name="prim_ram_32x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="5" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.portawe"/>
              <delay_constant in_port="prim_ram_32x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_32x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_32x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_32x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_32x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_32x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_32x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_32x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_32x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_32x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_32x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_32x36[0].clk_portain[0] prim_ram_32x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[4:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[4:0]" output="prim_ram_32x36[0].portaaddr[4:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[4:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].portaaddr[4:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_32x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_32x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_576_16x36_composite_prim_ram_1x(16x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{4}" class="memory" name="prim_ram_16x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="4" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_16x36.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_16x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.portawe"/>
              <delay_constant in_port="prim_ram_16x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_16x36.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_16x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_16x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_16x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_16x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_16x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_16x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_16x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_16x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_16x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_16x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_16x36[0].clk_portain[0] prim_ram_16x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[3:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[3:0]" output="prim_ram_16x36[0].portaaddr[3:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[3:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].portaaddr[3:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_16x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_16x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_576_16x36_composite_prim_ram_1x(16x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{4}" class="memory" name="prim_ram_16x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="4" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.portawe"/>
              <delay_constant in_port="prim_ram_16x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_16x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_16x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_16x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_16x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_16x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_16x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_16x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_16x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_16x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_16x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_16x36[0].clk_portain[0] prim_ram_16x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[3:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[3:0]" output="prim_ram_16x36[0].portaaddr[3:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[3:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].portaaddr[3:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_16x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_16x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_288_8x36_composite_prim_ram_1x(8x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{3}" class="memory" name="prim_ram_8x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="3" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_8x36.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_8x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.portawe"/>
              <delay_constant in_port="prim_ram_8x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_8x36.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_8x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_8x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_8x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_8x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_8x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_8x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_8x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_8x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_8x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_8x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_8x36[0].clk_portain[0] prim_ram_8x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[2:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[2:0]" output="prim_ram_8x36[0].portaaddr[2:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[2:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].portaaddr[2:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_8x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_8x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_288_8x36_composite_prim_ram_1x(8x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{3}" class="memory" name="prim_ram_8x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="3" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.portawe"/>
              <delay_constant in_port="prim_ram_8x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_8x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_8x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_8x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_8x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_8x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_8x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_8x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_8x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_8x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_8x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_8x36[0].clk_portain[0] prim_ram_8x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[2:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[2:0]" output="prim_ram_8x36[0].portaaddr[2:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[2:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].portaaddr[2:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_8x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_8x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_144_4x36_composite_prim_ram_1x(4x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{2}" class="memory" name="prim_ram_4x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="2" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_4x36.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_4x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.portawe"/>
              <delay_constant in_port="prim_ram_4x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_4x36.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_4x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_4x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_4x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_4x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_4x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_4x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_4x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_4x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_4x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_4x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_4x36[0].clk_portain[0] prim_ram_4x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[1:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[1:0]" output="prim_ram_4x36[0].portaaddr[1:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[1:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].portaaddr[1:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_4x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_4x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_144_4x36_composite_prim_ram_1x(4x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{2}" class="memory" name="prim_ram_4x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="2" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.portawe"/>
              <delay_constant in_port="prim_ram_4x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_4x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_4x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_4x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_4x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_4x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_4x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_4x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_4x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_4x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_4x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_4x36[0].clk_portain[0] prim_ram_4x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[1:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[1:0]" output="prim_ram_4x36[0].portaaddr[1:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[1:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].portaaddr[1:0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_4x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_4x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_72_2x36_composite_prim_ram_1x(2x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{1}" class="memory" name="prim_ram_2x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_2x36.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_2x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.portawe"/>
              <delay_constant in_port="prim_ram_2x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_2x36.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_2x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_2x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_2x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_2x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_2x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_2x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_2x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_2x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_2x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_2x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_2x36[0].clk_portain[0] prim_ram_2x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[0]" name="interconnect_common_ram_block_M9K_addr_a_in_[0]" output="prim_ram_2x36[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].portaaddr[0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_2x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_2x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_72_2x36_composite_prim_ram_1x(2x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{1}" class="memory" name="prim_ram_2x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.portawe"/>
              <delay_constant in_port="prim_ram_2x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_2x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_2x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_2x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_2x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_2x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_2x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_2x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_2x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_2x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_2x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_2x36[0].clk_portain[0] prim_ram_2x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[0]" name="interconnect_common_ram_block_M9K_addr_a_in_[0]" output="prim_ram_2x36[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].portaaddr[0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_2x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_2x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_36_1x36_composite_prim_ram_1x(1x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{0}" class="memory" name="prim_ram_1x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_1x36.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_1x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.portawe"/>
              <delay_constant in_port="prim_ram_1x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_1x36.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_1x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_1x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_1x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_1x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_1x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_1x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_1x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_1x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_1x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_1x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_1x36[0].clk_portain[0] prim_ram_1x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[0]" name="interconnect_common_ram_block_M9K_addr_a_in_[0]" output="prim_ram_1x36[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].portaaddr[0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_1x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_1x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_36_1x36_composite_prim_ram_1x(1x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{0}" class="memory" name="prim_ram_1x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.portawe" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.portawe"/>
              <delay_constant in_port="prim_ram_1x36.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.portawe" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_1x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_1x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_1x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_1x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_1x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_1x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_1x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_1x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15:8]" name="interconnect_common_ram_block_M9K_control_in_[15:8]" output="prim_ram_1x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[15:8]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_1x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_1x36[0].clk_portain[0] prim_ram_1x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[0]" name="interconnect_common_ram_block_M9K_addr_a_in_[0]" output="prim_ram_1x36[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].portaaddr[0]"/>
              </complete>
              <direct input="ram_block_M9K.data_a_in[35:0]" name="interconnect_split_ram_block_M9K_data_a_in_[35:0]" output="prim_ram_1x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M9K.data_a_in[35:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_1x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_9K_1Kx9_composite_prim_ram_1x(1Kx9)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{10}" class="memory" name="prim_ram_1Kx9" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="10" port_class="address1"/>
              <output name="portadataout" num_pins="9" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_1Kx9.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_1Kx9.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.portaaddr"/>
              <delay_constant in_port="prim_ram_1Kx9.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_1Kx9.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_1Kx9[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_1Kx9[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_1Kx9[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_1Kx9[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_1Kx9[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_1Kx9[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_1Kx9[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_1Kx9[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_1Kx9[0].clk_portain[0] prim_ram_1Kx9[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[9:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[9:0]" output="prim_ram_1Kx9[0].portaaddr[9:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[9:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].portaaddr[9:0]"/>
              </complete>
              <direct input="prim_ram_1Kx9[0].portadataout[8:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[8:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_9K_1Kx9_composite_prim_ram_1x(1Kx9)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{10}" class="memory" name="prim_ram_1Kx9" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="10" port_class="address1"/>
              <output name="portadataout" num_pins="9" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx9.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1Kx9.portaaddr"/>
              <delay_constant in_port="prim_ram_1Kx9.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx9.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1Kx9.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx9.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_1Kx9[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_1Kx9[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_1Kx9[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_1Kx9[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_1Kx9[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_1Kx9[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_1Kx9[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_1Kx9[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_1Kx9[0].clk_portain[0] prim_ram_1Kx9[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[9:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[9:0]" output="prim_ram_1Kx9[0].portaaddr[9:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[9:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1Kx9[0].portaaddr[9:0]"/>
              </complete>
              <direct input="prim_ram_1Kx9[0].portadataout[8:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[8:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_9K_512x18_composite_prim_ram_1x(512x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{9}" class="memory" name="prim_ram_512x18" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="9" port_class="address1"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_512x18.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_512x18.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.portaaddr"/>
              <delay_constant in_port="prim_ram_512x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_512x18.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_512x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_512x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_512x18[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_512x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_512x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_512x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_512x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_512x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_512x18[0].clk_portain[0] prim_ram_512x18[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[8:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[8:0]" output="prim_ram_512x18[0].portaaddr[8:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[8:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].portaaddr[8:0]"/>
              </complete>
              <direct input="prim_ram_512x18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_9K_512x18_composite_prim_ram_1x(512x18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{9}" class="memory" name="prim_ram_512x18" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="9" port_class="address1"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x18.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_512x18.portaaddr"/>
              <delay_constant in_port="prim_ram_512x18.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <delay_constant in_port="prim_ram_512x18.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_512x18.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_512x18.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_512x18[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_512x18[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_512x18[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_512x18[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_512x18[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_512x18[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_512x18[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_512x18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_512x18[0].clk_portain[0] prim_ram_512x18[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[8:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[8:0]" output="prim_ram_512x18[0].portaaddr[8:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[8:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_512x18[0].portaaddr[8:0]"/>
              </complete>
              <direct input="prim_ram_512x18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[17:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_9K_256x36_composite_prim_ram_1x(256x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{8}" class="memory" name="prim_ram_256x36" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="8" port_class="address1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_256x36.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_256x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.portaaddr"/>
              <delay_constant in_port="prim_ram_256x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_256x36.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_256x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_256x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_256x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_256x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_256x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_256x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_256x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_256x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_256x36[0].clk_portain[0] prim_ram_256x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[7:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[7:0]" output="prim_ram_256x36[0].portaaddr[7:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[7:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].portaaddr[7:0]"/>
              </complete>
              <direct input="prim_ram_256x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_9K_256x36_composite_prim_ram_1x(256x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{8}" class="memory" name="prim_ram_256x36" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="8" port_class="address1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x36.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_256x36.portaaddr"/>
              <delay_constant in_port="prim_ram_256x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <delay_constant in_port="prim_ram_256x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_256x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_256x36.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_256x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_256x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_256x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_256x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_256x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_256x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_256x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_256x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_256x36[0].clk_portain[0] prim_ram_256x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[7:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[7:0]" output="prim_ram_256x36[0].portaaddr[7:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[7:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_256x36[0].portaaddr[7:0]"/>
              </complete>
              <direct input="prim_ram_256x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_8K_8Kx1_composite_prim_ram_1x(8Kx1)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{13}" class="memory" name="prim_ram_8Kx1" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="13" port_class="address1"/>
              <output name="portadataout" num_pins="1" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_8Kx1.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_8Kx1.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.portaaddr"/>
              <delay_constant in_port="prim_ram_8Kx1.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_8Kx1.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_8Kx1[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_8Kx1[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_8Kx1[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_8Kx1[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_8Kx1[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_8Kx1[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_8Kx1[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_8Kx1[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_8Kx1[0].clk_portain[0] prim_ram_8Kx1[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]" output="prim_ram_8Kx1[0].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].portaaddr[12:0]"/>
              </complete>
              <direct input="prim_ram_8Kx1[0].portadataout[0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_8K_8Kx1_composite_prim_ram_1x(8Kx1)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{13}" class="memory" name="prim_ram_8Kx1" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="13" port_class="address1"/>
              <output name="portadataout" num_pins="1" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx1.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8Kx1.portaaddr"/>
              <delay_constant in_port="prim_ram_8Kx1.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx1.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8Kx1.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx1.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_8Kx1[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_8Kx1[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_8Kx1[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_8Kx1[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_8Kx1[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_8Kx1[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_8Kx1[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_8Kx1[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_8Kx1[0].clk_portain[0] prim_ram_8Kx1[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]" output="prim_ram_8Kx1[0].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8Kx1[0].portaaddr[12:0]"/>
              </complete>
              <direct input="prim_ram_8Kx1[0].portadataout[0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_8K_4Kx2_composite_prim_ram_1x(4Kx2)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{12}" class="memory" name="prim_ram_4Kx2" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="12" port_class="address1"/>
              <output name="portadataout" num_pins="2" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_4Kx2.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_4Kx2.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.portaaddr"/>
              <delay_constant in_port="prim_ram_4Kx2.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_4Kx2.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_4Kx2[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_4Kx2[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_4Kx2[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_4Kx2[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_4Kx2[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_4Kx2[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_4Kx2[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_4Kx2[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_4Kx2[0].clk_portain[0] prim_ram_4Kx2[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[11:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[11:0]" output="prim_ram_4Kx2[0].portaaddr[11:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[11:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].portaaddr[11:0]"/>
              </complete>
              <direct input="prim_ram_4Kx2[0].portadataout[1:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[1:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_8K_4Kx2_composite_prim_ram_1x(4Kx2)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{12}" class="memory" name="prim_ram_4Kx2" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="12" port_class="address1"/>
              <output name="portadataout" num_pins="2" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx2.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4Kx2.portaaddr"/>
              <delay_constant in_port="prim_ram_4Kx2.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx2.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4Kx2.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx2.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_4Kx2[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_4Kx2[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_4Kx2[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_4Kx2[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_4Kx2[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_4Kx2[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_4Kx2[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_4Kx2[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_4Kx2[0].clk_portain[0] prim_ram_4Kx2[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[11:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[11:0]" output="prim_ram_4Kx2[0].portaaddr[11:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[11:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4Kx2[0].portaaddr[11:0]"/>
              </complete>
              <direct input="prim_ram_4Kx2[0].portadataout[1:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[1:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_8K_2Kx4_composite_prim_ram_1x(2Kx4)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{11}" class="memory" name="prim_ram_2Kx4" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="11" port_class="address1"/>
              <output name="portadataout" num_pins="4" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_2Kx4.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_2Kx4.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.portaaddr"/>
              <delay_constant in_port="prim_ram_2Kx4.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_2Kx4.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_2Kx4[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_2Kx4[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_2Kx4[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_2Kx4[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_2Kx4[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_2Kx4[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_2Kx4[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_2Kx4[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_2Kx4[0].clk_portain[0] prim_ram_2Kx4[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[10:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[10:0]" output="prim_ram_2Kx4[0].portaaddr[10:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[10:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].portaaddr[10:0]"/>
              </complete>
              <direct input="prim_ram_2Kx4[0].portadataout[3:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[3:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_8K_2Kx4_composite_prim_ram_1x(2Kx4)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{11}" class="memory" name="prim_ram_2Kx4" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="11" port_class="address1"/>
              <output name="portadataout" num_pins="4" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx4.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2Kx4.portaaddr"/>
              <delay_constant in_port="prim_ram_2Kx4.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx4.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2Kx4.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx4.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_2Kx4[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_2Kx4[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_2Kx4[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_2Kx4[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_2Kx4[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_2Kx4[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_2Kx4[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_2Kx4[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_2Kx4[0].clk_portain[0] prim_ram_2Kx4[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[10:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[10:0]" output="prim_ram_2Kx4[0].portaaddr[10:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[10:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2Kx4[0].portaaddr[10:0]"/>
              </complete>
              <direct input="prim_ram_2Kx4[0].portadataout[3:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[3:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_4K_128x36_composite_prim_ram_1x(128x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{7}" class="memory" name="prim_ram_128x36" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="7" port_class="address1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_128x36.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_128x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.portaaddr"/>
              <delay_constant in_port="prim_ram_128x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_128x36.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_128x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_128x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_128x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_128x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_128x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_128x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_128x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_128x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_128x36[0].clk_portain[0] prim_ram_128x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[6:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[6:0]" output="prim_ram_128x36[0].portaaddr[6:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[6:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].portaaddr[6:0]"/>
              </complete>
              <direct input="prim_ram_128x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_4K_128x36_composite_prim_ram_1x(128x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{7}" class="memory" name="prim_ram_128x36" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="7" port_class="address1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x36.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_128x36.portaaddr"/>
              <delay_constant in_port="prim_ram_128x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <delay_constant in_port="prim_ram_128x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_128x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_128x36.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_128x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_128x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_128x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_128x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_128x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_128x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_128x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_128x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_128x36[0].clk_portain[0] prim_ram_128x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[6:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[6:0]" output="prim_ram_128x36[0].portaaddr[6:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[6:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_128x36[0].portaaddr[6:0]"/>
              </complete>
              <direct input="prim_ram_128x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_2K_64x36_composite_prim_ram_1x(64x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{6}" class="memory" name="prim_ram_64x36" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="6" port_class="address1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_64x36.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_64x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.portaaddr"/>
              <delay_constant in_port="prim_ram_64x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_64x36.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_64x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_64x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_64x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_64x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_64x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_64x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_64x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_64x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_64x36[0].clk_portain[0] prim_ram_64x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[5:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[5:0]" output="prim_ram_64x36[0].portaaddr[5:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[5:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].portaaddr[5:0]"/>
              </complete>
              <direct input="prim_ram_64x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_2K_64x36_composite_prim_ram_1x(64x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{6}" class="memory" name="prim_ram_64x36" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="6" port_class="address1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x36.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_64x36.portaaddr"/>
              <delay_constant in_port="prim_ram_64x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <delay_constant in_port="prim_ram_64x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_64x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_64x36.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_64x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_64x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_64x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_64x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_64x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_64x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_64x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_64x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_64x36[0].clk_portain[0] prim_ram_64x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[5:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[5:0]" output="prim_ram_64x36[0].portaaddr[5:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[5:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_64x36[0].portaaddr[5:0]"/>
              </complete>
              <direct input="prim_ram_64x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_1K_32x36_composite_prim_ram_1x(32x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{5}" class="memory" name="prim_ram_32x36" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="5" port_class="address1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_32x36.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_32x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.portaaddr"/>
              <delay_constant in_port="prim_ram_32x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_32x36.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_32x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_32x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_32x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_32x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_32x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_32x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_32x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_32x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_32x36[0].clk_portain[0] prim_ram_32x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[4:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[4:0]" output="prim_ram_32x36[0].portaaddr[4:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[4:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].portaaddr[4:0]"/>
              </complete>
              <direct input="prim_ram_32x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_1K_32x36_composite_prim_ram_1x(32x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{5}" class="memory" name="prim_ram_32x36" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="5" port_class="address1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x36.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_32x36.portaaddr"/>
              <delay_constant in_port="prim_ram_32x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <delay_constant in_port="prim_ram_32x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_32x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_32x36.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_32x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_32x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_32x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_32x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_32x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_32x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_32x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_32x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_32x36[0].clk_portain[0] prim_ram_32x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[4:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[4:0]" output="prim_ram_32x36[0].portaaddr[4:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[4:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_32x36[0].portaaddr[4:0]"/>
              </complete>
              <direct input="prim_ram_32x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_576_16x36_composite_prim_ram_1x(16x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{4}" class="memory" name="prim_ram_16x36" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="4" port_class="address1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_16x36.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_16x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.portaaddr"/>
              <delay_constant in_port="prim_ram_16x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_16x36.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_16x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_16x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_16x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_16x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_16x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_16x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_16x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_16x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_16x36[0].clk_portain[0] prim_ram_16x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[3:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[3:0]" output="prim_ram_16x36[0].portaaddr[3:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[3:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].portaaddr[3:0]"/>
              </complete>
              <direct input="prim_ram_16x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_576_16x36_composite_prim_ram_1x(16x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{4}" class="memory" name="prim_ram_16x36" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="4" port_class="address1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x36.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_16x36.portaaddr"/>
              <delay_constant in_port="prim_ram_16x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <delay_constant in_port="prim_ram_16x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_16x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_16x36.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_16x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_16x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_16x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_16x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_16x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_16x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_16x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_16x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_16x36[0].clk_portain[0] prim_ram_16x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[3:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[3:0]" output="prim_ram_16x36[0].portaaddr[3:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[3:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_16x36[0].portaaddr[3:0]"/>
              </complete>
              <direct input="prim_ram_16x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_288_8x36_composite_prim_ram_1x(8x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{3}" class="memory" name="prim_ram_8x36" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="3" port_class="address1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_8x36.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_8x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.portaaddr"/>
              <delay_constant in_port="prim_ram_8x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_8x36.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_8x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_8x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_8x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_8x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_8x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_8x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_8x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_8x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_8x36[0].clk_portain[0] prim_ram_8x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[2:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[2:0]" output="prim_ram_8x36[0].portaaddr[2:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[2:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].portaaddr[2:0]"/>
              </complete>
              <direct input="prim_ram_8x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_288_8x36_composite_prim_ram_1x(8x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{3}" class="memory" name="prim_ram_8x36" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="3" port_class="address1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x36.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_8x36.portaaddr"/>
              <delay_constant in_port="prim_ram_8x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <delay_constant in_port="prim_ram_8x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_8x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_8x36.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_8x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_8x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_8x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_8x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_8x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_8x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_8x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_8x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_8x36[0].clk_portain[0] prim_ram_8x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[2:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[2:0]" output="prim_ram_8x36[0].portaaddr[2:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[2:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_8x36[0].portaaddr[2:0]"/>
              </complete>
              <direct input="prim_ram_8x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_144_4x36_composite_prim_ram_1x(4x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{2}" class="memory" name="prim_ram_4x36" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="2" port_class="address1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_4x36.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_4x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.portaaddr"/>
              <delay_constant in_port="prim_ram_4x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_4x36.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_4x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_4x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_4x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_4x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_4x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_4x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_4x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_4x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_4x36[0].clk_portain[0] prim_ram_4x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[1:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[1:0]" output="prim_ram_4x36[0].portaaddr[1:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[1:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].portaaddr[1:0]"/>
              </complete>
              <direct input="prim_ram_4x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_144_4x36_composite_prim_ram_1x(4x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{2}" class="memory" name="prim_ram_4x36" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="2" port_class="address1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x36.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_4x36.portaaddr"/>
              <delay_constant in_port="prim_ram_4x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <delay_constant in_port="prim_ram_4x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_4x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_4x36.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_4x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_4x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_4x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_4x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_4x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_4x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_4x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_4x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_4x36[0].clk_portain[0] prim_ram_4x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[1:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[1:0]" output="prim_ram_4x36[0].portaaddr[1:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[1:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_4x36[0].portaaddr[1:0]"/>
              </complete>
              <direct input="prim_ram_4x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_72_2x36_composite_prim_ram_1x(2x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{1}" class="memory" name="prim_ram_2x36" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_2x36.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_2x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.portaaddr"/>
              <delay_constant in_port="prim_ram_2x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_2x36.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_2x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_2x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_2x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_2x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_2x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_2x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_2x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_2x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_2x36[0].clk_portain[0] prim_ram_2x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[0]" name="interconnect_common_ram_block_M9K_addr_a_in_[0]" output="prim_ram_2x36[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].portaaddr[0]"/>
              </complete>
              <direct input="prim_ram_2x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_72_2x36_composite_prim_ram_1x(2x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{1}" class="memory" name="prim_ram_2x36" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x36.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_2x36.portaaddr"/>
              <delay_constant in_port="prim_ram_2x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <delay_constant in_port="prim_ram_2x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_2x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_2x36.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_2x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_2x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_2x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_2x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_2x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_2x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_2x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_2x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_2x36[0].clk_portain[0] prim_ram_2x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[0]" name="interconnect_common_ram_block_M9K_addr_a_in_[0]" output="prim_ram_2x36[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_2x36[0].portaaddr[0]"/>
              </complete>
              <direct input="prim_ram_2x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_36_1x36_composite_prim_ram_1x(1x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{0}" class="memory" name="prim_ram_1x36" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_1x36.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_1x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.portaaddr"/>
              <delay_constant in_port="prim_ram_1x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_1x36.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_1x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_1x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_1x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_1x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_1x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_1x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_1x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_1x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_1x36[0].clk_portain[0] prim_ram_1x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[0]" name="interconnect_common_ram_block_M9K_addr_a_in_[0]" output="prim_ram_1x36[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].portaaddr[0]"/>
              </complete>
              <direct input="prim_ram_1x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_36_1x36_composite_prim_ram_1x(1x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{0}" class="memory" name="prim_ram_1x36" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x36.portaaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_1x36.portaaddr"/>
              <delay_constant in_port="prim_ram_1x36.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <delay_constant in_port="prim_ram_1x36.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_1x36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.ena2" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_1x36.portaaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_1x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_1x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_1x36[0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_1x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_1x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[5]" name="interconnect_common_ram_block_M9K_control_in_[5]" output="prim_ram_1x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[6]" name="interconnect_common_ram_block_M9K_control_in_[6]" output="prim_ram_1x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[6]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[7]" name="interconnect_common_ram_block_M9K_control_in_[7]" output="prim_ram_1x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[7]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_1x36[0].clk_portain[0] prim_ram_1x36[0].clk_portaout[0] "/>
              <complete input="ram_block_M9K.addr_a_in[0]" name="interconnect_common_ram_block_M9K_addr_a_in_[0]" output="prim_ram_1x36[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_1x36[0].portaaddr[0]"/>
              </complete>
              <direct input="prim_ram_1x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M9K_data_out_1" output="ram_block_M9K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_mixed_width">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}" name="prim_ram_dual_port_mixed_width" num_pb="18">
              <input name="portadatain" num_pins="36"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="13"/>
              <input name="portbre" num_pins="1"/>
              <input name="portawe" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="13"/>
              <output name="portbdataout" num_pins="36"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1"/>
              <clock name="clk_portain" num_pins="1"/>
              <clock name="clk_portaout" num_pins="1"/>
              <clock name="clk_portbout" num_pins="1"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_dual_port_mixed_width.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_dual_port_mixed_width.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_dual_port_mixed_width.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_dual_port_mixed_width.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_dual_port_mixed_width.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_dual_port_mixed_width.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_dual_port_mixed_width.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_dual_port_mixed_width.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.portbaddr"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_dual_port_mixed_width.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_dual_port_mixed_width.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_dual_port_mixed_width.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_dual_port_mixed_width.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_dual_port_mixed_width.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_dual_port_mixed_width.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_dual_port_mixed_width.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_dual_port_mixed_width.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_dual_port_mixed_width[17:0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17:0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_dual_port_mixed_width[17:0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17:0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_dual_port_mixed_width[17:0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17:0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_dual_port_mixed_width[17:0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17:0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_dual_port_mixed_width[17:0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17:0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_dual_port_mixed_width[17:0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17:0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_dual_port_mixed_width[17:0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17:0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_dual_port_mixed_width[17:0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17:0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_dual_port_mixed_width[17:0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17:0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_dual_port_mixed_width[17:0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17:0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.data_b_in" name="interconnect_full_ram_block_M9K_data_b_in_0" output="">
                <delay_constant in_port="ram_block_M9K.data_b_in" max="4.83e-10" min="1.43e-10" out_port=""/>
              </complete>
              <complete input="ram_block_M9K.data_a_in" name="interconnect_full_ram_block_M9K_data_a_in_0" output="prim_ram_dual_port_mixed_width[17:0].portadatain[35:0] ">
                <delay_constant in_port="ram_block_M9K.data_a_in" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17:0].portadatain[35:0] "/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_dual_port_mixed_width[17:0].clk_portbin[0] prim_ram_dual_port_mixed_width[17:0].clk_portain[0] prim_ram_dual_port_mixed_width[17:0].clk_portaout[0] prim_ram_dual_port_mixed_width[17:0].clk_portbout[0] "/>
              <complete input="prim_ram_dual_port_mixed_width[17:0].eccstatus[2:0] " name="interconnect_full_ram_block_M9K_control_out_0" output="ram_block_M9K.control_out"/>
              <complete input="prim_ram_dual_port_mixed_width[17:0].portbdataout[35:0] " name="interconnect_full_ram_block_M9K_data_out_0" output="ram_block_M9K.data_out"/>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_0" output="prim_ram_dual_port_mixed_width[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[0].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_1" output="prim_ram_dual_port_mixed_width[1].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[1].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_2" output="prim_ram_dual_port_mixed_width[2].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[2].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_3" output="prim_ram_dual_port_mixed_width[3].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[3].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_4" output="prim_ram_dual_port_mixed_width[4].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[4].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_5" output="prim_ram_dual_port_mixed_width[5].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[5].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_6" output="prim_ram_dual_port_mixed_width[6].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[6].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_7" output="prim_ram_dual_port_mixed_width[7].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[7].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_8" output="prim_ram_dual_port_mixed_width[8].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[8].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_9" output="prim_ram_dual_port_mixed_width[9].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[9].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_10" output="prim_ram_dual_port_mixed_width[10].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[10].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_11" output="prim_ram_dual_port_mixed_width[11].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[11].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_12" output="prim_ram_dual_port_mixed_width[12].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[12].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_13" output="prim_ram_dual_port_mixed_width[13].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[13].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_14" output="prim_ram_dual_port_mixed_width[14].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[14].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_15" output="prim_ram_dual_port_mixed_width[15].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[15].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_16" output="prim_ram_dual_port_mixed_width[16].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[16].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_17" output="prim_ram_dual_port_mixed_width[17].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_0" output="prim_ram_dual_port_mixed_width[0].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[0].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_1" output="prim_ram_dual_port_mixed_width[1].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[1].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_2" output="prim_ram_dual_port_mixed_width[2].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[2].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_3" output="prim_ram_dual_port_mixed_width[3].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[3].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_4" output="prim_ram_dual_port_mixed_width[4].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[4].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_5" output="prim_ram_dual_port_mixed_width[5].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[5].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_6" output="prim_ram_dual_port_mixed_width[6].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[6].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_7" output="prim_ram_dual_port_mixed_width[7].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[7].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_8" output="prim_ram_dual_port_mixed_width[8].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[8].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_9" output="prim_ram_dual_port_mixed_width[9].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[9].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_10" output="prim_ram_dual_port_mixed_width[10].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[10].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_11" output="prim_ram_dual_port_mixed_width[11].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[11].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_12" output="prim_ram_dual_port_mixed_width[12].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[12].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_13" output="prim_ram_dual_port_mixed_width[13].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[13].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_14" output="prim_ram_dual_port_mixed_width[14].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[14].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_15" output="prim_ram_dual_port_mixed_width[15].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[15].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_16" output="prim_ram_dual_port_mixed_width[16].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[16].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_17" output="prim_ram_dual_port_mixed_width[17].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_0" output="prim_ram_dual_port_mixed_width[0].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[0].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_1" output="prim_ram_dual_port_mixed_width[1].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[1].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_2" output="prim_ram_dual_port_mixed_width[2].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[2].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_3" output="prim_ram_dual_port_mixed_width[3].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[3].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_4" output="prim_ram_dual_port_mixed_width[4].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[4].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_5" output="prim_ram_dual_port_mixed_width[5].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[5].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_6" output="prim_ram_dual_port_mixed_width[6].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[6].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_7" output="prim_ram_dual_port_mixed_width[7].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[7].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_8" output="prim_ram_dual_port_mixed_width[8].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[8].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_9" output="prim_ram_dual_port_mixed_width[9].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[9].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_10" output="prim_ram_dual_port_mixed_width[10].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[10].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_11" output="prim_ram_dual_port_mixed_width[11].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[11].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_12" output="prim_ram_dual_port_mixed_width[12].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[12].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_13" output="prim_ram_dual_port_mixed_width[13].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[13].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_14" output="prim_ram_dual_port_mixed_width[14].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[14].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_15" output="prim_ram_dual_port_mixed_width[15].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[15].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_16" output="prim_ram_dual_port_mixed_width[16].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[16].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_17" output="prim_ram_dual_port_mixed_width[17].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17].portbaddr[12:0]"/>
              </direct>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_mixed_width">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}" name="prim_ram_dual_port_mixed_width" num_pb="18">
              <input name="portadatain" num_pins="36"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="13"/>
              <input name="portbre" num_pins="1"/>
              <input name="portawe" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="13"/>
              <output name="portbdataout" num_pins="36"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1"/>
              <clock name="clk_portain" num_pins="1"/>
              <clock name="clk_portaout" num_pins="1"/>
              <clock name="clk_portbout" num_pins="1"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_dual_port_mixed_width.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_dual_port_mixed_width.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_dual_port_mixed_width.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_dual_port_mixed_width.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_dual_port_mixed_width.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_dual_port_mixed_width.portbaddr" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_dual_port_mixed_width.portbaddr"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.portadatain" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_dual_port_mixed_width.clr1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_dual_port_mixed_width.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_dual_port_mixed_width.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.ena1" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_dual_port_mixed_width.portbre" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_dual_port_mixed_width.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_dual_port_mixed_width.portbaddr" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_dual_port_mixed_width[17:0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17:0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_dual_port_mixed_width[17:0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17:0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[10]" name="interconnect_common_ram_block_M9K_control_in_[10]" output="prim_ram_dual_port_mixed_width[17:0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[10]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17:0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[11]" name="interconnect_common_ram_block_M9K_control_in_[11]" output="prim_ram_dual_port_mixed_width[17:0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[11]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17:0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[12]" name="interconnect_common_ram_block_M9K_control_in_[12]" output="prim_ram_dual_port_mixed_width[17:0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[12]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17:0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_dual_port_mixed_width[17:0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17:0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_dual_port_mixed_width[17:0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17:0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_dual_port_mixed_width[17:0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17:0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_dual_port_mixed_width[17:0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17:0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_dual_port_mixed_width[17:0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17:0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.data_b_in" name="interconnect_full_ram_block_M9K_data_b_in_0" output="">
                <delay_constant in_port="ram_block_M9K.data_b_in" max="4.83e-10" min="1.43e-10" out_port=""/>
              </complete>
              <complete input="ram_block_M9K.data_a_in" name="interconnect_full_ram_block_M9K_data_a_in_0" output="prim_ram_dual_port_mixed_width[17:0].portadatain[35:0] ">
                <delay_constant in_port="ram_block_M9K.data_a_in" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17:0].portadatain[35:0] "/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_dual_port_mixed_width[17:0].clk_portbin[0] prim_ram_dual_port_mixed_width[17:0].clk_portain[0] prim_ram_dual_port_mixed_width[17:0].clk_portaout[0] prim_ram_dual_port_mixed_width[17:0].clk_portbout[0] "/>
              <complete input="prim_ram_dual_port_mixed_width[17:0].eccstatus[2:0] " name="interconnect_full_ram_block_M9K_control_out_0" output="ram_block_M9K.control_out"/>
              <complete input="prim_ram_dual_port_mixed_width[17:0].portbdataout[35:0] " name="interconnect_full_ram_block_M9K_data_out_0" output="ram_block_M9K.data_out"/>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_0" output="prim_ram_dual_port_mixed_width[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[0].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_1" output="prim_ram_dual_port_mixed_width[1].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[1].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_2" output="prim_ram_dual_port_mixed_width[2].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[2].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_3" output="prim_ram_dual_port_mixed_width[3].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[3].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_4" output="prim_ram_dual_port_mixed_width[4].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[4].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_5" output="prim_ram_dual_port_mixed_width[5].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[5].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_6" output="prim_ram_dual_port_mixed_width[6].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[6].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_7" output="prim_ram_dual_port_mixed_width[7].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[7].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_8" output="prim_ram_dual_port_mixed_width[8].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[8].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_9" output="prim_ram_dual_port_mixed_width[9].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[9].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_10" output="prim_ram_dual_port_mixed_width[10].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[10].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_11" output="prim_ram_dual_port_mixed_width[11].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[11].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_12" output="prim_ram_dual_port_mixed_width[12].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[12].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_13" output="prim_ram_dual_port_mixed_width[13].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[13].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_14" output="prim_ram_dual_port_mixed_width[14].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[14].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_15" output="prim_ram_dual_port_mixed_width[15].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[15].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_16" output="prim_ram_dual_port_mixed_width[16].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[16].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[9:2]" name="interconnect_common_ram_block_M9K_control_in_[9:2]_17" output="prim_ram_dual_port_mixed_width[17].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[9:2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_0" output="prim_ram_dual_port_mixed_width[0].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[0].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_1" output="prim_ram_dual_port_mixed_width[1].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[1].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_2" output="prim_ram_dual_port_mixed_width[2].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[2].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_3" output="prim_ram_dual_port_mixed_width[3].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[3].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_4" output="prim_ram_dual_port_mixed_width[4].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[4].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_5" output="prim_ram_dual_port_mixed_width[5].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[5].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_6" output="prim_ram_dual_port_mixed_width[6].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[6].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_7" output="prim_ram_dual_port_mixed_width[7].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[7].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_8" output="prim_ram_dual_port_mixed_width[8].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[8].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_9" output="prim_ram_dual_port_mixed_width[9].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[9].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_10" output="prim_ram_dual_port_mixed_width[10].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[10].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_11" output="prim_ram_dual_port_mixed_width[11].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[11].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_12" output="prim_ram_dual_port_mixed_width[12].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[12].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_13" output="prim_ram_dual_port_mixed_width[13].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[13].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_14" output="prim_ram_dual_port_mixed_width[14].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[14].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_15" output="prim_ram_dual_port_mixed_width[15].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[15].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_16" output="prim_ram_dual_port_mixed_width[16].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[16].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_17" output="prim_ram_dual_port_mixed_width[17].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_0" output="prim_ram_dual_port_mixed_width[0].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[0].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_1" output="prim_ram_dual_port_mixed_width[1].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[1].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_2" output="prim_ram_dual_port_mixed_width[2].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[2].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_3" output="prim_ram_dual_port_mixed_width[3].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[3].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_4" output="prim_ram_dual_port_mixed_width[4].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[4].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_5" output="prim_ram_dual_port_mixed_width[5].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[5].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_6" output="prim_ram_dual_port_mixed_width[6].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[6].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_7" output="prim_ram_dual_port_mixed_width[7].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[7].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_8" output="prim_ram_dual_port_mixed_width[8].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[8].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_9" output="prim_ram_dual_port_mixed_width[9].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[9].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_10" output="prim_ram_dual_port_mixed_width[10].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[10].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_11" output="prim_ram_dual_port_mixed_width[11].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[11].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_12" output="prim_ram_dual_port_mixed_width[12].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[12].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_13" output="prim_ram_dual_port_mixed_width[13].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[13].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_14" output="prim_ram_dual_port_mixed_width[14].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[14].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_15" output="prim_ram_dual_port_mixed_width[15].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[15].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_16" output="prim_ram_dual_port_mixed_width[16].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[16].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_17" output="prim_ram_dual_port_mixed_width[17].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_dual_port_mixed_width[17].portbaddr[12:0]"/>
              </direct>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_mixed_width">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}" name="prim_ram_bidir_dual_port_mixed_width" num_pb="18">
              <input name="portadatain" num_pins="18"/>
              <input name="portare" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="13"/>
              <input name="portbaddr" num_pins="13"/>
              <input name="portbre" num_pins="1"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1"/>
              <input name="portbdatain" num_pins="18"/>
              <output name="portadataout" num_pins="18"/>
              <output name="portbdataout" num_pins="18"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1"/>
              <clock name="clk_portbin" num_pins="1"/>
              <clock name="clk_portain" num_pins="1"/>
              <clock name="clk_portaout" num_pins="1"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portare" value="6.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_bidir_dual_port_mixed_width.portadataout" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_bidir_dual_port_mixed_width.portbdataout" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_bidir_dual_port_mixed_width.eccstatus" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="9.8e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="9.8e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portbdatain"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portare" value="3e-11"/>
              <T_hold clock="clk_portaout" port="prim_ram_bidir_dual_port_mixed_width.portadataout" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_bidir_dual_port_mixed_width.portbdataout" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbout" port="prim_ram_bidir_dual_port_mixed_width.eccstatus" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_bidir_dual_port_mixed_width[17:0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_bidir_dual_port_mixed_width[17:0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_bidir_dual_port_mixed_width[17:0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_bidir_dual_port_mixed_width[17:0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_bidir_dual_port_mixed_width[17:0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_bidir_dual_port_mixed_width[17:0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_bidir_dual_port_mixed_width[17:0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_bidir_dual_port_mixed_width[17:0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_bidir_dual_port_mixed_width[17:0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_bidir_dual_port_mixed_width[17:0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_bidir_dual_port_mixed_width[17:0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_bidir_dual_port_mixed_width[17:0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.data_b_in" name="interconnect_full_ram_block_M9K_data_b_in_0" output="prim_ram_bidir_dual_port_mixed_width[17:0].portbdatain[17:0] ">
                <delay_constant in_port="ram_block_M9K.data_b_in" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].portbdatain[17:0] "/>
              </complete>
              <complete input="ram_block_M9K.data_a_in" name="interconnect_full_ram_block_M9K_data_a_in_0" output="prim_ram_bidir_dual_port_mixed_width[17:0].portadatain[17:0] ">
                <delay_constant in_port="ram_block_M9K.data_a_in" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].portadatain[17:0] "/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_bidir_dual_port_mixed_width[17:0].clk_portbout[0] prim_ram_bidir_dual_port_mixed_width[17:0].clk_portbin[0] prim_ram_bidir_dual_port_mixed_width[17:0].clk_portain[0] prim_ram_bidir_dual_port_mixed_width[17:0].clk_portaout[0] "/>
              <complete input="prim_ram_bidir_dual_port_mixed_width[17:0].eccstatus[2:0] " name="interconnect_full_ram_block_M9K_control_out_0" output="ram_block_M9K.control_out"/>
              <complete input="prim_ram_bidir_dual_port_mixed_width[17:0].portadataout[17:0] prim_ram_bidir_dual_port_mixed_width[17:0].portbdataout[17:0] " name="interconnect_full_ram_block_M9K_data_out_0" output="ram_block_M9K.data_out"/>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_0" output="prim_ram_bidir_dual_port_mixed_width[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[0].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_1" output="prim_ram_bidir_dual_port_mixed_width[1].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[1].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_2" output="prim_ram_bidir_dual_port_mixed_width[2].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[2].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_3" output="prim_ram_bidir_dual_port_mixed_width[3].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[3].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_4" output="prim_ram_bidir_dual_port_mixed_width[4].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[4].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_5" output="prim_ram_bidir_dual_port_mixed_width[5].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[5].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_6" output="prim_ram_bidir_dual_port_mixed_width[6].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[6].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_7" output="prim_ram_bidir_dual_port_mixed_width[7].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[7].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_8" output="prim_ram_bidir_dual_port_mixed_width[8].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[8].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_9" output="prim_ram_bidir_dual_port_mixed_width[9].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[9].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_10" output="prim_ram_bidir_dual_port_mixed_width[10].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[10].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_11" output="prim_ram_bidir_dual_port_mixed_width[11].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[11].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_12" output="prim_ram_bidir_dual_port_mixed_width[12].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[12].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_13" output="prim_ram_bidir_dual_port_mixed_width[13].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[13].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_14" output="prim_ram_bidir_dual_port_mixed_width[14].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[14].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_15" output="prim_ram_bidir_dual_port_mixed_width[15].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[15].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_16" output="prim_ram_bidir_dual_port_mixed_width[16].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[16].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_17" output="prim_ram_bidir_dual_port_mixed_width[17].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_0" output="prim_ram_bidir_dual_port_mixed_width[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[0].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_1" output="prim_ram_bidir_dual_port_mixed_width[1].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[1].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_2" output="prim_ram_bidir_dual_port_mixed_width[2].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[2].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_3" output="prim_ram_bidir_dual_port_mixed_width[3].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[3].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_4" output="prim_ram_bidir_dual_port_mixed_width[4].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[4].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_5" output="prim_ram_bidir_dual_port_mixed_width[5].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[5].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_6" output="prim_ram_bidir_dual_port_mixed_width[6].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[6].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_7" output="prim_ram_bidir_dual_port_mixed_width[7].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[7].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_8" output="prim_ram_bidir_dual_port_mixed_width[8].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[8].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_9" output="prim_ram_bidir_dual_port_mixed_width[9].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[9].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_10" output="prim_ram_bidir_dual_port_mixed_width[10].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[10].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_11" output="prim_ram_bidir_dual_port_mixed_width[11].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[11].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_12" output="prim_ram_bidir_dual_port_mixed_width[12].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[12].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_13" output="prim_ram_bidir_dual_port_mixed_width[13].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[13].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_14" output="prim_ram_bidir_dual_port_mixed_width[14].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[14].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_15" output="prim_ram_bidir_dual_port_mixed_width[15].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[15].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_16" output="prim_ram_bidir_dual_port_mixed_width[16].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[16].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_17" output="prim_ram_bidir_dual_port_mixed_width[17].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_0" output="prim_ram_bidir_dual_port_mixed_width[0].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[0].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_1" output="prim_ram_bidir_dual_port_mixed_width[1].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[1].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_2" output="prim_ram_bidir_dual_port_mixed_width[2].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[2].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_3" output="prim_ram_bidir_dual_port_mixed_width[3].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[3].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_4" output="prim_ram_bidir_dual_port_mixed_width[4].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[4].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_5" output="prim_ram_bidir_dual_port_mixed_width[5].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[5].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_6" output="prim_ram_bidir_dual_port_mixed_width[6].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[6].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_7" output="prim_ram_bidir_dual_port_mixed_width[7].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[7].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_8" output="prim_ram_bidir_dual_port_mixed_width[8].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[8].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_9" output="prim_ram_bidir_dual_port_mixed_width[9].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[9].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_10" output="prim_ram_bidir_dual_port_mixed_width[10].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[10].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_11" output="prim_ram_bidir_dual_port_mixed_width[11].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[11].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_12" output="prim_ram_bidir_dual_port_mixed_width[12].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[12].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_13" output="prim_ram_bidir_dual_port_mixed_width[13].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[13].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_14" output="prim_ram_bidir_dual_port_mixed_width[14].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[14].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_15" output="prim_ram_bidir_dual_port_mixed_width[15].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[15].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_16" output="prim_ram_bidir_dual_port_mixed_width[16].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[16].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_17" output="prim_ram_bidir_dual_port_mixed_width[17].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_0" output="prim_ram_bidir_dual_port_mixed_width[0].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[0].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_1" output="prim_ram_bidir_dual_port_mixed_width[1].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[1].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_2" output="prim_ram_bidir_dual_port_mixed_width[2].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[2].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_3" output="prim_ram_bidir_dual_port_mixed_width[3].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[3].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_4" output="prim_ram_bidir_dual_port_mixed_width[4].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[4].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_5" output="prim_ram_bidir_dual_port_mixed_width[5].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[5].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_6" output="prim_ram_bidir_dual_port_mixed_width[6].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[6].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_7" output="prim_ram_bidir_dual_port_mixed_width[7].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[7].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_8" output="prim_ram_bidir_dual_port_mixed_width[8].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[8].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_9" output="prim_ram_bidir_dual_port_mixed_width[9].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[9].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_10" output="prim_ram_bidir_dual_port_mixed_width[10].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[10].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_11" output="prim_ram_bidir_dual_port_mixed_width[11].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[11].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_12" output="prim_ram_bidir_dual_port_mixed_width[12].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[12].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_13" output="prim_ram_bidir_dual_port_mixed_width[13].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[13].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_14" output="prim_ram_bidir_dual_port_mixed_width[14].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[14].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_15" output="prim_ram_bidir_dual_port_mixed_width[15].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[15].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_16" output="prim_ram_bidir_dual_port_mixed_width[16].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[16].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_17" output="prim_ram_bidir_dual_port_mixed_width[17].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17].portbaddr[12:0]"/>
              </direct>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_mixed_width">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}" name="prim_ram_bidir_dual_port_mixed_width" num_pb="18">
              <input name="portadatain" num_pins="18"/>
              <input name="portare" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="13"/>
              <input name="portbaddr" num_pins="13"/>
              <input name="portbre" num_pins="1"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1"/>
              <input name="portbdatain" num_pins="18"/>
              <output name="portadataout" num_pins="18"/>
              <output name="portbdataout" num_pins="18"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1"/>
              <clock name="clk_portbin" num_pins="1"/>
              <clock name="clk_portain" num_pins="1"/>
              <clock name="clk_portaout" num_pins="1"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portadatain" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portare" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.clr0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portaaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portaaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbaddr" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbre" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.clr1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbbyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbwe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.ena2" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.ena3" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.ena0" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.ena1" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbaddrstall" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portabyteenamasks" value="6.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portawe" value="6.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbdatain" value="6.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portare"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="6.9e-11" min="6.9e-11" port="prim_ram_bidir_dual_port_mixed_width.portbdatain"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portadatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portare" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.clr0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portaaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portaaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbaddr" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbre" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.clr1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbbyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbwe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena2" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena3" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena0" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena1" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbaddrstall" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portabyteenamasks" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portawe" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbdatain" max="1.053e-09" min="1.022e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portadatain" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portare" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.clr0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portaaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portaaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbaddr" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbre" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.clr1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbbyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbwe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.ena2" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.ena3" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.ena0" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.ena1" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbaddrstall" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portabyteenamasks" value="3e-11"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portawe" value="3e-11"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbdatain" value="3e-11"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M9K.control_in[0]" name="interconnect_common_ram_block_M9K_control_in_[0]" output="prim_ram_bidir_dual_port_mixed_width[17:0].portare[0]">
                <delay_constant in_port="ram_block_M9K.control_in[0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].portare[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[1]" name="interconnect_common_ram_block_M9K_control_in_[1]" output="prim_ram_bidir_dual_port_mixed_width[17:0].clr0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[1]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[2]" name="interconnect_common_ram_block_M9K_control_in_[2]" output="prim_ram_bidir_dual_port_mixed_width[17:0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[2]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[3]" name="interconnect_common_ram_block_M9K_control_in_[3]" output="prim_ram_bidir_dual_port_mixed_width[17:0].portbre[0]">
                <delay_constant in_port="ram_block_M9K.control_in[3]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[4]" name="interconnect_common_ram_block_M9K_control_in_[4]" output="prim_ram_bidir_dual_port_mixed_width[17:0].clr1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[4]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[13]" name="interconnect_common_ram_block_M9K_control_in_[13]" output="prim_ram_bidir_dual_port_mixed_width[17:0].portbwe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[13]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[14]" name="interconnect_common_ram_block_M9K_control_in_[14]" output="prim_ram_bidir_dual_port_mixed_width[17:0].ena2[0]">
                <delay_constant in_port="ram_block_M9K.control_in[14]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[15]" name="interconnect_common_ram_block_M9K_control_in_[15]" output="prim_ram_bidir_dual_port_mixed_width[17:0].ena3[0]">
                <delay_constant in_port="ram_block_M9K.control_in[15]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[16]" name="interconnect_common_ram_block_M9K_control_in_[16]" output="prim_ram_bidir_dual_port_mixed_width[17:0].ena0[0]">
                <delay_constant in_port="ram_block_M9K.control_in[16]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[17]" name="interconnect_common_ram_block_M9K_control_in_[17]" output="prim_ram_bidir_dual_port_mixed_width[17:0].ena1[0]">
                <delay_constant in_port="ram_block_M9K.control_in[17]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[18]" name="interconnect_common_ram_block_M9K_control_in_[18]" output="prim_ram_bidir_dual_port_mixed_width[17:0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M9K.control_in[18]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M9K.control_in[27]" name="interconnect_common_ram_block_M9K_control_in_[27]" output="prim_ram_bidir_dual_port_mixed_width[17:0].portawe[0]">
                <delay_constant in_port="ram_block_M9K.control_in[27]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M9K.data_b_in" name="interconnect_full_ram_block_M9K_data_b_in_0" output="prim_ram_bidir_dual_port_mixed_width[17:0].portbdatain[17:0] ">
                <delay_constant in_port="ram_block_M9K.data_b_in" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].portbdatain[17:0] "/>
              </complete>
              <complete input="ram_block_M9K.data_a_in" name="interconnect_full_ram_block_M9K_data_a_in_0" output="prim_ram_bidir_dual_port_mixed_width[17:0].portadatain[17:0] ">
                <delay_constant in_port="ram_block_M9K.data_a_in" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17:0].portadatain[17:0] "/>
              </complete>
              <complete input="ram_block_M9K.clk_in[1:0]" name="interconnect_full_ram_block_M9K_clk_in_1" output="prim_ram_bidir_dual_port_mixed_width[17:0].clk_portbout[0] prim_ram_bidir_dual_port_mixed_width[17:0].clk_portbin[0] prim_ram_bidir_dual_port_mixed_width[17:0].clk_portain[0] prim_ram_bidir_dual_port_mixed_width[17:0].clk_portaout[0] "/>
              <complete input="prim_ram_bidir_dual_port_mixed_width[17:0].eccstatus[2:0] " name="interconnect_full_ram_block_M9K_control_out_0" output="ram_block_M9K.control_out"/>
              <complete input="prim_ram_bidir_dual_port_mixed_width[17:0].portadataout[17:0] prim_ram_bidir_dual_port_mixed_width[17:0].portbdataout[17:0] " name="interconnect_full_ram_block_M9K_data_out_0" output="ram_block_M9K.data_out"/>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_0" output="prim_ram_bidir_dual_port_mixed_width[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[0].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_1" output="prim_ram_bidir_dual_port_mixed_width[1].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[1].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_2" output="prim_ram_bidir_dual_port_mixed_width[2].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[2].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_3" output="prim_ram_bidir_dual_port_mixed_width[3].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[3].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_4" output="prim_ram_bidir_dual_port_mixed_width[4].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[4].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_5" output="prim_ram_bidir_dual_port_mixed_width[5].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[5].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_6" output="prim_ram_bidir_dual_port_mixed_width[6].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[6].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_7" output="prim_ram_bidir_dual_port_mixed_width[7].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[7].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_8" output="prim_ram_bidir_dual_port_mixed_width[8].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[8].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_9" output="prim_ram_bidir_dual_port_mixed_width[9].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[9].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_10" output="prim_ram_bidir_dual_port_mixed_width[10].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[10].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_11" output="prim_ram_bidir_dual_port_mixed_width[11].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[11].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_12" output="prim_ram_bidir_dual_port_mixed_width[12].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[12].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_13" output="prim_ram_bidir_dual_port_mixed_width[13].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[13].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_14" output="prim_ram_bidir_dual_port_mixed_width[14].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[14].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_15" output="prim_ram_bidir_dual_port_mixed_width[15].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[15].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_16" output="prim_ram_bidir_dual_port_mixed_width[16].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[16].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[12:5]" name="interconnect_common_ram_block_M9K_control_in_[12:5]_17" output="prim_ram_bidir_dual_port_mixed_width[17].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[12:5]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_0" output="prim_ram_bidir_dual_port_mixed_width[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[0].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_1" output="prim_ram_bidir_dual_port_mixed_width[1].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[1].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_2" output="prim_ram_bidir_dual_port_mixed_width[2].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[2].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_3" output="prim_ram_bidir_dual_port_mixed_width[3].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[3].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_4" output="prim_ram_bidir_dual_port_mixed_width[4].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[4].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_5" output="prim_ram_bidir_dual_port_mixed_width[5].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[5].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_6" output="prim_ram_bidir_dual_port_mixed_width[6].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[6].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_7" output="prim_ram_bidir_dual_port_mixed_width[7].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[7].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_8" output="prim_ram_bidir_dual_port_mixed_width[8].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[8].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_9" output="prim_ram_bidir_dual_port_mixed_width[9].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[9].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_10" output="prim_ram_bidir_dual_port_mixed_width[10].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[10].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_11" output="prim_ram_bidir_dual_port_mixed_width[11].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[11].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_12" output="prim_ram_bidir_dual_port_mixed_width[12].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[12].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_13" output="prim_ram_bidir_dual_port_mixed_width[13].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[13].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_14" output="prim_ram_bidir_dual_port_mixed_width[14].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[14].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_15" output="prim_ram_bidir_dual_port_mixed_width[15].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[15].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_16" output="prim_ram_bidir_dual_port_mixed_width[16].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[16].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.control_in[26:19]" name="interconnect_common_ram_block_M9K_control_in_[26:19]_17" output="prim_ram_bidir_dual_port_mixed_width[17].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M9K.control_in[26:19]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_0" output="prim_ram_bidir_dual_port_mixed_width[0].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[0].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_1" output="prim_ram_bidir_dual_port_mixed_width[1].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[1].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_2" output="prim_ram_bidir_dual_port_mixed_width[2].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[2].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_3" output="prim_ram_bidir_dual_port_mixed_width[3].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[3].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_4" output="prim_ram_bidir_dual_port_mixed_width[4].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[4].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_5" output="prim_ram_bidir_dual_port_mixed_width[5].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[5].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_6" output="prim_ram_bidir_dual_port_mixed_width[6].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[6].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_7" output="prim_ram_bidir_dual_port_mixed_width[7].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[7].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_8" output="prim_ram_bidir_dual_port_mixed_width[8].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[8].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_9" output="prim_ram_bidir_dual_port_mixed_width[9].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[9].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_10" output="prim_ram_bidir_dual_port_mixed_width[10].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[10].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_11" output="prim_ram_bidir_dual_port_mixed_width[11].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[11].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_12" output="prim_ram_bidir_dual_port_mixed_width[12].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[12].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_13" output="prim_ram_bidir_dual_port_mixed_width[13].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[13].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_14" output="prim_ram_bidir_dual_port_mixed_width[14].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[14].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_15" output="prim_ram_bidir_dual_port_mixed_width[15].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[15].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_16" output="prim_ram_bidir_dual_port_mixed_width[16].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[16].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_a_in[12:0]" name="interconnect_common_ram_block_M9K_addr_a_in_[12:0]_17" output="prim_ram_bidir_dual_port_mixed_width[17].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_a_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17].portaaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_0" output="prim_ram_bidir_dual_port_mixed_width[0].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[0].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_1" output="prim_ram_bidir_dual_port_mixed_width[1].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[1].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_2" output="prim_ram_bidir_dual_port_mixed_width[2].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[2].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_3" output="prim_ram_bidir_dual_port_mixed_width[3].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[3].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_4" output="prim_ram_bidir_dual_port_mixed_width[4].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[4].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_5" output="prim_ram_bidir_dual_port_mixed_width[5].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[5].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_6" output="prim_ram_bidir_dual_port_mixed_width[6].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[6].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_7" output="prim_ram_bidir_dual_port_mixed_width[7].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[7].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_8" output="prim_ram_bidir_dual_port_mixed_width[8].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[8].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_9" output="prim_ram_bidir_dual_port_mixed_width[9].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[9].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_10" output="prim_ram_bidir_dual_port_mixed_width[10].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[10].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_11" output="prim_ram_bidir_dual_port_mixed_width[11].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[11].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_12" output="prim_ram_bidir_dual_port_mixed_width[12].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[12].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_13" output="prim_ram_bidir_dual_port_mixed_width[13].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[13].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_14" output="prim_ram_bidir_dual_port_mixed_width[14].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[14].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_15" output="prim_ram_bidir_dual_port_mixed_width[15].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[15].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_16" output="prim_ram_bidir_dual_port_mixed_width[16].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[16].portbaddr[12:0]"/>
              </direct>
              <direct input="ram_block_M9K.addr_b_in[12:0]" name="interconnect_common_ram_block_M9K_addr_b_in_[12:0]_17" output="prim_ram_bidir_dual_port_mixed_width[17].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M9K.addr_b_in[12:0]" max="4.83e-10" min="1.43e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17].portbaddr[12:0]"/>
              </direct>
            </interconnect>
          </mode>
        </pb_type>
        <interconnect>
          <complete input="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit0" output="ram_block_M9K[0].control_in[0]">
            <delay_constant in_port="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[89:72]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[0]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit1" output="ram_block_M9K[0].control_in[1]">
            <delay_constant in_port="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[35:18]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[1]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[53:36]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit2" output="ram_block_M9K[0].control_in[2]">
            <delay_constant in_port="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[53:36]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[2]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit3" output="ram_block_M9K[0].control_in[3]">
            <delay_constant in_port="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[35:18]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[3]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit4" output="ram_block_M9K[0].control_in[4]">
            <delay_constant in_port="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[4]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit5" output="ram_block_M9K[0].control_in[5]">
            <delay_constant in_port="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[5]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit6" output="ram_block_M9K[0].control_in[6]">
            <delay_constant in_port="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[89:72]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[6]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit7" output="ram_block_M9K[0].control_in[7]">
            <delay_constant in_port="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[35:18]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[7]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit8" output="ram_block_M9K[0].control_in[8]">
            <delay_constant in_port="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[89:72]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[8]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit9" output="ram_block_M9K[0].control_in[9]">
            <delay_constant in_port="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[35:18]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[9]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[103:90]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit10" output="ram_block_M9K[0].control_in[10]">
            <delay_constant in_port="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[103:90]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[10]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[53:36]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit11" output="ram_block_M9K[0].control_in[11]">
            <delay_constant in_port="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[53:36]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[11]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[53:36]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit12" output="ram_block_M9K[0].control_in[12]">
            <delay_constant in_port="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[53:36]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[12]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[103:90]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit13" output="ram_block_M9K[0].control_in[13]">
            <delay_constant in_port="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[103:90]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[13]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[53:36]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit14" output="ram_block_M9K[0].control_in[14]">
            <delay_constant in_port="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[53:36]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[14]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit15" output="ram_block_M9K[0].control_in[15]">
            <delay_constant in_port="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[35:18]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[15]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit16" output="ram_block_M9K[0].control_in[16]">
            <delay_constant in_port="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[16]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit17" output="ram_block_M9K[0].control_in[17]">
            <delay_constant in_port="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[89:72]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[17]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit18" output="ram_block_M9K[0].control_in[18]">
            <delay_constant in_port="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[89:72]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[18]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[17:0]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit19" output="ram_block_M9K[0].control_in[19]">
            <delay_constant in_port="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[17:0]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[19]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[103:90]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit20" output="ram_block_M9K[0].control_in[20]">
            <delay_constant in_port="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[103:90]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[20]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[103:90]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit21" output="ram_block_M9K[0].control_in[21]">
            <delay_constant in_port="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[103:90]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[21]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit22" output="ram_block_M9K[0].control_in[22]">
            <delay_constant in_port="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[22]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[103:90]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit23" output="ram_block_M9K[0].control_in[23]">
            <delay_constant in_port="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[103:90]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[23]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[53:36]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit24" output="ram_block_M9K[0].control_in[24]">
            <delay_constant in_port="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[53:36]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[24]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit25" output="ram_block_M9K[0].control_in[25]">
            <delay_constant in_port="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[35:18]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[25]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[103:90]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit26" output="ram_block_M9K[0].control_in[26]">
            <delay_constant in_port="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[103:90]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[26]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_1_bit27" output="ram_block_M9K[0].control_in[27]">
            <delay_constant in_port="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].control_in[27]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_2_bit0" output="ram_block_M9K[0].data_b_in[0]">
            <delay_constant in_port="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_b_in[0]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_2_bit1" output="ram_block_M9K[0].data_b_in[1]">
            <delay_constant in_port="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_b_in[1]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_2_bit2" output="ram_block_M9K[0].data_b_in[2]">
            <delay_constant in_port="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_b_in[2]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[53:36]" name="interconnect_partial_xbar_M9K_data_addr_control_in_2_bit3" output="ram_block_M9K[0].data_b_in[3]">
            <delay_constant in_port="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[53:36]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_b_in[3]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[53:36]" name="interconnect_partial_xbar_M9K_data_addr_control_in_2_bit4" output="ram_block_M9K[0].data_b_in[4]">
            <delay_constant in_port="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[53:36]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_b_in[4]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M9K_data_addr_control_in_2_bit5" output="ram_block_M9K[0].data_b_in[5]">
            <delay_constant in_port="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[35:18]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_b_in[5]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_2_bit6" output="ram_block_M9K[0].data_b_in[6]">
            <delay_constant in_port="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_b_in[6]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[53:36]" name="interconnect_partial_xbar_M9K_data_addr_control_in_2_bit7" output="ram_block_M9K[0].data_b_in[7]">
            <delay_constant in_port="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[53:36]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_b_in[7]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M9K_data_addr_control_in_2_bit8" output="ram_block_M9K[0].data_b_in[8]">
            <delay_constant in_port="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[89:72]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_b_in[8]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_2_bit9" output="ram_block_M9K[0].data_b_in[9]">
            <delay_constant in_port="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_b_in[9]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M9K_data_addr_control_in_2_bit10" output="ram_block_M9K[0].data_b_in[10]">
            <delay_constant in_port="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[89:72]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_b_in[10]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M9K_data_addr_control_in_2_bit11" output="ram_block_M9K[0].data_b_in[11]">
            <delay_constant in_port="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[89:72]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_b_in[11]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_2_bit12" output="ram_block_M9K[0].data_b_in[12]">
            <delay_constant in_port="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_b_in[12]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_2_bit13" output="ram_block_M9K[0].data_b_in[13]">
            <delay_constant in_port="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_b_in[13]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_2_bit14" output="ram_block_M9K[0].data_b_in[14]">
            <delay_constant in_port="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_b_in[14]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M9K_data_addr_control_in_2_bit15" output="ram_block_M9K[0].data_b_in[15]">
            <delay_constant in_port="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[89:72]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_b_in[15]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_2_bit16" output="ram_block_M9K[0].data_b_in[16]">
            <delay_constant in_port="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_b_in[16]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_2_bit17" output="ram_block_M9K[0].data_b_in[17]">
            <delay_constant in_port="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_b_in[17]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit0" output="ram_block_M9K[0].data_a_in[0]">
            <delay_constant in_port="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[35:18]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[0]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[17:0]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit1" output="ram_block_M9K[0].data_a_in[1]">
            <delay_constant in_port="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[17:0]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[1]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit2" output="ram_block_M9K[0].data_a_in[2]">
            <delay_constant in_port="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[89:72]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[2]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit3" output="ram_block_M9K[0].data_a_in[3]">
            <delay_constant in_port="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[89:72]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[3]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit4" output="ram_block_M9K[0].data_a_in[4]">
            <delay_constant in_port="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[89:72]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[4]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit5" output="ram_block_M9K[0].data_a_in[5]">
            <delay_constant in_port="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[5]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit6" output="ram_block_M9K[0].data_a_in[6]">
            <delay_constant in_port="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[6]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[17:0]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit7" output="ram_block_M9K[0].data_a_in[7]">
            <delay_constant in_port="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[17:0]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[7]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[53:36]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit8" output="ram_block_M9K[0].data_a_in[8]">
            <delay_constant in_port="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[53:36]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[8]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[103:90]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit9" output="ram_block_M9K[0].data_a_in[9]">
            <delay_constant in_port="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[103:90]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[9]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[103:90]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit10" output="ram_block_M9K[0].data_a_in[10]">
            <delay_constant in_port="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[103:90]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[10]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[17:0]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit11" output="ram_block_M9K[0].data_a_in[11]">
            <delay_constant in_port="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[17:0]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[11]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit12" output="ram_block_M9K[0].data_a_in[12]">
            <delay_constant in_port="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[89:72]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[12]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[17:0]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit13" output="ram_block_M9K[0].data_a_in[13]">
            <delay_constant in_port="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[17:0]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[13]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[17:0]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit14" output="ram_block_M9K[0].data_a_in[14]">
            <delay_constant in_port="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[17:0]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[14]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit15" output="ram_block_M9K[0].data_a_in[15]">
            <delay_constant in_port="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[15]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit16" output="ram_block_M9K[0].data_a_in[16]">
            <delay_constant in_port="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[35:18]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[16]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[17:0]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit17" output="ram_block_M9K[0].data_a_in[17]">
            <delay_constant in_port="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[17:0]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[17]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[103:90]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit18" output="ram_block_M9K[0].data_a_in[18]">
            <delay_constant in_port="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[103:90]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[18]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[53:36]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit19" output="ram_block_M9K[0].data_a_in[19]">
            <delay_constant in_port="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[53:36]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[19]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[103:90]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit20" output="ram_block_M9K[0].data_a_in[20]">
            <delay_constant in_port="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[103:90]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[20]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit21" output="ram_block_M9K[0].data_a_in[21]">
            <delay_constant in_port="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[35:18]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[21]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[103:90]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit22" output="ram_block_M9K[0].data_a_in[22]">
            <delay_constant in_port="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[103:90]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[22]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit23" output="ram_block_M9K[0].data_a_in[23]">
            <delay_constant in_port="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[89:72]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[23]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[53:36]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit24" output="ram_block_M9K[0].data_a_in[24]">
            <delay_constant in_port="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[53:36]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[24]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit25" output="ram_block_M9K[0].data_a_in[25]">
            <delay_constant in_port="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[25]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit26" output="ram_block_M9K[0].data_a_in[26]">
            <delay_constant in_port="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[35:18]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[26]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit27" output="ram_block_M9K[0].data_a_in[27]">
            <delay_constant in_port="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[27]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit28" output="ram_block_M9K[0].data_a_in[28]">
            <delay_constant in_port="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[35:18]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[28]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[103:90]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit29" output="ram_block_M9K[0].data_a_in[29]">
            <delay_constant in_port="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[103:90]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[29]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit30" output="ram_block_M9K[0].data_a_in[30]">
            <delay_constant in_port="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[30]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit31" output="ram_block_M9K[0].data_a_in[31]">
            <delay_constant in_port="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[89:72]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[31]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[17:0]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit32" output="ram_block_M9K[0].data_a_in[32]">
            <delay_constant in_port="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[17:0]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[32]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[103:90]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit33" output="ram_block_M9K[0].data_a_in[33]">
            <delay_constant in_port="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[103:90]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[33]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit34" output="ram_block_M9K[0].data_a_in[34]">
            <delay_constant in_port="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[35:18]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[34]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[103:90]" name="interconnect_partial_xbar_M9K_data_addr_control_in_3_bit35" output="ram_block_M9K[0].data_a_in[35]">
            <delay_constant in_port="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[103:90]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].data_a_in[35]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M9K_data_addr_control_in_4_bit0" output="ram_block_M9K[0].addr_a_in[0]">
            <delay_constant in_port="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[89:72]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_a_in[0]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_4_bit1" output="ram_block_M9K[0].addr_a_in[1]">
            <delay_constant in_port="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_a_in[1]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M9K_data_addr_control_in_4_bit2" output="ram_block_M9K[0].addr_a_in[2]">
            <delay_constant in_port="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[35:18]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_a_in[2]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M9K_data_addr_control_in_4_bit3" output="ram_block_M9K[0].addr_a_in[3]">
            <delay_constant in_port="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[35:18]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_a_in[3]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[53:36]" name="interconnect_partial_xbar_M9K_data_addr_control_in_4_bit4" output="ram_block_M9K[0].addr_a_in[4]">
            <delay_constant in_port="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[53:36]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_a_in[4]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_4_bit5" output="ram_block_M9K[0].addr_a_in[5]">
            <delay_constant in_port="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_a_in[5]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M9K_data_addr_control_in_4_bit6" output="ram_block_M9K[0].addr_a_in[6]">
            <delay_constant in_port="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[89:72]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_a_in[6]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_4_bit7" output="ram_block_M9K[0].addr_a_in[7]">
            <delay_constant in_port="M9K.data_addr_control_in[53:36] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_a_in[7]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[53:36]" name="interconnect_partial_xbar_M9K_data_addr_control_in_4_bit8" output="ram_block_M9K[0].addr_a_in[8]">
            <delay_constant in_port="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[53:36]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_a_in[8]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[17:0]" name="interconnect_partial_xbar_M9K_data_addr_control_in_4_bit9" output="ram_block_M9K[0].addr_a_in[9]">
            <delay_constant in_port="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[17:0]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_a_in[9]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[53:36]" name="interconnect_partial_xbar_M9K_data_addr_control_in_4_bit10" output="ram_block_M9K[0].addr_a_in[10]">
            <delay_constant in_port="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[53:36]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_a_in[10]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M9K_data_addr_control_in_4_bit11" output="ram_block_M9K[0].addr_a_in[11]">
            <delay_constant in_port="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[89:72]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_a_in[11]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[53:36]" name="interconnect_partial_xbar_M9K_data_addr_control_in_4_bit12" output="ram_block_M9K[0].addr_a_in[12]">
            <delay_constant in_port="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[53:36]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_a_in[12]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[53:36]" name="interconnect_partial_xbar_M9K_data_addr_control_in_5_bit0" output="ram_block_M9K[0].addr_b_in[0]">
            <delay_constant in_port="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[53:36]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_b_in[0]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[103:90]" name="interconnect_partial_xbar_M9K_data_addr_control_in_5_bit1" output="ram_block_M9K[0].addr_b_in[1]">
            <delay_constant in_port="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[103:90]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_b_in[1]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M9K_data_addr_control_in_5_bit2" output="ram_block_M9K[0].addr_b_in[2]">
            <delay_constant in_port="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[35:18]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_b_in[2]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_5_bit3" output="ram_block_M9K[0].addr_b_in[3]">
            <delay_constant in_port="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_b_in[3]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M9K_data_addr_control_in_5_bit4" output="ram_block_M9K[0].addr_b_in[4]">
            <delay_constant in_port="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[89:72]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_b_in[4]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[53:36]" name="interconnect_partial_xbar_M9K_data_addr_control_in_5_bit5" output="ram_block_M9K[0].addr_b_in[5]">
            <delay_constant in_port="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[53:36]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_b_in[5]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M9K_data_addr_control_in_5_bit6" output="ram_block_M9K[0].addr_b_in[6]">
            <delay_constant in_port="M9K.data_addr_control_in[89:72] M9K.data_addr_control_in[35:18]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_b_in[6]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M9K_data_addr_control_in_5_bit7" output="ram_block_M9K[0].addr_b_in[7]">
            <delay_constant in_port="M9K.data_addr_control_in[35:18] M9K.data_addr_control_in[89:72]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_b_in[7]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M9K_data_addr_control_in_5_bit8" output="ram_block_M9K[0].addr_b_in[8]">
            <delay_constant in_port="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[89:72]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_b_in[8]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[17:0]" name="interconnect_partial_xbar_M9K_data_addr_control_in_5_bit9" output="ram_block_M9K[0].addr_b_in[9]">
            <delay_constant in_port="M9K.data_addr_control_in[71:54] M9K.data_addr_control_in[17:0]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_b_in[9]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M9K_data_addr_control_in_5_bit10" output="ram_block_M9K[0].addr_b_in[10]">
            <delay_constant in_port="M9K.data_addr_control_in[17:0] M9K.data_addr_control_in[71:54]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_b_in[10]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M9K_data_addr_control_in_5_bit11" output="ram_block_M9K[0].addr_b_in[11]">
            <delay_constant in_port="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[35:18]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_b_in[11]"/>
          </complete>
          <complete input="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[17:0]" name="interconnect_partial_xbar_M9K_data_addr_control_in_5_bit12" output="ram_block_M9K[0].addr_b_in[12]">
            <delay_constant in_port="M9K.data_addr_control_in[103:90] M9K.data_addr_control_in[17:0]" max="1.63e-10" min="1.6e-10" out_port="ram_block_M9K[0].addr_b_in[12]"/>
          </complete>
          <direct input="M9K.clk_in[1:0]" name="interconnect_full_M9K_clk_in_1" output="ram_block_M9K[0].clk_in[1:0] "/>
          <direct input="ram_block_M9K[0].data_out[35:0] " name="interconnect_full_M9K_data_out_1" output="M9K.data_out[35:0]">
            <delay_constant in_port="ram_block_M9K[0].data_out[35:0] " max="5.6e-11" min="5.2e-11" out_port="M9K.data_out[35:0]"/>
          </direct>
          <direct input="ram_block_M9K[0].control_out[2:0] " name="interconnect_full_M9K_control_out_1" output="M9K.control_out[2:0]">
            <delay_constant in_port="ram_block_M9K[0].control_out[2:0] " max="5.6e-11" min="5.2e-11" out_port="M9K.control_out[2:0]"/>
          </direct>
        </interconnect>
      </mode>
    </pb_type>
    <pb_type name="M144K">
      <input name="data_addr_control_in" num_pins="416"/>
      <output name="data_out" num_pins="120"/>
      <output name="control_out" num_pins="3"/>
      <clock name="clk_in" num_pins="2"/>
      <mode name="ram">
        <pb_type name="ram_block_M144K" num_pb="1">
          <input name="control_in" num_pins="28"/>
          <input name="data_b_in" num_pins="36"/>
          <input name="data_a_in" num_pins="72"/>
          <input name="addr_a_in" num_pins="14"/>
          <input name="addr_b_in" num_pins="14"/>
          <output name="control_out" num_pins="3"/>
          <output name="data_out" num_pins="72"/>
          <clock name="clk_in" num_pins="2"/>
          <mode name="dual_port_reg-out_class_size_144K_A16Kx9_B16Kx9_composite_prim_ram_1x(A16Kx9_B16Kx9)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{14}.port_b_address_width{14}" class="memory" name="prim_ram_A16Kx9_B16Kx9" num_pb="1">
              <input name="portadatain" num_pins="9" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="14" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="14" port_class="address2"/>
              <output name="portbdataout" num_pins="9" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A16Kx9_B16Kx9.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A16Kx9_B16Kx9.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portbaddr"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A16Kx9_B16Kx9.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A16Kx9_B16Kx9.eccstatus" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A16Kx9_B16Kx9[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A16Kx9_B16Kx9[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A16Kx9_B16Kx9[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A16Kx9_B16Kx9[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A16Kx9_B16Kx9[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A16Kx9_B16Kx9[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A16Kx9_B16Kx9[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A16Kx9_B16Kx9[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A16Kx9_B16Kx9[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A16Kx9_B16Kx9[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A16Kx9_B16Kx9[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A16Kx9_B16Kx9[0].clk_portbin[0] prim_ram_A16Kx9_B16Kx9[0].clk_portain[0] prim_ram_A16Kx9_B16Kx9[0].clk_portaout[0] prim_ram_A16Kx9_B16Kx9[0].clk_portbout[0] "/>
              <complete input="prim_ram_A16Kx9_B16Kx9[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]" output="prim_ram_A16Kx9_B16Kx9[0].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portaaddr[13:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]" output="prim_ram_A16Kx9_B16Kx9[0].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portbaddr[13:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[8:0]" name="interconnect_split_ram_block_M144K_data_a_in_[8:0]" output="prim_ram_A16Kx9_B16Kx9[0].portadatain[8:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[8:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portadatain[8:0]"/>
              </direct>
              <direct input="prim_ram_A16Kx9_B16Kx9[0].portbdataout[8:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[8:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_144K_A16Kx9_B16Kx9_composite_prim_ram_1x(A16Kx9_B16Kx9)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{14}.port_b_address_width{14}" class="memory" name="prim_ram_A16Kx9_B16Kx9" num_pb="1">
              <input name="portadatain" num_pins="9" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="14" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="14" port_class="address2"/>
              <output name="portbdataout" num_pins="9" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portbaddr"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A16Kx9_B16Kx9[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A16Kx9_B16Kx9[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A16Kx9_B16Kx9[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A16Kx9_B16Kx9[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A16Kx9_B16Kx9[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A16Kx9_B16Kx9[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A16Kx9_B16Kx9[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A16Kx9_B16Kx9[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A16Kx9_B16Kx9[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A16Kx9_B16Kx9[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A16Kx9_B16Kx9[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A16Kx9_B16Kx9[0].clk_portbin[0] prim_ram_A16Kx9_B16Kx9[0].clk_portain[0] prim_ram_A16Kx9_B16Kx9[0].clk_portaout[0] prim_ram_A16Kx9_B16Kx9[0].clk_portbout[0] "/>
              <complete input="prim_ram_A16Kx9_B16Kx9[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]" output="prim_ram_A16Kx9_B16Kx9[0].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portaaddr[13:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]" output="prim_ram_A16Kx9_B16Kx9[0].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portbaddr[13:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[8:0]" name="interconnect_split_ram_block_M144K_data_a_in_[8:0]" output="prim_ram_A16Kx9_B16Kx9[0].portadatain[8:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[8:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portadatain[8:0]"/>
              </direct>
              <direct input="prim_ram_A16Kx9_B16Kx9[0].portbdataout[8:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[8:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_144K_A8Kx18_B8Kx18_composite_prim_ram_1x(A8Kx18_B8Kx18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{13}.port_b_address_width{13}" class="memory" name="prim_ram_A8Kx18_B8Kx18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="13" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="13" port_class="address2"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A8Kx18_B8Kx18.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A8Kx18_B8Kx18.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portbaddr"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A8Kx18_B8Kx18.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A8Kx18_B8Kx18.eccstatus" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A8Kx18_B8Kx18[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A8Kx18_B8Kx18[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A8Kx18_B8Kx18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A8Kx18_B8Kx18[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A8Kx18_B8Kx18[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A8Kx18_B8Kx18[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A8Kx18_B8Kx18[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A8Kx18_B8Kx18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A8Kx18_B8Kx18[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A8Kx18_B8Kx18[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A8Kx18_B8Kx18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A8Kx18_B8Kx18[0].clk_portbin[0] prim_ram_A8Kx18_B8Kx18[0].clk_portain[0] prim_ram_A8Kx18_B8Kx18[0].clk_portaout[0] prim_ram_A8Kx18_B8Kx18[0].clk_portbout[0] "/>
              <complete input="prim_ram_A8Kx18_B8Kx18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[12:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[12:0]" output="prim_ram_A8Kx18_B8Kx18[0].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[12:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portaaddr[12:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[12:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[12:0]" output="prim_ram_A8Kx18_B8Kx18[0].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[12:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portbaddr[12:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[17:0]" name="interconnect_split_ram_block_M144K_data_a_in_[17:0]" output="prim_ram_A8Kx18_B8Kx18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[17:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A8Kx18_B8Kx18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[17:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_144K_A8Kx18_B8Kx18_composite_prim_ram_1x(A8Kx18_B8Kx18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{13}.port_b_address_width{13}" class="memory" name="prim_ram_A8Kx18_B8Kx18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="13" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="13" port_class="address2"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portbaddr"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A8Kx18_B8Kx18[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A8Kx18_B8Kx18[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A8Kx18_B8Kx18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A8Kx18_B8Kx18[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A8Kx18_B8Kx18[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A8Kx18_B8Kx18[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A8Kx18_B8Kx18[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A8Kx18_B8Kx18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A8Kx18_B8Kx18[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A8Kx18_B8Kx18[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A8Kx18_B8Kx18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A8Kx18_B8Kx18[0].clk_portbin[0] prim_ram_A8Kx18_B8Kx18[0].clk_portain[0] prim_ram_A8Kx18_B8Kx18[0].clk_portaout[0] prim_ram_A8Kx18_B8Kx18[0].clk_portbout[0] "/>
              <complete input="prim_ram_A8Kx18_B8Kx18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[12:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[12:0]" output="prim_ram_A8Kx18_B8Kx18[0].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[12:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portaaddr[12:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[12:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[12:0]" output="prim_ram_A8Kx18_B8Kx18[0].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[12:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portbaddr[12:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[17:0]" name="interconnect_split_ram_block_M144K_data_a_in_[17:0]" output="prim_ram_A8Kx18_B8Kx18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[17:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A8Kx18_B8Kx18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[17:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_144K_A4Kx36_B4Kx36_composite_prim_ram_1x(A4Kx36_B4Kx36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{12}.port_b_address_width{12}" class="memory" name="prim_ram_A4Kx36_B4Kx36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="12" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="12" port_class="address2"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A4Kx36_B4Kx36.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A4Kx36_B4Kx36.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portbaddr"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A4Kx36_B4Kx36.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A4Kx36_B4Kx36.eccstatus" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A4Kx36_B4Kx36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A4Kx36_B4Kx36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A4Kx36_B4Kx36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A4Kx36_B4Kx36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A4Kx36_B4Kx36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A4Kx36_B4Kx36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A4Kx36_B4Kx36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A4Kx36_B4Kx36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A4Kx36_B4Kx36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A4Kx36_B4Kx36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A4Kx36_B4Kx36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A4Kx36_B4Kx36[0].clk_portbin[0] prim_ram_A4Kx36_B4Kx36[0].clk_portain[0] prim_ram_A4Kx36_B4Kx36[0].clk_portaout[0] prim_ram_A4Kx36_B4Kx36[0].clk_portbout[0] "/>
              <complete input="prim_ram_A4Kx36_B4Kx36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[11:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[11:0]" output="prim_ram_A4Kx36_B4Kx36[0].portaaddr[11:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[11:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portaaddr[11:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[11:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[11:0]" output="prim_ram_A4Kx36_B4Kx36[0].portbaddr[11:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[11:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portbaddr[11:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A4Kx36_B4Kx36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A4Kx36_B4Kx36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_144K_A4Kx36_B4Kx36_composite_prim_ram_1x(A4Kx36_B4Kx36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{12}.port_b_address_width{12}" class="memory" name="prim_ram_A4Kx36_B4Kx36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="12" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="12" port_class="address2"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portbaddr"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A4Kx36_B4Kx36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A4Kx36_B4Kx36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A4Kx36_B4Kx36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A4Kx36_B4Kx36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A4Kx36_B4Kx36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A4Kx36_B4Kx36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A4Kx36_B4Kx36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A4Kx36_B4Kx36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A4Kx36_B4Kx36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A4Kx36_B4Kx36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A4Kx36_B4Kx36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A4Kx36_B4Kx36[0].clk_portbin[0] prim_ram_A4Kx36_B4Kx36[0].clk_portain[0] prim_ram_A4Kx36_B4Kx36[0].clk_portaout[0] prim_ram_A4Kx36_B4Kx36[0].clk_portbout[0] "/>
              <complete input="prim_ram_A4Kx36_B4Kx36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[11:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[11:0]" output="prim_ram_A4Kx36_B4Kx36[0].portaaddr[11:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[11:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portaaddr[11:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[11:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[11:0]" output="prim_ram_A4Kx36_B4Kx36[0].portbaddr[11:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[11:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portbaddr[11:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A4Kx36_B4Kx36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A4Kx36_B4Kx36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_144K_A2Kx72_B2Kx72_composite_prim_ram_1x(A2Kx72_B2Kx72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{11}.port_b_address_width{11}" class="memory" name="prim_ram_A2Kx72_B2Kx72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="11" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="11" port_class="address2"/>
              <output name="portbdataout" num_pins="72" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx72_B2Kx72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A2Kx72_B2Kx72.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A2Kx72_B2Kx72.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx72_B2Kx72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx72_B2Kx72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx72_B2Kx72.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx72_B2Kx72.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx72_B2Kx72.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.portbaddr"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx72_B2Kx72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A2Kx72_B2Kx72.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A2Kx72_B2Kx72.eccstatus" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx72_B2Kx72.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx72_B2Kx72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx72_B2Kx72.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx72_B2Kx72.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx72_B2Kx72.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A2Kx72_B2Kx72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A2Kx72_B2Kx72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A2Kx72_B2Kx72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A2Kx72_B2Kx72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A2Kx72_B2Kx72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A2Kx72_B2Kx72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A2Kx72_B2Kx72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A2Kx72_B2Kx72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A2Kx72_B2Kx72[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A2Kx72_B2Kx72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A2Kx72_B2Kx72[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A2Kx72_B2Kx72[0].clk_portbin[0] prim_ram_A2Kx72_B2Kx72[0].clk_portain[0] prim_ram_A2Kx72_B2Kx72[0].clk_portaout[0] prim_ram_A2Kx72_B2Kx72[0].clk_portbout[0] "/>
              <complete input="prim_ram_A2Kx72_B2Kx72[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[10:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[10:0]" output="prim_ram_A2Kx72_B2Kx72[0].portaaddr[10:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[10:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].portaaddr[10:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[10:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[10:0]" output="prim_ram_A2Kx72_B2Kx72[0].portbaddr[10:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[10:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].portbaddr[10:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_A2Kx72_B2Kx72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_A2Kx72_B2Kx72[0].portbdataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_144K_A2Kx72_B2Kx72_composite_prim_ram_1x(A2Kx72_B2Kx72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{11}.port_b_address_width{11}" class="memory" name="prim_ram_A2Kx72_B2Kx72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="11" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="11" port_class="address2"/>
              <output name="portbdataout" num_pins="72" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx72_B2Kx72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx72_B2Kx72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx72_B2Kx72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx72_B2Kx72.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx72_B2Kx72.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx72_B2Kx72.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx72_B2Kx72.portbaddr"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx72_B2Kx72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx72_B2Kx72.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx72_B2Kx72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx72_B2Kx72.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx72_B2Kx72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx72_B2Kx72.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx72_B2Kx72.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx72_B2Kx72.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx72_B2Kx72.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A2Kx72_B2Kx72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A2Kx72_B2Kx72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A2Kx72_B2Kx72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A2Kx72_B2Kx72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A2Kx72_B2Kx72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A2Kx72_B2Kx72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A2Kx72_B2Kx72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A2Kx72_B2Kx72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A2Kx72_B2Kx72[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A2Kx72_B2Kx72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A2Kx72_B2Kx72[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A2Kx72_B2Kx72[0].clk_portbin[0] prim_ram_A2Kx72_B2Kx72[0].clk_portain[0] prim_ram_A2Kx72_B2Kx72[0].clk_portaout[0] prim_ram_A2Kx72_B2Kx72[0].clk_portbout[0] "/>
              <complete input="prim_ram_A2Kx72_B2Kx72[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[10:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[10:0]" output="prim_ram_A2Kx72_B2Kx72[0].portaaddr[10:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[10:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].portaaddr[10:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[10:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[10:0]" output="prim_ram_A2Kx72_B2Kx72[0].portbaddr[10:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[10:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].portbaddr[10:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_A2Kx72_B2Kx72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx72_B2Kx72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_A2Kx72_B2Kx72[0].portbdataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_72K_A1Kx72_B1Kx72_composite_prim_ram_1x(A1Kx72_B1Kx72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{10}.port_b_address_width{10}" class="memory" name="prim_ram_A1Kx72_B1Kx72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="10" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="10" port_class="address2"/>
              <output name="portbdataout" num_pins="72" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx72_B1Kx72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A1Kx72_B1Kx72.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A1Kx72_B1Kx72.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx72_B1Kx72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx72_B1Kx72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx72_B1Kx72.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx72_B1Kx72.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx72_B1Kx72.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.portbaddr"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx72_B1Kx72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A1Kx72_B1Kx72.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A1Kx72_B1Kx72.eccstatus" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx72_B1Kx72.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx72_B1Kx72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx72_B1Kx72.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx72_B1Kx72.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx72_B1Kx72.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A1Kx72_B1Kx72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A1Kx72_B1Kx72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A1Kx72_B1Kx72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A1Kx72_B1Kx72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A1Kx72_B1Kx72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A1Kx72_B1Kx72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A1Kx72_B1Kx72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A1Kx72_B1Kx72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A1Kx72_B1Kx72[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A1Kx72_B1Kx72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A1Kx72_B1Kx72[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A1Kx72_B1Kx72[0].clk_portbin[0] prim_ram_A1Kx72_B1Kx72[0].clk_portain[0] prim_ram_A1Kx72_B1Kx72[0].clk_portaout[0] prim_ram_A1Kx72_B1Kx72[0].clk_portbout[0] "/>
              <complete input="prim_ram_A1Kx72_B1Kx72[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[9:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[9:0]" output="prim_ram_A1Kx72_B1Kx72[0].portaaddr[9:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[9:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].portaaddr[9:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[9:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[9:0]" output="prim_ram_A1Kx72_B1Kx72[0].portbaddr[9:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[9:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].portbaddr[9:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_A1Kx72_B1Kx72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_A1Kx72_B1Kx72[0].portbdataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_72K_A1Kx72_B1Kx72_composite_prim_ram_1x(A1Kx72_B1Kx72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{10}.port_b_address_width{10}" class="memory" name="prim_ram_A1Kx72_B1Kx72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="10" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="10" port_class="address2"/>
              <output name="portbdataout" num_pins="72" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx72_B1Kx72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx72_B1Kx72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx72_B1Kx72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx72_B1Kx72.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx72_B1Kx72.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx72_B1Kx72.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx72_B1Kx72.portbaddr"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx72_B1Kx72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx72_B1Kx72.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx72_B1Kx72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx72_B1Kx72.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx72_B1Kx72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx72_B1Kx72.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx72_B1Kx72.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx72_B1Kx72.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx72_B1Kx72.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A1Kx72_B1Kx72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A1Kx72_B1Kx72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A1Kx72_B1Kx72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A1Kx72_B1Kx72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A1Kx72_B1Kx72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A1Kx72_B1Kx72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A1Kx72_B1Kx72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A1Kx72_B1Kx72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A1Kx72_B1Kx72[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A1Kx72_B1Kx72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A1Kx72_B1Kx72[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A1Kx72_B1Kx72[0].clk_portbin[0] prim_ram_A1Kx72_B1Kx72[0].clk_portain[0] prim_ram_A1Kx72_B1Kx72[0].clk_portaout[0] prim_ram_A1Kx72_B1Kx72[0].clk_portbout[0] "/>
              <complete input="prim_ram_A1Kx72_B1Kx72[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[9:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[9:0]" output="prim_ram_A1Kx72_B1Kx72[0].portaaddr[9:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[9:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].portaaddr[9:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[9:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[9:0]" output="prim_ram_A1Kx72_B1Kx72[0].portbaddr[9:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[9:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].portbaddr[9:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_A1Kx72_B1Kx72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx72_B1Kx72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_A1Kx72_B1Kx72[0].portbdataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_36K_A512x72_B512x72_composite_prim_ram_1x(A512x72_B512x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{9}.port_b_address_width{9}" class="memory" name="prim_ram_A512x72_B512x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="9" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="9" port_class="address2"/>
              <output name="portbdataout" num_pins="72" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x72_B512x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x72_B512x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x72_B512x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x72_B512x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A512x72_B512x72.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A512x72_B512x72.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x72_B512x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x72_B512x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x72_B512x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x72_B512x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x72_B512x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x72_B512x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x72_B512x72.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x72_B512x72.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x72_B512x72.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x72_B512x72.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.portbaddr"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x72_B512x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x72_B512x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x72_B512x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x72_B512x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A512x72_B512x72.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A512x72_B512x72.eccstatus" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x72_B512x72.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x72_B512x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x72_B512x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x72_B512x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x72_B512x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x72_B512x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x72_B512x72.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x72_B512x72.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x72_B512x72.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x72_B512x72.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A512x72_B512x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A512x72_B512x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A512x72_B512x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A512x72_B512x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A512x72_B512x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A512x72_B512x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A512x72_B512x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A512x72_B512x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A512x72_B512x72[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A512x72_B512x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A512x72_B512x72[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A512x72_B512x72[0].clk_portbin[0] prim_ram_A512x72_B512x72[0].clk_portain[0] prim_ram_A512x72_B512x72[0].clk_portaout[0] prim_ram_A512x72_B512x72[0].clk_portbout[0] "/>
              <complete input="prim_ram_A512x72_B512x72[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[8:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[8:0]" output="prim_ram_A512x72_B512x72[0].portaaddr[8:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[8:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].portaaddr[8:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[8:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[8:0]" output="prim_ram_A512x72_B512x72[0].portbaddr[8:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[8:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].portbaddr[8:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_A512x72_B512x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_A512x72_B512x72[0].portbdataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_36K_A512x72_B512x72_composite_prim_ram_1x(A512x72_B512x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{9}.port_b_address_width{9}" class="memory" name="prim_ram_A512x72_B512x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="9" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="9" port_class="address2"/>
              <output name="portbdataout" num_pins="72" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x72_B512x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x72_B512x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x72_B512x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x72_B512x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x72_B512x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x72_B512x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x72_B512x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x72_B512x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x72_B512x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x72_B512x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x72_B512x72.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x72_B512x72.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x72_B512x72.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x72_B512x72.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x72_B512x72.portbaddr"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x72_B512x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x72_B512x72.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x72_B512x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x72_B512x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x72_B512x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x72_B512x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x72_B512x72.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x72_B512x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x72_B512x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x72_B512x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x72_B512x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x72_B512x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x72_B512x72.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x72_B512x72.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x72_B512x72.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x72_B512x72.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A512x72_B512x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A512x72_B512x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A512x72_B512x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A512x72_B512x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A512x72_B512x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A512x72_B512x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A512x72_B512x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A512x72_B512x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A512x72_B512x72[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A512x72_B512x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A512x72_B512x72[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A512x72_B512x72[0].clk_portbin[0] prim_ram_A512x72_B512x72[0].clk_portain[0] prim_ram_A512x72_B512x72[0].clk_portaout[0] prim_ram_A512x72_B512x72[0].clk_portbout[0] "/>
              <complete input="prim_ram_A512x72_B512x72[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[8:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[8:0]" output="prim_ram_A512x72_B512x72[0].portaaddr[8:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[8:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].portaaddr[8:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[8:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[8:0]" output="prim_ram_A512x72_B512x72[0].portbaddr[8:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[8:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].portbaddr[8:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_A512x72_B512x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x72_B512x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_A512x72_B512x72[0].portbdataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_18K_A256x72_B256x72_composite_prim_ram_1x(A256x72_B256x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{8}.port_b_address_width{8}" class="memory" name="prim_ram_A256x72_B256x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="8" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="8" port_class="address2"/>
              <output name="portbdataout" num_pins="72" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x72_B256x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x72_B256x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x72_B256x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x72_B256x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A256x72_B256x72.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A256x72_B256x72.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x72_B256x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x72_B256x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x72_B256x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x72_B256x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x72_B256x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x72_B256x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x72_B256x72.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x72_B256x72.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x72_B256x72.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x72_B256x72.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.portbaddr"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x72_B256x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x72_B256x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x72_B256x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x72_B256x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A256x72_B256x72.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A256x72_B256x72.eccstatus" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x72_B256x72.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x72_B256x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x72_B256x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x72_B256x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x72_B256x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x72_B256x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x72_B256x72.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x72_B256x72.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x72_B256x72.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x72_B256x72.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A256x72_B256x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A256x72_B256x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A256x72_B256x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A256x72_B256x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A256x72_B256x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A256x72_B256x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A256x72_B256x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A256x72_B256x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A256x72_B256x72[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A256x72_B256x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A256x72_B256x72[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A256x72_B256x72[0].clk_portbin[0] prim_ram_A256x72_B256x72[0].clk_portain[0] prim_ram_A256x72_B256x72[0].clk_portaout[0] prim_ram_A256x72_B256x72[0].clk_portbout[0] "/>
              <complete input="prim_ram_A256x72_B256x72[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[7:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[7:0]" output="prim_ram_A256x72_B256x72[0].portaaddr[7:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[7:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].portaaddr[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[7:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[7:0]" output="prim_ram_A256x72_B256x72[0].portbaddr[7:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[7:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].portbaddr[7:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_A256x72_B256x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_A256x72_B256x72[0].portbdataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_18K_A256x72_B256x72_composite_prim_ram_1x(A256x72_B256x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{8}.port_b_address_width{8}" class="memory" name="prim_ram_A256x72_B256x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="8" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="8" port_class="address2"/>
              <output name="portbdataout" num_pins="72" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x72_B256x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x72_B256x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x72_B256x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x72_B256x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x72_B256x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x72_B256x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x72_B256x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x72_B256x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x72_B256x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x72_B256x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x72_B256x72.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x72_B256x72.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x72_B256x72.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x72_B256x72.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x72_B256x72.portbaddr"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x72_B256x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x72_B256x72.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x72_B256x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x72_B256x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x72_B256x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x72_B256x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x72_B256x72.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x72_B256x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x72_B256x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x72_B256x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x72_B256x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x72_B256x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x72_B256x72.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x72_B256x72.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x72_B256x72.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x72_B256x72.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A256x72_B256x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A256x72_B256x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A256x72_B256x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A256x72_B256x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A256x72_B256x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A256x72_B256x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A256x72_B256x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A256x72_B256x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A256x72_B256x72[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A256x72_B256x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A256x72_B256x72[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A256x72_B256x72[0].clk_portbin[0] prim_ram_A256x72_B256x72[0].clk_portain[0] prim_ram_A256x72_B256x72[0].clk_portaout[0] prim_ram_A256x72_B256x72[0].clk_portbout[0] "/>
              <complete input="prim_ram_A256x72_B256x72[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[7:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[7:0]" output="prim_ram_A256x72_B256x72[0].portaaddr[7:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[7:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].portaaddr[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[7:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[7:0]" output="prim_ram_A256x72_B256x72[0].portbaddr[7:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[7:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].portbaddr[7:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_A256x72_B256x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x72_B256x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_A256x72_B256x72[0].portbdataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_9K_A128x72_B128x72_composite_prim_ram_1x(A128x72_B128x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{7}.port_b_address_width{7}" class="memory" name="prim_ram_A128x72_B128x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="7" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="7" port_class="address2"/>
              <output name="portbdataout" num_pins="72" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x72_B128x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x72_B128x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x72_B128x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x72_B128x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A128x72_B128x72.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A128x72_B128x72.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x72_B128x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x72_B128x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x72_B128x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x72_B128x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x72_B128x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x72_B128x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x72_B128x72.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x72_B128x72.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x72_B128x72.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x72_B128x72.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.portbaddr"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x72_B128x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x72_B128x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x72_B128x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x72_B128x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A128x72_B128x72.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A128x72_B128x72.eccstatus" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x72_B128x72.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x72_B128x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x72_B128x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x72_B128x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x72_B128x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x72_B128x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x72_B128x72.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x72_B128x72.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x72_B128x72.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x72_B128x72.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A128x72_B128x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A128x72_B128x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A128x72_B128x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A128x72_B128x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A128x72_B128x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A128x72_B128x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A128x72_B128x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A128x72_B128x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A128x72_B128x72[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A128x72_B128x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A128x72_B128x72[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A128x72_B128x72[0].clk_portbin[0] prim_ram_A128x72_B128x72[0].clk_portain[0] prim_ram_A128x72_B128x72[0].clk_portaout[0] prim_ram_A128x72_B128x72[0].clk_portbout[0] "/>
              <complete input="prim_ram_A128x72_B128x72[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[6:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[6:0]" output="prim_ram_A128x72_B128x72[0].portaaddr[6:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[6:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].portaaddr[6:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[6:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[6:0]" output="prim_ram_A128x72_B128x72[0].portbaddr[6:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[6:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].portbaddr[6:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_A128x72_B128x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_A128x72_B128x72[0].portbdataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_9K_A128x72_B128x72_composite_prim_ram_1x(A128x72_B128x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{7}.port_b_address_width{7}" class="memory" name="prim_ram_A128x72_B128x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="7" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="7" port_class="address2"/>
              <output name="portbdataout" num_pins="72" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x72_B128x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x72_B128x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x72_B128x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x72_B128x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x72_B128x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x72_B128x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x72_B128x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x72_B128x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x72_B128x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x72_B128x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x72_B128x72.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x72_B128x72.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x72_B128x72.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x72_B128x72.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x72_B128x72.portbaddr"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x72_B128x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x72_B128x72.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x72_B128x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x72_B128x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x72_B128x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x72_B128x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x72_B128x72.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x72_B128x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x72_B128x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x72_B128x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x72_B128x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x72_B128x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x72_B128x72.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x72_B128x72.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x72_B128x72.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x72_B128x72.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A128x72_B128x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A128x72_B128x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A128x72_B128x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A128x72_B128x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A128x72_B128x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A128x72_B128x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A128x72_B128x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A128x72_B128x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A128x72_B128x72[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A128x72_B128x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A128x72_B128x72[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A128x72_B128x72[0].clk_portbin[0] prim_ram_A128x72_B128x72[0].clk_portain[0] prim_ram_A128x72_B128x72[0].clk_portaout[0] prim_ram_A128x72_B128x72[0].clk_portbout[0] "/>
              <complete input="prim_ram_A128x72_B128x72[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[6:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[6:0]" output="prim_ram_A128x72_B128x72[0].portaaddr[6:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[6:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].portaaddr[6:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[6:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[6:0]" output="prim_ram_A128x72_B128x72[0].portbaddr[6:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[6:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].portbaddr[6:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_A128x72_B128x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x72_B128x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_A128x72_B128x72[0].portbdataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_4K_A64x72_B64x72_composite_prim_ram_1x(A64x72_B64x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{6}.port_b_address_width{6}" class="memory" name="prim_ram_A64x72_B64x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="6" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="6" port_class="address2"/>
              <output name="portbdataout" num_pins="72" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x72_B64x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x72_B64x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x72_B64x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x72_B64x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A64x72_B64x72.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A64x72_B64x72.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x72_B64x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x72_B64x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x72_B64x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x72_B64x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x72_B64x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x72_B64x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x72_B64x72.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x72_B64x72.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x72_B64x72.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x72_B64x72.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.portbaddr"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x72_B64x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x72_B64x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x72_B64x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x72_B64x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A64x72_B64x72.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A64x72_B64x72.eccstatus" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x72_B64x72.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x72_B64x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x72_B64x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x72_B64x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x72_B64x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x72_B64x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x72_B64x72.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x72_B64x72.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x72_B64x72.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x72_B64x72.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A64x72_B64x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A64x72_B64x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A64x72_B64x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A64x72_B64x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A64x72_B64x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A64x72_B64x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A64x72_B64x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A64x72_B64x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A64x72_B64x72[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A64x72_B64x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A64x72_B64x72[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A64x72_B64x72[0].clk_portbin[0] prim_ram_A64x72_B64x72[0].clk_portain[0] prim_ram_A64x72_B64x72[0].clk_portaout[0] prim_ram_A64x72_B64x72[0].clk_portbout[0] "/>
              <complete input="prim_ram_A64x72_B64x72[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[5:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[5:0]" output="prim_ram_A64x72_B64x72[0].portaaddr[5:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[5:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].portaaddr[5:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[5:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[5:0]" output="prim_ram_A64x72_B64x72[0].portbaddr[5:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[5:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].portbaddr[5:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_A64x72_B64x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_A64x72_B64x72[0].portbdataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_4K_A64x72_B64x72_composite_prim_ram_1x(A64x72_B64x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{6}.port_b_address_width{6}" class="memory" name="prim_ram_A64x72_B64x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="6" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="6" port_class="address2"/>
              <output name="portbdataout" num_pins="72" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x72_B64x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x72_B64x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x72_B64x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x72_B64x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x72_B64x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x72_B64x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x72_B64x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x72_B64x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x72_B64x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x72_B64x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x72_B64x72.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x72_B64x72.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x72_B64x72.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x72_B64x72.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x72_B64x72.portbaddr"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x72_B64x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x72_B64x72.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x72_B64x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x72_B64x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x72_B64x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x72_B64x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x72_B64x72.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x72_B64x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x72_B64x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x72_B64x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x72_B64x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x72_B64x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x72_B64x72.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x72_B64x72.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x72_B64x72.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x72_B64x72.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A64x72_B64x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A64x72_B64x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A64x72_B64x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A64x72_B64x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A64x72_B64x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A64x72_B64x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A64x72_B64x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A64x72_B64x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A64x72_B64x72[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A64x72_B64x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A64x72_B64x72[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A64x72_B64x72[0].clk_portbin[0] prim_ram_A64x72_B64x72[0].clk_portain[0] prim_ram_A64x72_B64x72[0].clk_portaout[0] prim_ram_A64x72_B64x72[0].clk_portbout[0] "/>
              <complete input="prim_ram_A64x72_B64x72[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[5:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[5:0]" output="prim_ram_A64x72_B64x72[0].portaaddr[5:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[5:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].portaaddr[5:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[5:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[5:0]" output="prim_ram_A64x72_B64x72[0].portbaddr[5:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[5:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].portbaddr[5:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_A64x72_B64x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x72_B64x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_A64x72_B64x72[0].portbdataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_2K_A32x72_B32x72_composite_prim_ram_1x(A32x72_B32x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{5}.port_b_address_width{5}" class="memory" name="prim_ram_A32x72_B32x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="5" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="5" port_class="address2"/>
              <output name="portbdataout" num_pins="72" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x72_B32x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x72_B32x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x72_B32x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x72_B32x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A32x72_B32x72.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A32x72_B32x72.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x72_B32x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x72_B32x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x72_B32x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x72_B32x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x72_B32x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x72_B32x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x72_B32x72.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x72_B32x72.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x72_B32x72.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x72_B32x72.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.portbaddr"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x72_B32x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x72_B32x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x72_B32x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x72_B32x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A32x72_B32x72.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A32x72_B32x72.eccstatus" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x72_B32x72.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x72_B32x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x72_B32x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x72_B32x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x72_B32x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x72_B32x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x72_B32x72.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x72_B32x72.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x72_B32x72.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x72_B32x72.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A32x72_B32x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A32x72_B32x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A32x72_B32x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A32x72_B32x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A32x72_B32x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A32x72_B32x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A32x72_B32x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A32x72_B32x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A32x72_B32x72[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A32x72_B32x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A32x72_B32x72[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A32x72_B32x72[0].clk_portbin[0] prim_ram_A32x72_B32x72[0].clk_portain[0] prim_ram_A32x72_B32x72[0].clk_portaout[0] prim_ram_A32x72_B32x72[0].clk_portbout[0] "/>
              <complete input="prim_ram_A32x72_B32x72[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[4:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[4:0]" output="prim_ram_A32x72_B32x72[0].portaaddr[4:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[4:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].portaaddr[4:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[4:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[4:0]" output="prim_ram_A32x72_B32x72[0].portbaddr[4:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[4:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].portbaddr[4:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_A32x72_B32x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_A32x72_B32x72[0].portbdataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_2K_A32x72_B32x72_composite_prim_ram_1x(A32x72_B32x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{5}.port_b_address_width{5}" class="memory" name="prim_ram_A32x72_B32x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="5" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="5" port_class="address2"/>
              <output name="portbdataout" num_pins="72" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x72_B32x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x72_B32x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x72_B32x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x72_B32x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x72_B32x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x72_B32x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x72_B32x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x72_B32x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x72_B32x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x72_B32x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x72_B32x72.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x72_B32x72.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x72_B32x72.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x72_B32x72.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x72_B32x72.portbaddr"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x72_B32x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x72_B32x72.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x72_B32x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x72_B32x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x72_B32x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x72_B32x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x72_B32x72.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x72_B32x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x72_B32x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x72_B32x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x72_B32x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x72_B32x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x72_B32x72.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x72_B32x72.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x72_B32x72.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x72_B32x72.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A32x72_B32x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A32x72_B32x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A32x72_B32x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A32x72_B32x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A32x72_B32x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A32x72_B32x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A32x72_B32x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A32x72_B32x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A32x72_B32x72[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A32x72_B32x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A32x72_B32x72[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A32x72_B32x72[0].clk_portbin[0] prim_ram_A32x72_B32x72[0].clk_portain[0] prim_ram_A32x72_B32x72[0].clk_portaout[0] prim_ram_A32x72_B32x72[0].clk_portbout[0] "/>
              <complete input="prim_ram_A32x72_B32x72[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[4:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[4:0]" output="prim_ram_A32x72_B32x72[0].portaaddr[4:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[4:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].portaaddr[4:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[4:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[4:0]" output="prim_ram_A32x72_B32x72[0].portbaddr[4:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[4:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].portbaddr[4:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_A32x72_B32x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x72_B32x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_A32x72_B32x72[0].portbdataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_1K_A16x72_B16x72_composite_prim_ram_1x(A16x72_B16x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{4}.port_b_address_width{4}" class="memory" name="prim_ram_A16x72_B16x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="4" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="4" port_class="address2"/>
              <output name="portbdataout" num_pins="72" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x72_B16x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x72_B16x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x72_B16x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x72_B16x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A16x72_B16x72.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A16x72_B16x72.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x72_B16x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x72_B16x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x72_B16x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x72_B16x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x72_B16x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x72_B16x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x72_B16x72.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x72_B16x72.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x72_B16x72.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x72_B16x72.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.portbaddr"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x72_B16x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x72_B16x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x72_B16x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x72_B16x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A16x72_B16x72.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A16x72_B16x72.eccstatus" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x72_B16x72.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x72_B16x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x72_B16x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x72_B16x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x72_B16x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x72_B16x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x72_B16x72.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x72_B16x72.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x72_B16x72.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x72_B16x72.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A16x72_B16x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A16x72_B16x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A16x72_B16x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A16x72_B16x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A16x72_B16x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A16x72_B16x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A16x72_B16x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A16x72_B16x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A16x72_B16x72[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A16x72_B16x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A16x72_B16x72[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A16x72_B16x72[0].clk_portbin[0] prim_ram_A16x72_B16x72[0].clk_portain[0] prim_ram_A16x72_B16x72[0].clk_portaout[0] prim_ram_A16x72_B16x72[0].clk_portbout[0] "/>
              <complete input="prim_ram_A16x72_B16x72[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[3:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[3:0]" output="prim_ram_A16x72_B16x72[0].portaaddr[3:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[3:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].portaaddr[3:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[3:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[3:0]" output="prim_ram_A16x72_B16x72[0].portbaddr[3:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[3:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].portbaddr[3:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_A16x72_B16x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_A16x72_B16x72[0].portbdataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_1K_A16x72_B16x72_composite_prim_ram_1x(A16x72_B16x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{4}.port_b_address_width{4}" class="memory" name="prim_ram_A16x72_B16x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="4" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="4" port_class="address2"/>
              <output name="portbdataout" num_pins="72" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x72_B16x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x72_B16x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x72_B16x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x72_B16x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x72_B16x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x72_B16x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x72_B16x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x72_B16x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x72_B16x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x72_B16x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x72_B16x72.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x72_B16x72.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x72_B16x72.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x72_B16x72.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x72_B16x72.portbaddr"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x72_B16x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x72_B16x72.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x72_B16x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x72_B16x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x72_B16x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x72_B16x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x72_B16x72.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x72_B16x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x72_B16x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x72_B16x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x72_B16x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x72_B16x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x72_B16x72.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x72_B16x72.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x72_B16x72.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x72_B16x72.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A16x72_B16x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A16x72_B16x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A16x72_B16x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A16x72_B16x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A16x72_B16x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A16x72_B16x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A16x72_B16x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A16x72_B16x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A16x72_B16x72[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A16x72_B16x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A16x72_B16x72[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A16x72_B16x72[0].clk_portbin[0] prim_ram_A16x72_B16x72[0].clk_portain[0] prim_ram_A16x72_B16x72[0].clk_portaout[0] prim_ram_A16x72_B16x72[0].clk_portbout[0] "/>
              <complete input="prim_ram_A16x72_B16x72[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[3:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[3:0]" output="prim_ram_A16x72_B16x72[0].portaaddr[3:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[3:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].portaaddr[3:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[3:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[3:0]" output="prim_ram_A16x72_B16x72[0].portbaddr[3:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[3:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].portbaddr[3:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_A16x72_B16x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x72_B16x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_A16x72_B16x72[0].portbdataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_576_A8x72_B8x72_composite_prim_ram_1x(A8x72_B8x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{3}.port_b_address_width{3}" class="memory" name="prim_ram_A8x72_B8x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="3" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="3" port_class="address2"/>
              <output name="portbdataout" num_pins="72" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x72_B8x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x72_B8x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x72_B8x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x72_B8x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A8x72_B8x72.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A8x72_B8x72.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x72_B8x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x72_B8x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x72_B8x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x72_B8x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x72_B8x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x72_B8x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x72_B8x72.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x72_B8x72.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x72_B8x72.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x72_B8x72.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.portbaddr"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x72_B8x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x72_B8x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x72_B8x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x72_B8x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A8x72_B8x72.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A8x72_B8x72.eccstatus" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x72_B8x72.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x72_B8x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x72_B8x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x72_B8x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x72_B8x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x72_B8x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x72_B8x72.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x72_B8x72.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x72_B8x72.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x72_B8x72.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A8x72_B8x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A8x72_B8x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A8x72_B8x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A8x72_B8x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A8x72_B8x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A8x72_B8x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A8x72_B8x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A8x72_B8x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A8x72_B8x72[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A8x72_B8x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A8x72_B8x72[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A8x72_B8x72[0].clk_portbin[0] prim_ram_A8x72_B8x72[0].clk_portain[0] prim_ram_A8x72_B8x72[0].clk_portaout[0] prim_ram_A8x72_B8x72[0].clk_portbout[0] "/>
              <complete input="prim_ram_A8x72_B8x72[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[2:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[2:0]" output="prim_ram_A8x72_B8x72[0].portaaddr[2:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[2:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].portaaddr[2:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[2:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[2:0]" output="prim_ram_A8x72_B8x72[0].portbaddr[2:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[2:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].portbaddr[2:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_A8x72_B8x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_A8x72_B8x72[0].portbdataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_576_A8x72_B8x72_composite_prim_ram_1x(A8x72_B8x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{3}.port_b_address_width{3}" class="memory" name="prim_ram_A8x72_B8x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="3" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="3" port_class="address2"/>
              <output name="portbdataout" num_pins="72" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x72_B8x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x72_B8x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x72_B8x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x72_B8x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x72_B8x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x72_B8x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x72_B8x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x72_B8x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x72_B8x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x72_B8x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x72_B8x72.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x72_B8x72.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x72_B8x72.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x72_B8x72.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x72_B8x72.portbaddr"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x72_B8x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x72_B8x72.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x72_B8x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x72_B8x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x72_B8x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x72_B8x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x72_B8x72.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x72_B8x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x72_B8x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x72_B8x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x72_B8x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x72_B8x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x72_B8x72.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x72_B8x72.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x72_B8x72.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x72_B8x72.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A8x72_B8x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A8x72_B8x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A8x72_B8x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A8x72_B8x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A8x72_B8x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A8x72_B8x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A8x72_B8x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A8x72_B8x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A8x72_B8x72[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A8x72_B8x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A8x72_B8x72[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A8x72_B8x72[0].clk_portbin[0] prim_ram_A8x72_B8x72[0].clk_portain[0] prim_ram_A8x72_B8x72[0].clk_portaout[0] prim_ram_A8x72_B8x72[0].clk_portbout[0] "/>
              <complete input="prim_ram_A8x72_B8x72[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[2:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[2:0]" output="prim_ram_A8x72_B8x72[0].portaaddr[2:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[2:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].portaaddr[2:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[2:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[2:0]" output="prim_ram_A8x72_B8x72[0].portbaddr[2:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[2:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].portbaddr[2:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_A8x72_B8x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x72_B8x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_A8x72_B8x72[0].portbdataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_288_A4x72_B4x72_composite_prim_ram_1x(A4x72_B4x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{2}.port_b_address_width{2}" class="memory" name="prim_ram_A4x72_B4x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="2" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="2" port_class="address2"/>
              <output name="portbdataout" num_pins="72" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x72_B4x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x72_B4x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x72_B4x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x72_B4x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A4x72_B4x72.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A4x72_B4x72.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x72_B4x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x72_B4x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x72_B4x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x72_B4x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x72_B4x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x72_B4x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x72_B4x72.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x72_B4x72.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x72_B4x72.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x72_B4x72.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.portbaddr"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x72_B4x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x72_B4x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x72_B4x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x72_B4x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A4x72_B4x72.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A4x72_B4x72.eccstatus" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x72_B4x72.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x72_B4x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x72_B4x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x72_B4x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x72_B4x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x72_B4x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x72_B4x72.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x72_B4x72.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x72_B4x72.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x72_B4x72.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A4x72_B4x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A4x72_B4x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A4x72_B4x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A4x72_B4x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A4x72_B4x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A4x72_B4x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A4x72_B4x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A4x72_B4x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A4x72_B4x72[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A4x72_B4x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A4x72_B4x72[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A4x72_B4x72[0].clk_portbin[0] prim_ram_A4x72_B4x72[0].clk_portain[0] prim_ram_A4x72_B4x72[0].clk_portaout[0] prim_ram_A4x72_B4x72[0].clk_portbout[0] "/>
              <complete input="prim_ram_A4x72_B4x72[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[1:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[1:0]" output="prim_ram_A4x72_B4x72[0].portaaddr[1:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[1:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].portaaddr[1:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[1:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[1:0]" output="prim_ram_A4x72_B4x72[0].portbaddr[1:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[1:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].portbaddr[1:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_A4x72_B4x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_A4x72_B4x72[0].portbdataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_288_A4x72_B4x72_composite_prim_ram_1x(A4x72_B4x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{2}.port_b_address_width{2}" class="memory" name="prim_ram_A4x72_B4x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="2" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="2" port_class="address2"/>
              <output name="portbdataout" num_pins="72" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x72_B4x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x72_B4x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x72_B4x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x72_B4x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x72_B4x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x72_B4x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x72_B4x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x72_B4x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x72_B4x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x72_B4x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x72_B4x72.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x72_B4x72.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x72_B4x72.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x72_B4x72.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x72_B4x72.portbaddr"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x72_B4x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x72_B4x72.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x72_B4x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x72_B4x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x72_B4x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x72_B4x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x72_B4x72.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x72_B4x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x72_B4x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x72_B4x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x72_B4x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x72_B4x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x72_B4x72.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x72_B4x72.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x72_B4x72.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x72_B4x72.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A4x72_B4x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A4x72_B4x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A4x72_B4x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A4x72_B4x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A4x72_B4x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A4x72_B4x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A4x72_B4x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A4x72_B4x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A4x72_B4x72[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A4x72_B4x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A4x72_B4x72[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A4x72_B4x72[0].clk_portbin[0] prim_ram_A4x72_B4x72[0].clk_portain[0] prim_ram_A4x72_B4x72[0].clk_portaout[0] prim_ram_A4x72_B4x72[0].clk_portbout[0] "/>
              <complete input="prim_ram_A4x72_B4x72[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[1:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[1:0]" output="prim_ram_A4x72_B4x72[0].portaaddr[1:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[1:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].portaaddr[1:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[1:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[1:0]" output="prim_ram_A4x72_B4x72[0].portbaddr[1:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[1:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].portbaddr[1:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_A4x72_B4x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x72_B4x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_A4x72_B4x72[0].portbdataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_144_A2x72_B2x72_composite_prim_ram_1x(A2x72_B2x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{1}.port_b_address_width{1}" class="memory" name="prim_ram_A2x72_B2x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="1" port_class="address2"/>
              <output name="portbdataout" num_pins="72" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x72_B2x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x72_B2x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x72_B2x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x72_B2x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A2x72_B2x72.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A2x72_B2x72.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x72_B2x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x72_B2x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x72_B2x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x72_B2x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x72_B2x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x72_B2x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x72_B2x72.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x72_B2x72.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x72_B2x72.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x72_B2x72.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.portbaddr"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x72_B2x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x72_B2x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x72_B2x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x72_B2x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A2x72_B2x72.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A2x72_B2x72.eccstatus" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x72_B2x72.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x72_B2x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x72_B2x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x72_B2x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x72_B2x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x72_B2x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x72_B2x72.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x72_B2x72.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x72_B2x72.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x72_B2x72.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A2x72_B2x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A2x72_B2x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A2x72_B2x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A2x72_B2x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A2x72_B2x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A2x72_B2x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A2x72_B2x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A2x72_B2x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A2x72_B2x72[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A2x72_B2x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A2x72_B2x72[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A2x72_B2x72[0].clk_portbin[0] prim_ram_A2x72_B2x72[0].clk_portain[0] prim_ram_A2x72_B2x72[0].clk_portaout[0] prim_ram_A2x72_B2x72[0].clk_portbout[0] "/>
              <complete input="prim_ram_A2x72_B2x72[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[0]" name="interconnect_common_ram_block_M144K_addr_a_in_[0]" output="prim_ram_A2x72_B2x72[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].portaaddr[0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[0]" name="interconnect_common_ram_block_M144K_addr_b_in_[0]" output="prim_ram_A2x72_B2x72[0].portbaddr[0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].portbaddr[0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_A2x72_B2x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_A2x72_B2x72[0].portbdataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_144_A2x72_B2x72_composite_prim_ram_1x(A2x72_B2x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{1}.port_b_address_width{1}" class="memory" name="prim_ram_A2x72_B2x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="1" port_class="address2"/>
              <output name="portbdataout" num_pins="72" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x72_B2x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x72_B2x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x72_B2x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x72_B2x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x72_B2x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x72_B2x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x72_B2x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x72_B2x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x72_B2x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x72_B2x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x72_B2x72.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x72_B2x72.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x72_B2x72.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x72_B2x72.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x72_B2x72.portbaddr"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x72_B2x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x72_B2x72.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x72_B2x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x72_B2x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x72_B2x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x72_B2x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x72_B2x72.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x72_B2x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x72_B2x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x72_B2x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x72_B2x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x72_B2x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x72_B2x72.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x72_B2x72.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x72_B2x72.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x72_B2x72.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A2x72_B2x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A2x72_B2x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A2x72_B2x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A2x72_B2x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A2x72_B2x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A2x72_B2x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A2x72_B2x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A2x72_B2x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A2x72_B2x72[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A2x72_B2x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A2x72_B2x72[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A2x72_B2x72[0].clk_portbin[0] prim_ram_A2x72_B2x72[0].clk_portain[0] prim_ram_A2x72_B2x72[0].clk_portaout[0] prim_ram_A2x72_B2x72[0].clk_portbout[0] "/>
              <complete input="prim_ram_A2x72_B2x72[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[0]" name="interconnect_common_ram_block_M144K_addr_a_in_[0]" output="prim_ram_A2x72_B2x72[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].portaaddr[0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[0]" name="interconnect_common_ram_block_M144K_addr_b_in_[0]" output="prim_ram_A2x72_B2x72[0].portbaddr[0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].portbaddr[0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_A2x72_B2x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x72_B2x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_A2x72_B2x72[0].portbdataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_class_size_72_A1x72_B1x72_composite_prim_ram_1x(A1x72_B1x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{0}.port_b_address_width{0}" class="memory" name="prim_ram_A1x72_B1x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="1" port_class="address2"/>
              <output name="portbdataout" num_pins="72" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x72_B1x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x72_B1x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x72_B1x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x72_B1x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A1x72_B1x72.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A1x72_B1x72.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x72_B1x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x72_B1x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x72_B1x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x72_B1x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x72_B1x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x72_B1x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x72_B1x72.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x72_B1x72.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x72_B1x72.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x72_B1x72.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.portbaddr"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x72_B1x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x72_B1x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x72_B1x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x72_B1x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A1x72_B1x72.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A1x72_B1x72.eccstatus" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x72_B1x72.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x72_B1x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x72_B1x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x72_B1x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x72_B1x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x72_B1x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x72_B1x72.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x72_B1x72.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x72_B1x72.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x72_B1x72.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A1x72_B1x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A1x72_B1x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A1x72_B1x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A1x72_B1x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A1x72_B1x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A1x72_B1x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A1x72_B1x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A1x72_B1x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A1x72_B1x72[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A1x72_B1x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A1x72_B1x72[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A1x72_B1x72[0].clk_portbin[0] prim_ram_A1x72_B1x72[0].clk_portain[0] prim_ram_A1x72_B1x72[0].clk_portaout[0] prim_ram_A1x72_B1x72[0].clk_portbout[0] "/>
              <complete input="prim_ram_A1x72_B1x72[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[0]" name="interconnect_common_ram_block_M144K_addr_a_in_[0]" output="prim_ram_A1x72_B1x72[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].portaaddr[0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[0]" name="interconnect_common_ram_block_M144K_addr_b_in_[0]" output="prim_ram_A1x72_B1x72[0].portbaddr[0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].portbaddr[0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_A1x72_B1x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_A1x72_B1x72[0].portbdataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_class_size_72_A1x72_B1x72_composite_prim_ram_1x(A1x72_B1x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{0}.port_b_address_width{0}" class="memory" name="prim_ram_A1x72_B1x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="1" port_class="address2"/>
              <output name="portbdataout" num_pins="72" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x72_B1x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x72_B1x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x72_B1x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x72_B1x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x72_B1x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x72_B1x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x72_B1x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x72_B1x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x72_B1x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x72_B1x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x72_B1x72.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x72_B1x72.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x72_B1x72.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x72_B1x72.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x72_B1x72.portbaddr"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x72_B1x72.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x72_B1x72.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x72_B1x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x72_B1x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x72_B1x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x72_B1x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x72_B1x72.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x72_B1x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x72_B1x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x72_B1x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x72_B1x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x72_B1x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x72_B1x72.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x72_B1x72.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x72_B1x72.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x72_B1x72.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A1x72_B1x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A1x72_B1x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]" output="prim_ram_A1x72_B1x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_A1x72_B1x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_A1x72_B1x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_A1x72_B1x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A1x72_B1x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A1x72_B1x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A1x72_B1x72[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A1x72_B1x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A1x72_B1x72[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A1x72_B1x72[0].clk_portbin[0] prim_ram_A1x72_B1x72[0].clk_portain[0] prim_ram_A1x72_B1x72[0].clk_portaout[0] prim_ram_A1x72_B1x72[0].clk_portbout[0] "/>
              <complete input="prim_ram_A1x72_B1x72[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[0]" name="interconnect_common_ram_block_M144K_addr_a_in_[0]" output="prim_ram_A1x72_B1x72[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].portaaddr[0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[0]" name="interconnect_common_ram_block_M144K_addr_b_in_[0]" output="prim_ram_A1x72_B1x72[0].portbaddr[0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].portbaddr[0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_A1x72_B1x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x72_B1x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_A1x72_B1x72[0].portbdataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_144K_A16Kx9_B16Kx9_composite_prim_ram_1x(A16Kx9_B16Kx9)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{14}.port_b_address_width{14}" class="memory" name="prim_ram_A16Kx9_B16Kx9" num_pb="1">
              <input name="portadatain" num_pins="9" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="14" port_class="address1"/>
              <input name="portbaddr" num_pins="14" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="9" port_class="data_in2"/>
              <output name="portadataout" num_pins="9" port_class="data_out1"/>
              <output name="portbdataout" num_pins="9" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A16Kx9_B16Kx9.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A16Kx9_B16Kx9.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A16Kx9_B16Kx9.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portbdatain"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_A16Kx9_B16Kx9.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbwe" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A16Kx9_B16Kx9.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A16Kx9_B16Kx9.eccstatus" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A16Kx9_B16Kx9[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A16Kx9_B16Kx9[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A16Kx9_B16Kx9[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A16Kx9_B16Kx9[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A16Kx9_B16Kx9[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A16Kx9_B16Kx9[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A16Kx9_B16Kx9[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A16Kx9_B16Kx9[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A16Kx9_B16Kx9[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A16Kx9_B16Kx9[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A16Kx9_B16Kx9[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A16Kx9_B16Kx9[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A16Kx9_B16Kx9[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A16Kx9_B16Kx9[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A16Kx9_B16Kx9[0].clk_portbout[0] prim_ram_A16Kx9_B16Kx9[0].clk_portbin[0] prim_ram_A16Kx9_B16Kx9[0].clk_portain[0] prim_ram_A16Kx9_B16Kx9[0].clk_portaout[0] "/>
              <complete input="prim_ram_A16Kx9_B16Kx9[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]" output="prim_ram_A16Kx9_B16Kx9[0].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portaaddr[13:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]" output="prim_ram_A16Kx9_B16Kx9[0].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portbaddr[13:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[8:0]" name="interconnect_split_ram_block_M144K_data_b_in_[8:0]" output="prim_ram_A16Kx9_B16Kx9[0].portbdatain[8:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[8:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portbdatain[8:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[8:0]" name="interconnect_split_ram_block_M144K_data_a_in_[8:0]" output="prim_ram_A16Kx9_B16Kx9[0].portadatain[8:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[8:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portadatain[8:0]"/>
              </direct>
              <direct input="prim_ram_A16Kx9_B16Kx9[0].portadataout[8:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[8:0]"/>
              <direct input="prim_ram_A16Kx9_B16Kx9[0].portbdataout[8:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[17:9]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_144K_A16Kx9_B16Kx9_composite_prim_ram_1x(A16Kx9_B16Kx9)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{14}.port_b_address_width{14}" class="memory" name="prim_ram_A16Kx9_B16Kx9" num_pb="1">
              <input name="portadatain" num_pins="9" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="14" port_class="address1"/>
              <input name="portbaddr" num_pins="14" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="9" port_class="data_in2"/>
              <output name="portadataout" num_pins="9" port_class="data_out1"/>
              <output name="portbdataout" num_pins="9" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16Kx9_B16Kx9.portbdatain"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.eccstatus"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_A16Kx9_B16Kx9.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16Kx9_B16Kx9.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbwe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16Kx9_B16Kx9.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16Kx9_B16Kx9.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A16Kx9_B16Kx9[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A16Kx9_B16Kx9[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A16Kx9_B16Kx9[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A16Kx9_B16Kx9[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A16Kx9_B16Kx9[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A16Kx9_B16Kx9[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A16Kx9_B16Kx9[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A16Kx9_B16Kx9[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A16Kx9_B16Kx9[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A16Kx9_B16Kx9[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A16Kx9_B16Kx9[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A16Kx9_B16Kx9[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A16Kx9_B16Kx9[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A16Kx9_B16Kx9[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A16Kx9_B16Kx9[0].clk_portbout[0] prim_ram_A16Kx9_B16Kx9[0].clk_portbin[0] prim_ram_A16Kx9_B16Kx9[0].clk_portain[0] prim_ram_A16Kx9_B16Kx9[0].clk_portaout[0] "/>
              <complete input="prim_ram_A16Kx9_B16Kx9[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]" output="prim_ram_A16Kx9_B16Kx9[0].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portaaddr[13:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]" output="prim_ram_A16Kx9_B16Kx9[0].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portbaddr[13:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[8:0]" name="interconnect_split_ram_block_M144K_data_b_in_[8:0]" output="prim_ram_A16Kx9_B16Kx9[0].portbdatain[8:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[8:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portbdatain[8:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[8:0]" name="interconnect_split_ram_block_M144K_data_a_in_[8:0]" output="prim_ram_A16Kx9_B16Kx9[0].portadatain[8:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[8:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16Kx9_B16Kx9[0].portadatain[8:0]"/>
              </direct>
              <direct input="prim_ram_A16Kx9_B16Kx9[0].portadataout[8:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[8:0]"/>
              <direct input="prim_ram_A16Kx9_B16Kx9[0].portbdataout[8:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[17:9]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_144K_A8Kx18_B8Kx18_composite_prim_ram_1x(A8Kx18_B8Kx18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{13}.port_b_address_width{13}" class="memory" name="prim_ram_A8Kx18_B8Kx18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="13" port_class="address1"/>
              <input name="portbaddr" num_pins="13" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="18" port_class="data_in2"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A8Kx18_B8Kx18.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A8Kx18_B8Kx18.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A8Kx18_B8Kx18.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portbdatain"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_A8Kx18_B8Kx18.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbwe" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A8Kx18_B8Kx18.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A8Kx18_B8Kx18.eccstatus" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A8Kx18_B8Kx18[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A8Kx18_B8Kx18[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A8Kx18_B8Kx18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A8Kx18_B8Kx18[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A8Kx18_B8Kx18[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A8Kx18_B8Kx18[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A8Kx18_B8Kx18[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A8Kx18_B8Kx18[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A8Kx18_B8Kx18[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A8Kx18_B8Kx18[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A8Kx18_B8Kx18[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A8Kx18_B8Kx18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A8Kx18_B8Kx18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A8Kx18_B8Kx18[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A8Kx18_B8Kx18[0].clk_portbout[0] prim_ram_A8Kx18_B8Kx18[0].clk_portbin[0] prim_ram_A8Kx18_B8Kx18[0].clk_portain[0] prim_ram_A8Kx18_B8Kx18[0].clk_portaout[0] "/>
              <complete input="prim_ram_A8Kx18_B8Kx18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[12:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[12:0]" output="prim_ram_A8Kx18_B8Kx18[0].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[12:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portaaddr[12:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[12:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[12:0]" output="prim_ram_A8Kx18_B8Kx18[0].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[12:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portbaddr[12:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[17:0]" name="interconnect_split_ram_block_M144K_data_b_in_[17:0]" output="prim_ram_A8Kx18_B8Kx18[0].portbdatain[17:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[17:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portbdatain[17:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[17:0]" name="interconnect_split_ram_block_M144K_data_a_in_[17:0]" output="prim_ram_A8Kx18_B8Kx18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[17:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A8Kx18_B8Kx18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[17:0]"/>
              <direct input="prim_ram_A8Kx18_B8Kx18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[35:18]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_144K_A8Kx18_B8Kx18_composite_prim_ram_1x(A8Kx18_B8Kx18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{13}.port_b_address_width{13}" class="memory" name="prim_ram_A8Kx18_B8Kx18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="13" port_class="address1"/>
              <input name="portbaddr" num_pins="13" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="18" port_class="data_in2"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <output name="portbdataout" num_pins="18" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8Kx18_B8Kx18.portbdatain"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.eccstatus"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_A8Kx18_B8Kx18.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8Kx18_B8Kx18.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbwe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8Kx18_B8Kx18.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8Kx18_B8Kx18.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A8Kx18_B8Kx18[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A8Kx18_B8Kx18[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A8Kx18_B8Kx18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A8Kx18_B8Kx18[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A8Kx18_B8Kx18[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A8Kx18_B8Kx18[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A8Kx18_B8Kx18[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A8Kx18_B8Kx18[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A8Kx18_B8Kx18[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A8Kx18_B8Kx18[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A8Kx18_B8Kx18[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A8Kx18_B8Kx18[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A8Kx18_B8Kx18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A8Kx18_B8Kx18[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A8Kx18_B8Kx18[0].clk_portbout[0] prim_ram_A8Kx18_B8Kx18[0].clk_portbin[0] prim_ram_A8Kx18_B8Kx18[0].clk_portain[0] prim_ram_A8Kx18_B8Kx18[0].clk_portaout[0] "/>
              <complete input="prim_ram_A8Kx18_B8Kx18[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[12:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[12:0]" output="prim_ram_A8Kx18_B8Kx18[0].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[12:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portaaddr[12:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[12:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[12:0]" output="prim_ram_A8Kx18_B8Kx18[0].portbaddr[12:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[12:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portbaddr[12:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[17:0]" name="interconnect_split_ram_block_M144K_data_b_in_[17:0]" output="prim_ram_A8Kx18_B8Kx18[0].portbdatain[17:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[17:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portbdatain[17:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[17:0]" name="interconnect_split_ram_block_M144K_data_a_in_[17:0]" output="prim_ram_A8Kx18_B8Kx18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[17:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8Kx18_B8Kx18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_A8Kx18_B8Kx18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[17:0]"/>
              <direct input="prim_ram_A8Kx18_B8Kx18[0].portbdataout[17:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[35:18]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_144K_A4Kx36_B4Kx36_composite_prim_ram_1x(A4Kx36_B4Kx36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{12}.port_b_address_width{12}" class="memory" name="prim_ram_A4Kx36_B4Kx36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="12" port_class="address1"/>
              <input name="portbaddr" num_pins="12" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A4Kx36_B4Kx36.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A4Kx36_B4Kx36.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A4Kx36_B4Kx36.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portbdatain"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_A4Kx36_B4Kx36.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A4Kx36_B4Kx36.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A4Kx36_B4Kx36.eccstatus" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A4Kx36_B4Kx36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A4Kx36_B4Kx36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A4Kx36_B4Kx36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A4Kx36_B4Kx36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A4Kx36_B4Kx36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A4Kx36_B4Kx36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A4Kx36_B4Kx36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A4Kx36_B4Kx36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A4Kx36_B4Kx36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A4Kx36_B4Kx36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A4Kx36_B4Kx36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A4Kx36_B4Kx36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A4Kx36_B4Kx36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A4Kx36_B4Kx36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A4Kx36_B4Kx36[0].clk_portbout[0] prim_ram_A4Kx36_B4Kx36[0].clk_portbin[0] prim_ram_A4Kx36_B4Kx36[0].clk_portain[0] prim_ram_A4Kx36_B4Kx36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A4Kx36_B4Kx36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[11:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[11:0]" output="prim_ram_A4Kx36_B4Kx36[0].portaaddr[11:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[11:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portaaddr[11:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[11:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[11:0]" output="prim_ram_A4Kx36_B4Kx36[0].portbaddr[11:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[11:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portbaddr[11:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A4Kx36_B4Kx36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A4Kx36_B4Kx36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A4Kx36_B4Kx36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A4Kx36_B4Kx36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_144K_A4Kx36_B4Kx36_composite_prim_ram_1x(A4Kx36_B4Kx36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{12}.port_b_address_width{12}" class="memory" name="prim_ram_A4Kx36_B4Kx36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="12" port_class="address1"/>
              <input name="portbaddr" num_pins="12" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4Kx36_B4Kx36.portbdatain"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A4Kx36_B4Kx36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4Kx36_B4Kx36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4Kx36_B4Kx36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4Kx36_B4Kx36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A4Kx36_B4Kx36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A4Kx36_B4Kx36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A4Kx36_B4Kx36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A4Kx36_B4Kx36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A4Kx36_B4Kx36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A4Kx36_B4Kx36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A4Kx36_B4Kx36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A4Kx36_B4Kx36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A4Kx36_B4Kx36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A4Kx36_B4Kx36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A4Kx36_B4Kx36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A4Kx36_B4Kx36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A4Kx36_B4Kx36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A4Kx36_B4Kx36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A4Kx36_B4Kx36[0].clk_portbout[0] prim_ram_A4Kx36_B4Kx36[0].clk_portbin[0] prim_ram_A4Kx36_B4Kx36[0].clk_portain[0] prim_ram_A4Kx36_B4Kx36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A4Kx36_B4Kx36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[11:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[11:0]" output="prim_ram_A4Kx36_B4Kx36[0].portaaddr[11:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[11:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portaaddr[11:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[11:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[11:0]" output="prim_ram_A4Kx36_B4Kx36[0].portbaddr[11:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[11:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portbaddr[11:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A4Kx36_B4Kx36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A4Kx36_B4Kx36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4Kx36_B4Kx36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A4Kx36_B4Kx36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A4Kx36_B4Kx36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_72K_A2Kx36_B2Kx36_composite_prim_ram_1x(A2Kx36_B2Kx36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{11}.port_b_address_width{11}" class="memory" name="prim_ram_A2Kx36_B2Kx36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="11" port_class="address1"/>
              <input name="portbaddr" num_pins="11" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A2Kx36_B2Kx36.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A2Kx36_B2Kx36.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A2Kx36_B2Kx36.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portbdatain"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_A2Kx36_B2Kx36.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A2Kx36_B2Kx36.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A2Kx36_B2Kx36.eccstatus" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A2Kx36_B2Kx36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A2Kx36_B2Kx36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A2Kx36_B2Kx36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A2Kx36_B2Kx36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A2Kx36_B2Kx36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A2Kx36_B2Kx36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A2Kx36_B2Kx36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A2Kx36_B2Kx36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A2Kx36_B2Kx36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A2Kx36_B2Kx36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A2Kx36_B2Kx36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A2Kx36_B2Kx36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A2Kx36_B2Kx36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A2Kx36_B2Kx36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A2Kx36_B2Kx36[0].clk_portbout[0] prim_ram_A2Kx36_B2Kx36[0].clk_portbin[0] prim_ram_A2Kx36_B2Kx36[0].clk_portain[0] prim_ram_A2Kx36_B2Kx36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A2Kx36_B2Kx36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[10:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[10:0]" output="prim_ram_A2Kx36_B2Kx36[0].portaaddr[10:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[10:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].portaaddr[10:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[10:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[10:0]" output="prim_ram_A2Kx36_B2Kx36[0].portbaddr[10:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[10:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].portbaddr[10:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A2Kx36_B2Kx36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A2Kx36_B2Kx36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A2Kx36_B2Kx36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A2Kx36_B2Kx36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_72K_A2Kx36_B2Kx36_composite_prim_ram_1x(A2Kx36_B2Kx36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{11}.port_b_address_width{11}" class="memory" name="prim_ram_A2Kx36_B2Kx36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="11" port_class="address1"/>
              <input name="portbaddr" num_pins="11" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2Kx36_B2Kx36.portbdatain"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A2Kx36_B2Kx36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2Kx36_B2Kx36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2Kx36_B2Kx36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2Kx36_B2Kx36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A2Kx36_B2Kx36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A2Kx36_B2Kx36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A2Kx36_B2Kx36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A2Kx36_B2Kx36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A2Kx36_B2Kx36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A2Kx36_B2Kx36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A2Kx36_B2Kx36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A2Kx36_B2Kx36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A2Kx36_B2Kx36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A2Kx36_B2Kx36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A2Kx36_B2Kx36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A2Kx36_B2Kx36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A2Kx36_B2Kx36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A2Kx36_B2Kx36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A2Kx36_B2Kx36[0].clk_portbout[0] prim_ram_A2Kx36_B2Kx36[0].clk_portbin[0] prim_ram_A2Kx36_B2Kx36[0].clk_portain[0] prim_ram_A2Kx36_B2Kx36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A2Kx36_B2Kx36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[10:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[10:0]" output="prim_ram_A2Kx36_B2Kx36[0].portaaddr[10:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[10:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].portaaddr[10:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[10:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[10:0]" output="prim_ram_A2Kx36_B2Kx36[0].portbaddr[10:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[10:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].portbaddr[10:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A2Kx36_B2Kx36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A2Kx36_B2Kx36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2Kx36_B2Kx36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A2Kx36_B2Kx36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A2Kx36_B2Kx36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_36K_A1Kx36_B1Kx36_composite_prim_ram_1x(A1Kx36_B1Kx36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{10}.port_b_address_width{10}" class="memory" name="prim_ram_A1Kx36_B1Kx36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="10" port_class="address1"/>
              <input name="portbaddr" num_pins="10" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A1Kx36_B1Kx36.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A1Kx36_B1Kx36.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A1Kx36_B1Kx36.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portbdatain"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_A1Kx36_B1Kx36.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A1Kx36_B1Kx36.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A1Kx36_B1Kx36.eccstatus" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A1Kx36_B1Kx36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A1Kx36_B1Kx36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A1Kx36_B1Kx36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A1Kx36_B1Kx36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A1Kx36_B1Kx36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A1Kx36_B1Kx36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A1Kx36_B1Kx36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A1Kx36_B1Kx36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A1Kx36_B1Kx36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A1Kx36_B1Kx36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A1Kx36_B1Kx36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A1Kx36_B1Kx36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A1Kx36_B1Kx36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A1Kx36_B1Kx36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A1Kx36_B1Kx36[0].clk_portbout[0] prim_ram_A1Kx36_B1Kx36[0].clk_portbin[0] prim_ram_A1Kx36_B1Kx36[0].clk_portain[0] prim_ram_A1Kx36_B1Kx36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A1Kx36_B1Kx36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[9:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[9:0]" output="prim_ram_A1Kx36_B1Kx36[0].portaaddr[9:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[9:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].portaaddr[9:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[9:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[9:0]" output="prim_ram_A1Kx36_B1Kx36[0].portbaddr[9:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[9:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].portbaddr[9:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A1Kx36_B1Kx36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A1Kx36_B1Kx36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A1Kx36_B1Kx36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A1Kx36_B1Kx36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_36K_A1Kx36_B1Kx36_composite_prim_ram_1x(A1Kx36_B1Kx36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{10}.port_b_address_width{10}" class="memory" name="prim_ram_A1Kx36_B1Kx36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="10" port_class="address1"/>
              <input name="portbaddr" num_pins="10" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1Kx36_B1Kx36.portbdatain"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_A1Kx36_B1Kx36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1Kx36_B1Kx36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1Kx36_B1Kx36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1Kx36_B1Kx36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A1Kx36_B1Kx36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A1Kx36_B1Kx36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A1Kx36_B1Kx36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A1Kx36_B1Kx36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A1Kx36_B1Kx36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A1Kx36_B1Kx36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A1Kx36_B1Kx36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A1Kx36_B1Kx36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A1Kx36_B1Kx36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A1Kx36_B1Kx36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A1Kx36_B1Kx36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A1Kx36_B1Kx36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A1Kx36_B1Kx36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A1Kx36_B1Kx36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A1Kx36_B1Kx36[0].clk_portbout[0] prim_ram_A1Kx36_B1Kx36[0].clk_portbin[0] prim_ram_A1Kx36_B1Kx36[0].clk_portain[0] prim_ram_A1Kx36_B1Kx36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A1Kx36_B1Kx36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[9:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[9:0]" output="prim_ram_A1Kx36_B1Kx36[0].portaaddr[9:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[9:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].portaaddr[9:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[9:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[9:0]" output="prim_ram_A1Kx36_B1Kx36[0].portbaddr[9:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[9:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].portbaddr[9:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A1Kx36_B1Kx36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A1Kx36_B1Kx36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1Kx36_B1Kx36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A1Kx36_B1Kx36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A1Kx36_B1Kx36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_18K_A512x36_B512x36_composite_prim_ram_1x(A512x36_B512x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{9}.port_b_address_width{9}" class="memory" name="prim_ram_A512x36_B512x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="9" port_class="address1"/>
              <input name="portbaddr" num_pins="9" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x36_B512x36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x36_B512x36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A512x36_B512x36.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x36_B512x36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x36_B512x36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x36_B512x36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x36_B512x36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x36_B512x36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x36_B512x36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x36_B512x36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x36_B512x36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A512x36_B512x36.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x36_B512x36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x36_B512x36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x36_B512x36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x36_B512x36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x36_B512x36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x36_B512x36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A512x36_B512x36.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x36_B512x36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x36_B512x36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portbdatain"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x36_B512x36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x36_B512x36.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_A512x36_B512x36.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x36_B512x36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x36_B512x36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x36_B512x36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x36_B512x36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x36_B512x36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x36_B512x36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x36_B512x36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x36_B512x36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A512x36_B512x36.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x36_B512x36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x36_B512x36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x36_B512x36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x36_B512x36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x36_B512x36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x36_B512x36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A512x36_B512x36.eccstatus" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x36_B512x36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x36_B512x36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A512x36_B512x36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A512x36_B512x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A512x36_B512x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A512x36_B512x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A512x36_B512x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A512x36_B512x36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A512x36_B512x36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A512x36_B512x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A512x36_B512x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A512x36_B512x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A512x36_B512x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A512x36_B512x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A512x36_B512x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A512x36_B512x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A512x36_B512x36[0].clk_portbout[0] prim_ram_A512x36_B512x36[0].clk_portbin[0] prim_ram_A512x36_B512x36[0].clk_portain[0] prim_ram_A512x36_B512x36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A512x36_B512x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[8:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[8:0]" output="prim_ram_A512x36_B512x36[0].portaaddr[8:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[8:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].portaaddr[8:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[8:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[8:0]" output="prim_ram_A512x36_B512x36[0].portbaddr[8:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[8:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].portbaddr[8:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A512x36_B512x36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A512x36_B512x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A512x36_B512x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A512x36_B512x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_18K_A512x36_B512x36_composite_prim_ram_1x(A512x36_B512x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{9}.port_b_address_width{9}" class="memory" name="prim_ram_A512x36_B512x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="9" port_class="address1"/>
              <input name="portbaddr" num_pins="9" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x36_B512x36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x36_B512x36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x36_B512x36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x36_B512x36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x36_B512x36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x36_B512x36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x36_B512x36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x36_B512x36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x36_B512x36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x36_B512x36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x36_B512x36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x36_B512x36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x36_B512x36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x36_B512x36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x36_B512x36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x36_B512x36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A512x36_B512x36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A512x36_B512x36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A512x36_B512x36.portbdatain"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portadataout"/>
              <delay_constant in_port="prim_ram_A512x36_B512x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A512x36_B512x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x36_B512x36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x36_B512x36.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x36_B512x36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x36_B512x36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x36_B512x36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x36_B512x36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x36_B512x36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x36_B512x36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x36_B512x36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x36_B512x36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x36_B512x36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x36_B512x36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x36_B512x36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x36_B512x36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x36_B512x36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x36_B512x36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A512x36_B512x36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A512x36_B512x36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A512x36_B512x36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A512x36_B512x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A512x36_B512x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A512x36_B512x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A512x36_B512x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A512x36_B512x36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A512x36_B512x36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A512x36_B512x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A512x36_B512x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A512x36_B512x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A512x36_B512x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A512x36_B512x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A512x36_B512x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A512x36_B512x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A512x36_B512x36[0].clk_portbout[0] prim_ram_A512x36_B512x36[0].clk_portbin[0] prim_ram_A512x36_B512x36[0].clk_portain[0] prim_ram_A512x36_B512x36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A512x36_B512x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[8:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[8:0]" output="prim_ram_A512x36_B512x36[0].portaaddr[8:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[8:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].portaaddr[8:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[8:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[8:0]" output="prim_ram_A512x36_B512x36[0].portbaddr[8:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[8:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].portbaddr[8:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A512x36_B512x36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A512x36_B512x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A512x36_B512x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A512x36_B512x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A512x36_B512x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_9K_A256x36_B256x36_composite_prim_ram_1x(A256x36_B256x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{8}.port_b_address_width{8}" class="memory" name="prim_ram_A256x36_B256x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="8" port_class="address1"/>
              <input name="portbaddr" num_pins="8" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A256x36_B256x36.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A256x36_B256x36.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A256x36_B256x36.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portbdatain"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_A256x36_B256x36.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A256x36_B256x36.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A256x36_B256x36.eccstatus" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A256x36_B256x36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A256x36_B256x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A256x36_B256x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A256x36_B256x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A256x36_B256x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A256x36_B256x36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A256x36_B256x36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A256x36_B256x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A256x36_B256x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A256x36_B256x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A256x36_B256x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A256x36_B256x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A256x36_B256x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A256x36_B256x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A256x36_B256x36[0].clk_portbout[0] prim_ram_A256x36_B256x36[0].clk_portbin[0] prim_ram_A256x36_B256x36[0].clk_portain[0] prim_ram_A256x36_B256x36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A256x36_B256x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[7:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[7:0]" output="prim_ram_A256x36_B256x36[0].portaaddr[7:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[7:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].portaaddr[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[7:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[7:0]" output="prim_ram_A256x36_B256x36[0].portbaddr[7:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[7:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].portbaddr[7:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A256x36_B256x36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A256x36_B256x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A256x36_B256x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A256x36_B256x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_9K_A256x36_B256x36_composite_prim_ram_1x(A256x36_B256x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{8}.port_b_address_width{8}" class="memory" name="prim_ram_A256x36_B256x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="8" port_class="address1"/>
              <input name="portbaddr" num_pins="8" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A256x36_B256x36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A256x36_B256x36.portbdatain"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portadataout"/>
              <delay_constant in_port="prim_ram_A256x36_B256x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A256x36_B256x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A256x36_B256x36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A256x36_B256x36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A256x36_B256x36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A256x36_B256x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A256x36_B256x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A256x36_B256x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A256x36_B256x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A256x36_B256x36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A256x36_B256x36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A256x36_B256x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A256x36_B256x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A256x36_B256x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A256x36_B256x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A256x36_B256x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A256x36_B256x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A256x36_B256x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A256x36_B256x36[0].clk_portbout[0] prim_ram_A256x36_B256x36[0].clk_portbin[0] prim_ram_A256x36_B256x36[0].clk_portain[0] prim_ram_A256x36_B256x36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A256x36_B256x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[7:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[7:0]" output="prim_ram_A256x36_B256x36[0].portaaddr[7:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[7:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].portaaddr[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[7:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[7:0]" output="prim_ram_A256x36_B256x36[0].portbaddr[7:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[7:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].portbaddr[7:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A256x36_B256x36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A256x36_B256x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A256x36_B256x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A256x36_B256x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A256x36_B256x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_4K_A128x36_B128x36_composite_prim_ram_1x(A128x36_B128x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{7}.port_b_address_width{7}" class="memory" name="prim_ram_A128x36_B128x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="7" port_class="address1"/>
              <input name="portbaddr" num_pins="7" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A128x36_B128x36.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A128x36_B128x36.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A128x36_B128x36.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portbdatain"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_A128x36_B128x36.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A128x36_B128x36.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A128x36_B128x36.eccstatus" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A128x36_B128x36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A128x36_B128x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A128x36_B128x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A128x36_B128x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A128x36_B128x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A128x36_B128x36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A128x36_B128x36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A128x36_B128x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A128x36_B128x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A128x36_B128x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A128x36_B128x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A128x36_B128x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A128x36_B128x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A128x36_B128x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A128x36_B128x36[0].clk_portbout[0] prim_ram_A128x36_B128x36[0].clk_portbin[0] prim_ram_A128x36_B128x36[0].clk_portain[0] prim_ram_A128x36_B128x36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A128x36_B128x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[6:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[6:0]" output="prim_ram_A128x36_B128x36[0].portaaddr[6:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[6:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].portaaddr[6:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[6:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[6:0]" output="prim_ram_A128x36_B128x36[0].portbaddr[6:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[6:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].portbaddr[6:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A128x36_B128x36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A128x36_B128x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A128x36_B128x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A128x36_B128x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_4K_A128x36_B128x36_composite_prim_ram_1x(A128x36_B128x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{7}.port_b_address_width{7}" class="memory" name="prim_ram_A128x36_B128x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="7" port_class="address1"/>
              <input name="portbaddr" num_pins="7" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A128x36_B128x36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A128x36_B128x36.portbdatain"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portadataout"/>
              <delay_constant in_port="prim_ram_A128x36_B128x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A128x36_B128x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A128x36_B128x36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A128x36_B128x36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A128x36_B128x36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A128x36_B128x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A128x36_B128x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A128x36_B128x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A128x36_B128x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A128x36_B128x36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A128x36_B128x36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A128x36_B128x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A128x36_B128x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A128x36_B128x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A128x36_B128x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A128x36_B128x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A128x36_B128x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A128x36_B128x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A128x36_B128x36[0].clk_portbout[0] prim_ram_A128x36_B128x36[0].clk_portbin[0] prim_ram_A128x36_B128x36[0].clk_portain[0] prim_ram_A128x36_B128x36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A128x36_B128x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[6:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[6:0]" output="prim_ram_A128x36_B128x36[0].portaaddr[6:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[6:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].portaaddr[6:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[6:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[6:0]" output="prim_ram_A128x36_B128x36[0].portbaddr[6:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[6:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].portbaddr[6:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A128x36_B128x36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A128x36_B128x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A128x36_B128x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A128x36_B128x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A128x36_B128x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_2K_A64x36_B64x36_composite_prim_ram_1x(A64x36_B64x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{6}.port_b_address_width{6}" class="memory" name="prim_ram_A64x36_B64x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="6" port_class="address1"/>
              <input name="portbaddr" num_pins="6" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A64x36_B64x36.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A64x36_B64x36.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A64x36_B64x36.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portbdatain"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_A64x36_B64x36.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A64x36_B64x36.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A64x36_B64x36.eccstatus" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A64x36_B64x36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A64x36_B64x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A64x36_B64x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A64x36_B64x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A64x36_B64x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A64x36_B64x36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A64x36_B64x36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A64x36_B64x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A64x36_B64x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A64x36_B64x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A64x36_B64x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A64x36_B64x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A64x36_B64x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A64x36_B64x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A64x36_B64x36[0].clk_portbout[0] prim_ram_A64x36_B64x36[0].clk_portbin[0] prim_ram_A64x36_B64x36[0].clk_portain[0] prim_ram_A64x36_B64x36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A64x36_B64x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[5:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[5:0]" output="prim_ram_A64x36_B64x36[0].portaaddr[5:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[5:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].portaaddr[5:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[5:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[5:0]" output="prim_ram_A64x36_B64x36[0].portbaddr[5:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[5:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].portbaddr[5:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A64x36_B64x36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A64x36_B64x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A64x36_B64x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A64x36_B64x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_2K_A64x36_B64x36_composite_prim_ram_1x(A64x36_B64x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{6}.port_b_address_width{6}" class="memory" name="prim_ram_A64x36_B64x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="6" port_class="address1"/>
              <input name="portbaddr" num_pins="6" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A64x36_B64x36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A64x36_B64x36.portbdatain"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portadataout"/>
              <delay_constant in_port="prim_ram_A64x36_B64x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A64x36_B64x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A64x36_B64x36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A64x36_B64x36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A64x36_B64x36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A64x36_B64x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A64x36_B64x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A64x36_B64x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A64x36_B64x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A64x36_B64x36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A64x36_B64x36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A64x36_B64x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A64x36_B64x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A64x36_B64x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A64x36_B64x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A64x36_B64x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A64x36_B64x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A64x36_B64x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A64x36_B64x36[0].clk_portbout[0] prim_ram_A64x36_B64x36[0].clk_portbin[0] prim_ram_A64x36_B64x36[0].clk_portain[0] prim_ram_A64x36_B64x36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A64x36_B64x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[5:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[5:0]" output="prim_ram_A64x36_B64x36[0].portaaddr[5:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[5:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].portaaddr[5:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[5:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[5:0]" output="prim_ram_A64x36_B64x36[0].portbaddr[5:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[5:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].portbaddr[5:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A64x36_B64x36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A64x36_B64x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A64x36_B64x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A64x36_B64x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A64x36_B64x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_1K_A32x36_B32x36_composite_prim_ram_1x(A32x36_B32x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{5}.port_b_address_width{5}" class="memory" name="prim_ram_A32x36_B32x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="5" port_class="address1"/>
              <input name="portbaddr" num_pins="5" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A32x36_B32x36.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A32x36_B32x36.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A32x36_B32x36.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portbdatain"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_A32x36_B32x36.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A32x36_B32x36.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A32x36_B32x36.eccstatus" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A32x36_B32x36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A32x36_B32x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A32x36_B32x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A32x36_B32x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A32x36_B32x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A32x36_B32x36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A32x36_B32x36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A32x36_B32x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A32x36_B32x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A32x36_B32x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A32x36_B32x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A32x36_B32x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A32x36_B32x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A32x36_B32x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A32x36_B32x36[0].clk_portbout[0] prim_ram_A32x36_B32x36[0].clk_portbin[0] prim_ram_A32x36_B32x36[0].clk_portain[0] prim_ram_A32x36_B32x36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A32x36_B32x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[4:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[4:0]" output="prim_ram_A32x36_B32x36[0].portaaddr[4:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[4:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].portaaddr[4:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[4:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[4:0]" output="prim_ram_A32x36_B32x36[0].portbaddr[4:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[4:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].portbaddr[4:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A32x36_B32x36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A32x36_B32x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A32x36_B32x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A32x36_B32x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_1K_A32x36_B32x36_composite_prim_ram_1x(A32x36_B32x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{5}.port_b_address_width{5}" class="memory" name="prim_ram_A32x36_B32x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="5" port_class="address1"/>
              <input name="portbaddr" num_pins="5" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A32x36_B32x36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A32x36_B32x36.portbdatain"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portadataout"/>
              <delay_constant in_port="prim_ram_A32x36_B32x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A32x36_B32x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A32x36_B32x36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A32x36_B32x36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A32x36_B32x36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A32x36_B32x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A32x36_B32x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A32x36_B32x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A32x36_B32x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A32x36_B32x36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A32x36_B32x36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A32x36_B32x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A32x36_B32x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A32x36_B32x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A32x36_B32x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A32x36_B32x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A32x36_B32x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A32x36_B32x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A32x36_B32x36[0].clk_portbout[0] prim_ram_A32x36_B32x36[0].clk_portbin[0] prim_ram_A32x36_B32x36[0].clk_portain[0] prim_ram_A32x36_B32x36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A32x36_B32x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[4:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[4:0]" output="prim_ram_A32x36_B32x36[0].portaaddr[4:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[4:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].portaaddr[4:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[4:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[4:0]" output="prim_ram_A32x36_B32x36[0].portbaddr[4:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[4:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].portbaddr[4:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A32x36_B32x36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A32x36_B32x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A32x36_B32x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A32x36_B32x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A32x36_B32x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_576_A16x36_B16x36_composite_prim_ram_1x(A16x36_B16x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{4}.port_b_address_width{4}" class="memory" name="prim_ram_A16x36_B16x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="4" port_class="address1"/>
              <input name="portbaddr" num_pins="4" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A16x36_B16x36.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A16x36_B16x36.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A16x36_B16x36.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portbdatain"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_A16x36_B16x36.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A16x36_B16x36.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A16x36_B16x36.eccstatus" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A16x36_B16x36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A16x36_B16x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A16x36_B16x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A16x36_B16x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A16x36_B16x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A16x36_B16x36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A16x36_B16x36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A16x36_B16x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A16x36_B16x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A16x36_B16x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A16x36_B16x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A16x36_B16x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A16x36_B16x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A16x36_B16x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A16x36_B16x36[0].clk_portbout[0] prim_ram_A16x36_B16x36[0].clk_portbin[0] prim_ram_A16x36_B16x36[0].clk_portain[0] prim_ram_A16x36_B16x36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A16x36_B16x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[3:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[3:0]" output="prim_ram_A16x36_B16x36[0].portaaddr[3:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[3:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].portaaddr[3:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[3:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[3:0]" output="prim_ram_A16x36_B16x36[0].portbaddr[3:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[3:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].portbaddr[3:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A16x36_B16x36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A16x36_B16x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A16x36_B16x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A16x36_B16x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_576_A16x36_B16x36_composite_prim_ram_1x(A16x36_B16x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{4}.port_b_address_width{4}" class="memory" name="prim_ram_A16x36_B16x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="4" port_class="address1"/>
              <input name="portbaddr" num_pins="4" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A16x36_B16x36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A16x36_B16x36.portbdatain"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portadataout"/>
              <delay_constant in_port="prim_ram_A16x36_B16x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A16x36_B16x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A16x36_B16x36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A16x36_B16x36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A16x36_B16x36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A16x36_B16x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A16x36_B16x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A16x36_B16x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A16x36_B16x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A16x36_B16x36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A16x36_B16x36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A16x36_B16x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A16x36_B16x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A16x36_B16x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A16x36_B16x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A16x36_B16x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A16x36_B16x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A16x36_B16x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A16x36_B16x36[0].clk_portbout[0] prim_ram_A16x36_B16x36[0].clk_portbin[0] prim_ram_A16x36_B16x36[0].clk_portain[0] prim_ram_A16x36_B16x36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A16x36_B16x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[3:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[3:0]" output="prim_ram_A16x36_B16x36[0].portaaddr[3:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[3:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].portaaddr[3:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[3:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[3:0]" output="prim_ram_A16x36_B16x36[0].portbaddr[3:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[3:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].portbaddr[3:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A16x36_B16x36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A16x36_B16x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A16x36_B16x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A16x36_B16x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A16x36_B16x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_288_A8x36_B8x36_composite_prim_ram_1x(A8x36_B8x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{3}.port_b_address_width{3}" class="memory" name="prim_ram_A8x36_B8x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="3" port_class="address1"/>
              <input name="portbaddr" num_pins="3" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A8x36_B8x36.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A8x36_B8x36.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A8x36_B8x36.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portbdatain"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_A8x36_B8x36.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A8x36_B8x36.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A8x36_B8x36.eccstatus" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A8x36_B8x36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A8x36_B8x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A8x36_B8x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A8x36_B8x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A8x36_B8x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A8x36_B8x36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A8x36_B8x36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A8x36_B8x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A8x36_B8x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A8x36_B8x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A8x36_B8x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A8x36_B8x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A8x36_B8x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A8x36_B8x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A8x36_B8x36[0].clk_portbout[0] prim_ram_A8x36_B8x36[0].clk_portbin[0] prim_ram_A8x36_B8x36[0].clk_portain[0] prim_ram_A8x36_B8x36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A8x36_B8x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[2:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[2:0]" output="prim_ram_A8x36_B8x36[0].portaaddr[2:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[2:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].portaaddr[2:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[2:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[2:0]" output="prim_ram_A8x36_B8x36[0].portbaddr[2:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[2:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].portbaddr[2:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A8x36_B8x36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A8x36_B8x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A8x36_B8x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A8x36_B8x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_288_A8x36_B8x36_composite_prim_ram_1x(A8x36_B8x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{3}.port_b_address_width{3}" class="memory" name="prim_ram_A8x36_B8x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="3" port_class="address1"/>
              <input name="portbaddr" num_pins="3" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A8x36_B8x36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A8x36_B8x36.portbdatain"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portadataout"/>
              <delay_constant in_port="prim_ram_A8x36_B8x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A8x36_B8x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A8x36_B8x36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A8x36_B8x36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A8x36_B8x36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A8x36_B8x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A8x36_B8x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A8x36_B8x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A8x36_B8x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A8x36_B8x36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A8x36_B8x36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A8x36_B8x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A8x36_B8x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A8x36_B8x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A8x36_B8x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A8x36_B8x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A8x36_B8x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A8x36_B8x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A8x36_B8x36[0].clk_portbout[0] prim_ram_A8x36_B8x36[0].clk_portbin[0] prim_ram_A8x36_B8x36[0].clk_portain[0] prim_ram_A8x36_B8x36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A8x36_B8x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[2:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[2:0]" output="prim_ram_A8x36_B8x36[0].portaaddr[2:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[2:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].portaaddr[2:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[2:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[2:0]" output="prim_ram_A8x36_B8x36[0].portbaddr[2:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[2:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].portbaddr[2:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A8x36_B8x36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A8x36_B8x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A8x36_B8x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A8x36_B8x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A8x36_B8x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_144_A4x36_B4x36_composite_prim_ram_1x(A4x36_B4x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{2}.port_b_address_width{2}" class="memory" name="prim_ram_A4x36_B4x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="2" port_class="address1"/>
              <input name="portbaddr" num_pins="2" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A4x36_B4x36.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A4x36_B4x36.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A4x36_B4x36.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portbdatain"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_A4x36_B4x36.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A4x36_B4x36.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A4x36_B4x36.eccstatus" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A4x36_B4x36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A4x36_B4x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A4x36_B4x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A4x36_B4x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A4x36_B4x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A4x36_B4x36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A4x36_B4x36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A4x36_B4x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A4x36_B4x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A4x36_B4x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A4x36_B4x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A4x36_B4x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A4x36_B4x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A4x36_B4x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A4x36_B4x36[0].clk_portbout[0] prim_ram_A4x36_B4x36[0].clk_portbin[0] prim_ram_A4x36_B4x36[0].clk_portain[0] prim_ram_A4x36_B4x36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A4x36_B4x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[1:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[1:0]" output="prim_ram_A4x36_B4x36[0].portaaddr[1:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[1:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].portaaddr[1:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[1:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[1:0]" output="prim_ram_A4x36_B4x36[0].portbaddr[1:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[1:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].portbaddr[1:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A4x36_B4x36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A4x36_B4x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A4x36_B4x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A4x36_B4x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_144_A4x36_B4x36_composite_prim_ram_1x(A4x36_B4x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{2}.port_b_address_width{2}" class="memory" name="prim_ram_A4x36_B4x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="2" port_class="address1"/>
              <input name="portbaddr" num_pins="2" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A4x36_B4x36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A4x36_B4x36.portbdatain"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portadataout"/>
              <delay_constant in_port="prim_ram_A4x36_B4x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A4x36_B4x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A4x36_B4x36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A4x36_B4x36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A4x36_B4x36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A4x36_B4x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A4x36_B4x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A4x36_B4x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A4x36_B4x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A4x36_B4x36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A4x36_B4x36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A4x36_B4x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A4x36_B4x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A4x36_B4x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A4x36_B4x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A4x36_B4x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A4x36_B4x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A4x36_B4x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A4x36_B4x36[0].clk_portbout[0] prim_ram_A4x36_B4x36[0].clk_portbin[0] prim_ram_A4x36_B4x36[0].clk_portain[0] prim_ram_A4x36_B4x36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A4x36_B4x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[1:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[1:0]" output="prim_ram_A4x36_B4x36[0].portaaddr[1:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[1:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].portaaddr[1:0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[1:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[1:0]" output="prim_ram_A4x36_B4x36[0].portbaddr[1:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[1:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].portbaddr[1:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A4x36_B4x36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A4x36_B4x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A4x36_B4x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A4x36_B4x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A4x36_B4x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_72_A2x36_B2x36_composite_prim_ram_1x(A2x36_B2x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{1}.port_b_address_width{1}" class="memory" name="prim_ram_A2x36_B2x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <input name="portbaddr" num_pins="1" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A2x36_B2x36.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A2x36_B2x36.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A2x36_B2x36.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portbdatain"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_A2x36_B2x36.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A2x36_B2x36.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A2x36_B2x36.eccstatus" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A2x36_B2x36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A2x36_B2x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A2x36_B2x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A2x36_B2x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A2x36_B2x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A2x36_B2x36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A2x36_B2x36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A2x36_B2x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A2x36_B2x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A2x36_B2x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A2x36_B2x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A2x36_B2x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A2x36_B2x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A2x36_B2x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A2x36_B2x36[0].clk_portbout[0] prim_ram_A2x36_B2x36[0].clk_portbin[0] prim_ram_A2x36_B2x36[0].clk_portain[0] prim_ram_A2x36_B2x36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A2x36_B2x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[0]" name="interconnect_common_ram_block_M144K_addr_a_in_[0]" output="prim_ram_A2x36_B2x36[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].portaaddr[0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[0]" name="interconnect_common_ram_block_M144K_addr_b_in_[0]" output="prim_ram_A2x36_B2x36[0].portbaddr[0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].portbaddr[0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A2x36_B2x36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A2x36_B2x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A2x36_B2x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A2x36_B2x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_72_A2x36_B2x36_composite_prim_ram_1x(A2x36_B2x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{1}.port_b_address_width{1}" class="memory" name="prim_ram_A2x36_B2x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <input name="portbaddr" num_pins="1" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A2x36_B2x36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A2x36_B2x36.portbdatain"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portadataout"/>
              <delay_constant in_port="prim_ram_A2x36_B2x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A2x36_B2x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A2x36_B2x36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A2x36_B2x36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A2x36_B2x36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A2x36_B2x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A2x36_B2x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A2x36_B2x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A2x36_B2x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A2x36_B2x36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A2x36_B2x36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A2x36_B2x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A2x36_B2x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A2x36_B2x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A2x36_B2x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A2x36_B2x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A2x36_B2x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A2x36_B2x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A2x36_B2x36[0].clk_portbout[0] prim_ram_A2x36_B2x36[0].clk_portbin[0] prim_ram_A2x36_B2x36[0].clk_portain[0] prim_ram_A2x36_B2x36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A2x36_B2x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[0]" name="interconnect_common_ram_block_M144K_addr_a_in_[0]" output="prim_ram_A2x36_B2x36[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].portaaddr[0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[0]" name="interconnect_common_ram_block_M144K_addr_b_in_[0]" output="prim_ram_A2x36_B2x36[0].portbaddr[0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].portbaddr[0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A2x36_B2x36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A2x36_B2x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A2x36_B2x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A2x36_B2x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A2x36_B2x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_class_size_36_A1x36_B1x36_composite_prim_ram_1x(A1x36_B1x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}.port_a_address_width{0}.port_b_address_width{0}" class="memory" name="prim_ram_A1x36_B1x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <input name="portbaddr" num_pins="1" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_A1x36_B1x36.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A1x36_B1x36.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_A1x36_B1x36.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portbdatain"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_A1x36_B1x36.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A1x36_B1x36.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_A1x36_B1x36.eccstatus" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A1x36_B1x36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A1x36_B1x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A1x36_B1x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A1x36_B1x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A1x36_B1x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A1x36_B1x36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A1x36_B1x36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A1x36_B1x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A1x36_B1x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A1x36_B1x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A1x36_B1x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A1x36_B1x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A1x36_B1x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A1x36_B1x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A1x36_B1x36[0].clk_portbout[0] prim_ram_A1x36_B1x36[0].clk_portbin[0] prim_ram_A1x36_B1x36[0].clk_portain[0] prim_ram_A1x36_B1x36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A1x36_B1x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[0]" name="interconnect_common_ram_block_M144K_addr_a_in_[0]" output="prim_ram_A1x36_B1x36[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].portaaddr[0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[0]" name="interconnect_common_ram_block_M144K_addr_b_in_[0]" output="prim_ram_A1x36_B1x36[0].portbaddr[0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].portbaddr[0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A1x36_B1x36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A1x36_B1x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A1x36_B1x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A1x36_B1x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_class_size_36_A1x36_B1x36_composite_prim_ram_1x(A1x36_B1x36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}.port_a_address_width{0}.port_b_address_width{0}" class="memory" name="prim_ram_A1x36_B1x36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <input name="portbaddr" num_pins="1" port_class="address2"/>
              <input name="portbre" num_pins="1" port_class="read_en2"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1" port_class="write_en2"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <input name="portbdatain" num_pins="36" port_class="data_in2"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <output name="portbdataout" num_pins="36" port_class="data_out2"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1" port_class="clock"/>
              <clock name="clk_portbin" num_pins="1" port_class="clock"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_A1x36_B1x36.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_A1x36_B1x36.portbdatain"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.eccstatus"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portadataout"/>
              <delay_constant in_port="prim_ram_A1x36_B1x36.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_A1x36_B1x36.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbwe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_A1x36_B1x36.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_A1x36_B1x36.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_A1x36_B1x36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_A1x36_B1x36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_A1x36_B1x36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_A1x36_B1x36[0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_A1x36_B1x36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]" output="prim_ram_A1x36_B1x36[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].portbbyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_A1x36_B1x36[0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_A1x36_B1x36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_A1x36_B1x36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_A1x36_B1x36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_A1x36_B1x36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_A1x36_B1x36[0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]" output="prim_ram_A1x36_B1x36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_A1x36_B1x36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_A1x36_B1x36[0].clk_portbout[0] prim_ram_A1x36_B1x36[0].clk_portbin[0] prim_ram_A1x36_B1x36[0].clk_portain[0] prim_ram_A1x36_B1x36[0].clk_portaout[0] "/>
              <complete input="prim_ram_A1x36_B1x36[0].eccstatus[2:0]" name="interconnect_common_ram_block_M144K_control_out_[2:0]" output="ram_block_M144K.control_out[2:0]"/>
              <complete input="ram_block_M144K.addr_a_in[0]" name="interconnect_common_ram_block_M144K_addr_a_in_[0]" output="prim_ram_A1x36_B1x36[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].portaaddr[0]"/>
              </complete>
              <complete input="ram_block_M144K.addr_b_in[0]" name="interconnect_common_ram_block_M144K_addr_b_in_[0]" output="prim_ram_A1x36_B1x36[0].portbaddr[0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].portbaddr[0]"/>
              </complete>
              <direct input="ram_block_M144K.data_b_in[35:0]" name="interconnect_split_ram_block_M144K_data_b_in_[35:0]" output="prim_ram_A1x36_B1x36[0].portbdatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_b_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].portbdatain[35:0]"/>
              </direct>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_A1x36_B1x36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_A1x36_B1x36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_A1x36_B1x36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
              <direct input="prim_ram_A1x36_B1x36[0].portbdataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_2" output="ram_block_M144K.data_out[71:36]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_144K_16Kx9_composite_prim_ram_1x(16Kx9)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{14}" class="memory" name="prim_ram_16Kx9" num_pb="1">
              <input name="portadatain" num_pins="9" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="14" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="9" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_16Kx9.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.portawe"/>
              <delay_constant in_port="prim_ram_16Kx9.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_16Kx9.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_16Kx9[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_16Kx9[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_16Kx9[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_16Kx9[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_16Kx9[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_16Kx9[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_16Kx9[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_16Kx9[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_16Kx9[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_16Kx9[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_16Kx9[0].clk_portain[0] prim_ram_16Kx9[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]" output="prim_ram_16Kx9[0].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].portaaddr[13:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[8:0]" name="interconnect_split_ram_block_M144K_data_a_in_[8:0]" output="prim_ram_16Kx9[0].portadatain[8:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[8:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].portadatain[8:0]"/>
              </direct>
              <direct input="prim_ram_16Kx9[0].portadataout[8:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[8:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_144K_16Kx9_composite_prim_ram_1x(16Kx9)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{14}" class="memory" name="prim_ram_16Kx9" num_pb="1">
              <input name="portadatain" num_pins="9" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="14" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="9" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.portawe"/>
              <delay_constant in_port="prim_ram_16Kx9.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_16Kx9[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_16Kx9[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_16Kx9[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_16Kx9[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_16Kx9[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_16Kx9[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_16Kx9[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_16Kx9[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_16Kx9[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_16Kx9[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_16Kx9[0].clk_portain[0] prim_ram_16Kx9[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]" output="prim_ram_16Kx9[0].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].portaaddr[13:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[8:0]" name="interconnect_split_ram_block_M144K_data_a_in_[8:0]" output="prim_ram_16Kx9[0].portadatain[8:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[8:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].portadatain[8:0]"/>
              </direct>
              <direct input="prim_ram_16Kx9[0].portadataout[8:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[8:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_144K_8Kx18_composite_prim_ram_1x(8Kx18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{13}" class="memory" name="prim_ram_8Kx18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="13" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_8Kx18.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.portawe"/>
              <delay_constant in_port="prim_ram_8Kx18.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_8Kx18.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_8Kx18[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_8Kx18[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_8Kx18[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_8Kx18[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_8Kx18[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_8Kx18[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_8Kx18[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_8Kx18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_8Kx18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_8Kx18[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_8Kx18[0].clk_portain[0] prim_ram_8Kx18[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[12:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[12:0]" output="prim_ram_8Kx18[0].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[12:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].portaaddr[12:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[17:0]" name="interconnect_split_ram_block_M144K_data_a_in_[17:0]" output="prim_ram_8Kx18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[17:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_8Kx18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[17:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_144K_8Kx18_composite_prim_ram_1x(8Kx18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{13}" class="memory" name="prim_ram_8Kx18" num_pb="1">
              <input name="portadatain" num_pins="18" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="13" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.portawe"/>
              <delay_constant in_port="prim_ram_8Kx18.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_8Kx18[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_8Kx18[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_8Kx18[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_8Kx18[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_8Kx18[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_8Kx18[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_8Kx18[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_8Kx18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_8Kx18[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_8Kx18[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_8Kx18[0].clk_portain[0] prim_ram_8Kx18[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[12:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[12:0]" output="prim_ram_8Kx18[0].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[12:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].portaaddr[12:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[17:0]" name="interconnect_split_ram_block_M144K_data_a_in_[17:0]" output="prim_ram_8Kx18[0].portadatain[17:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[17:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].portadatain[17:0]"/>
              </direct>
              <direct input="prim_ram_8Kx18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[17:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_144K_4Kx36_composite_prim_ram_1x(4Kx36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{12}" class="memory" name="prim_ram_4Kx36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="12" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_4Kx36.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.portawe"/>
              <delay_constant in_port="prim_ram_4Kx36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_4Kx36.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_4Kx36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_4Kx36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_4Kx36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_4Kx36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_4Kx36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_4Kx36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_4Kx36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_4Kx36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_4Kx36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_4Kx36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_4Kx36[0].clk_portain[0] prim_ram_4Kx36[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[11:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[11:0]" output="prim_ram_4Kx36[0].portaaddr[11:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[11:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].portaaddr[11:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_4Kx36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_4Kx36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_144K_4Kx36_composite_prim_ram_1x(4Kx36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{12}" class="memory" name="prim_ram_4Kx36" num_pb="1">
              <input name="portadatain" num_pins="36" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="12" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.portawe"/>
              <delay_constant in_port="prim_ram_4Kx36.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_4Kx36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_4Kx36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_4Kx36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_4Kx36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_4Kx36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_4Kx36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_4Kx36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_4Kx36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_4Kx36[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_4Kx36[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_4Kx36[0].clk_portain[0] prim_ram_4Kx36[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[11:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[11:0]" output="prim_ram_4Kx36[0].portaaddr[11:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[11:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].portaaddr[11:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[35:0]" name="interconnect_split_ram_block_M144K_data_a_in_[35:0]" output="prim_ram_4Kx36[0].portadatain[35:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[35:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].portadatain[35:0]"/>
              </direct>
              <direct input="prim_ram_4Kx36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_144K_2Kx72_composite_prim_ram_1x(2Kx72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{11}" class="memory" name="prim_ram_2Kx72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="11" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_2Kx72.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.portawe"/>
              <delay_constant in_port="prim_ram_2Kx72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_2Kx72.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_2Kx72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_2Kx72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_2Kx72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_2Kx72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_2Kx72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_2Kx72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_2Kx72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_2Kx72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_2Kx72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_2Kx72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_2Kx72[0].clk_portain[0] prim_ram_2Kx72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[10:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[10:0]" output="prim_ram_2Kx72[0].portaaddr[10:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[10:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].portaaddr[10:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_2Kx72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_2Kx72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_144K_2Kx72_composite_prim_ram_1x(2Kx72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{11}" class="memory" name="prim_ram_2Kx72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="11" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.portawe"/>
              <delay_constant in_port="prim_ram_2Kx72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_2Kx72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_2Kx72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_2Kx72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_2Kx72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_2Kx72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_2Kx72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_2Kx72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_2Kx72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_2Kx72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_2Kx72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_2Kx72[0].clk_portain[0] prim_ram_2Kx72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[10:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[10:0]" output="prim_ram_2Kx72[0].portaaddr[10:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[10:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].portaaddr[10:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_2Kx72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_2Kx72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_72K_1Kx72_composite_prim_ram_1x(1Kx72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{10}" class="memory" name="prim_ram_1Kx72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="10" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_1Kx72.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.portawe"/>
              <delay_constant in_port="prim_ram_1Kx72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_1Kx72.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_1Kx72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_1Kx72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_1Kx72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_1Kx72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_1Kx72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_1Kx72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_1Kx72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_1Kx72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_1Kx72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_1Kx72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_1Kx72[0].clk_portain[0] prim_ram_1Kx72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[9:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[9:0]" output="prim_ram_1Kx72[0].portaaddr[9:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[9:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].portaaddr[9:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_1Kx72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_1Kx72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_72K_1Kx72_composite_prim_ram_1x(1Kx72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{10}" class="memory" name="prim_ram_1Kx72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="10" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.portawe"/>
              <delay_constant in_port="prim_ram_1Kx72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_1Kx72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_1Kx72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_1Kx72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_1Kx72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_1Kx72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_1Kx72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_1Kx72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_1Kx72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_1Kx72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_1Kx72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_1Kx72[0].clk_portain[0] prim_ram_1Kx72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[9:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[9:0]" output="prim_ram_1Kx72[0].portaaddr[9:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[9:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].portaaddr[9:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_1Kx72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_1Kx72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_36K_512x72_composite_prim_ram_1x(512x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{9}" class="memory" name="prim_ram_512x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="9" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_512x72.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.portawe"/>
              <delay_constant in_port="prim_ram_512x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_512x72.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_512x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_512x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_512x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_512x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_512x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_512x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_512x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_512x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_512x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_512x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_512x72[0].clk_portain[0] prim_ram_512x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[8:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[8:0]" output="prim_ram_512x72[0].portaaddr[8:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[8:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].portaaddr[8:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_512x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_512x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_36K_512x72_composite_prim_ram_1x(512x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{9}" class="memory" name="prim_ram_512x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="9" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.portawe"/>
              <delay_constant in_port="prim_ram_512x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_512x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_512x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_512x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_512x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_512x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_512x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_512x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_512x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_512x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_512x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_512x72[0].clk_portain[0] prim_ram_512x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[8:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[8:0]" output="prim_ram_512x72[0].portaaddr[8:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[8:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].portaaddr[8:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_512x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_512x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_18K_256x72_composite_prim_ram_1x(256x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{8}" class="memory" name="prim_ram_256x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="8" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_256x72.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.portawe"/>
              <delay_constant in_port="prim_ram_256x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_256x72.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_256x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_256x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_256x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_256x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_256x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_256x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_256x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_256x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_256x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_256x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_256x72[0].clk_portain[0] prim_ram_256x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[7:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[7:0]" output="prim_ram_256x72[0].portaaddr[7:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[7:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].portaaddr[7:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_256x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_256x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_18K_256x72_composite_prim_ram_1x(256x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{8}" class="memory" name="prim_ram_256x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="8" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.portawe"/>
              <delay_constant in_port="prim_ram_256x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_256x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_256x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_256x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_256x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_256x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_256x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_256x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_256x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_256x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_256x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_256x72[0].clk_portain[0] prim_ram_256x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[7:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[7:0]" output="prim_ram_256x72[0].portaaddr[7:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[7:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].portaaddr[7:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_256x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_256x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_9K_128x72_composite_prim_ram_1x(128x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{7}" class="memory" name="prim_ram_128x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="7" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_128x72.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.portawe"/>
              <delay_constant in_port="prim_ram_128x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_128x72.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_128x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_128x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_128x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_128x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_128x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_128x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_128x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_128x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_128x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_128x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_128x72[0].clk_portain[0] prim_ram_128x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[6:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[6:0]" output="prim_ram_128x72[0].portaaddr[6:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[6:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].portaaddr[6:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_128x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_128x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_9K_128x72_composite_prim_ram_1x(128x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{7}" class="memory" name="prim_ram_128x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="7" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.portawe"/>
              <delay_constant in_port="prim_ram_128x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_128x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_128x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_128x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_128x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_128x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_128x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_128x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_128x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_128x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_128x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_128x72[0].clk_portain[0] prim_ram_128x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[6:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[6:0]" output="prim_ram_128x72[0].portaaddr[6:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[6:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].portaaddr[6:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_128x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_128x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_4K_64x72_composite_prim_ram_1x(64x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{6}" class="memory" name="prim_ram_64x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="6" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_64x72.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.portawe"/>
              <delay_constant in_port="prim_ram_64x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_64x72.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_64x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_64x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_64x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_64x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_64x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_64x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_64x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_64x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_64x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_64x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_64x72[0].clk_portain[0] prim_ram_64x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[5:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[5:0]" output="prim_ram_64x72[0].portaaddr[5:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[5:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].portaaddr[5:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_64x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_64x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_4K_64x72_composite_prim_ram_1x(64x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{6}" class="memory" name="prim_ram_64x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="6" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.portawe"/>
              <delay_constant in_port="prim_ram_64x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_64x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_64x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_64x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_64x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_64x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_64x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_64x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_64x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_64x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_64x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_64x72[0].clk_portain[0] prim_ram_64x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[5:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[5:0]" output="prim_ram_64x72[0].portaaddr[5:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[5:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].portaaddr[5:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_64x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_64x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_2K_32x72_composite_prim_ram_1x(32x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{5}" class="memory" name="prim_ram_32x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="5" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_32x72.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.portawe"/>
              <delay_constant in_port="prim_ram_32x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_32x72.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_32x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_32x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_32x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_32x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_32x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_32x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_32x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_32x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_32x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_32x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_32x72[0].clk_portain[0] prim_ram_32x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[4:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[4:0]" output="prim_ram_32x72[0].portaaddr[4:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[4:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].portaaddr[4:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_32x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_32x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_2K_32x72_composite_prim_ram_1x(32x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{5}" class="memory" name="prim_ram_32x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="5" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.portawe"/>
              <delay_constant in_port="prim_ram_32x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_32x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_32x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_32x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_32x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_32x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_32x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_32x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_32x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_32x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_32x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_32x72[0].clk_portain[0] prim_ram_32x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[4:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[4:0]" output="prim_ram_32x72[0].portaaddr[4:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[4:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].portaaddr[4:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_32x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_32x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_1K_16x72_composite_prim_ram_1x(16x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{4}" class="memory" name="prim_ram_16x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="4" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_16x72.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.portawe"/>
              <delay_constant in_port="prim_ram_16x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_16x72.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_16x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_16x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_16x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_16x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_16x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_16x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_16x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_16x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_16x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_16x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_16x72[0].clk_portain[0] prim_ram_16x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[3:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[3:0]" output="prim_ram_16x72[0].portaaddr[3:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[3:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].portaaddr[3:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_16x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_16x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_1K_16x72_composite_prim_ram_1x(16x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{4}" class="memory" name="prim_ram_16x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="4" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.portawe"/>
              <delay_constant in_port="prim_ram_16x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_16x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_16x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_16x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_16x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_16x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_16x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_16x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_16x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_16x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_16x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_16x72[0].clk_portain[0] prim_ram_16x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[3:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[3:0]" output="prim_ram_16x72[0].portaaddr[3:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[3:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].portaaddr[3:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_16x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_16x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_576_8x72_composite_prim_ram_1x(8x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{3}" class="memory" name="prim_ram_8x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="3" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_8x72.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.portawe"/>
              <delay_constant in_port="prim_ram_8x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_8x72.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_8x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_8x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_8x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_8x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_8x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_8x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_8x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_8x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_8x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_8x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_8x72[0].clk_portain[0] prim_ram_8x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[2:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[2:0]" output="prim_ram_8x72[0].portaaddr[2:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[2:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].portaaddr[2:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_8x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_8x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_576_8x72_composite_prim_ram_1x(8x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{3}" class="memory" name="prim_ram_8x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="3" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.portawe"/>
              <delay_constant in_port="prim_ram_8x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_8x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_8x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_8x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_8x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_8x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_8x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_8x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_8x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_8x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_8x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_8x72[0].clk_portain[0] prim_ram_8x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[2:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[2:0]" output="prim_ram_8x72[0].portaaddr[2:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[2:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].portaaddr[2:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_8x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_8x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_288_4x72_composite_prim_ram_1x(4x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{2}" class="memory" name="prim_ram_4x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="2" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_4x72.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.portawe"/>
              <delay_constant in_port="prim_ram_4x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_4x72.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_4x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_4x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_4x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_4x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_4x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_4x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_4x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_4x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_4x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_4x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_4x72[0].clk_portain[0] prim_ram_4x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[1:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[1:0]" output="prim_ram_4x72[0].portaaddr[1:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[1:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].portaaddr[1:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_4x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_4x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_288_4x72_composite_prim_ram_1x(4x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{2}" class="memory" name="prim_ram_4x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="2" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.portawe"/>
              <delay_constant in_port="prim_ram_4x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_4x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_4x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_4x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_4x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_4x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_4x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_4x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_4x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_4x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_4x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_4x72[0].clk_portain[0] prim_ram_4x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[1:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[1:0]" output="prim_ram_4x72[0].portaaddr[1:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[1:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].portaaddr[1:0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_4x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_4x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_144_2x72_composite_prim_ram_1x(2x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{1}" class="memory" name="prim_ram_2x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_2x72.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.portawe"/>
              <delay_constant in_port="prim_ram_2x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_2x72.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_2x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_2x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_2x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_2x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_2x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_2x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_2x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_2x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_2x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_2x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_2x72[0].clk_portain[0] prim_ram_2x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[0]" name="interconnect_common_ram_block_M144K_addr_a_in_[0]" output="prim_ram_2x72[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].portaaddr[0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_2x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_2x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_144_2x72_composite_prim_ram_1x(2x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{1}" class="memory" name="prim_ram_2x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.portawe"/>
              <delay_constant in_port="prim_ram_2x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_2x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_2x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_2x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_2x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_2x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_2x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_2x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_2x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_2x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_2x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_2x72[0].clk_portain[0] prim_ram_2x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[0]" name="interconnect_common_ram_block_M144K_addr_a_in_[0]" output="prim_ram_2x72[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].portaaddr[0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_2x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_2x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_reg-out_class_size_72_1x72_composite_prim_ram_1x(1x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{reg}.port_a_address_width{0}" class="memory" name="prim_ram_1x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_1x72.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.portawe"/>
              <delay_constant in_port="prim_ram_1x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_1x72.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_1x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_1x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_1x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_1x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_1x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_1x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_1x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_1x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_1x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_1x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_1x72[0].clk_portain[0] prim_ram_1x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[0]" name="interconnect_common_ram_block_M144K_addr_a_in_[0]" output="prim_ram_1x72[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].portaaddr[0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_1x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_1x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="single_port_combout_class_size_72_1x72_composite_prim_ram_1x(1x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{single_port}.output_type{comb}.port_a_address_width{0}" class="memory" name="prim_ram_1x72" num_pb="1">
              <input name="portadatain" num_pins="72" port_class="data_in1"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1" port_class="write_en1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.portawe" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.portaaddr"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.portawe"/>
              <delay_constant in_port="prim_ram_1x72.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.portaaddr" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.portawe" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_1x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_1x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_1x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_1x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_1x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_1x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_1x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_1x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15:8]" name="interconnect_common_ram_block_M144K_control_in_[15:8]" output="prim_ram_1x72[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[15:8]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].portabyteenamasks[7:0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_1x72[0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_1x72[0].clk_portain[0] prim_ram_1x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[0]" name="interconnect_common_ram_block_M144K_addr_a_in_[0]" output="prim_ram_1x72[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].portaaddr[0]"/>
              </complete>
              <direct input="ram_block_M144K.data_a_in[71:0]" name="interconnect_split_ram_block_M144K_data_a_in_[71:0]" output="prim_ram_1x72[0].portadatain[71:0]">
                <delay_constant in_port="ram_block_M144K.data_a_in[71:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].portadatain[71:0]"/>
              </direct>
              <direct input="prim_ram_1x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_144K_16Kx9_composite_prim_ram_1x(16Kx9)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{14}" class="memory" name="prim_ram_16Kx9" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="14" port_class="address1"/>
              <output name="portadataout" num_pins="9" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_16Kx9.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.portaaddr"/>
              <delay_constant in_port="prim_ram_16Kx9.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_16Kx9.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_16Kx9[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_16Kx9[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_16Kx9[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_16Kx9[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_16Kx9[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_16Kx9[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_16Kx9[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_16Kx9[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_16Kx9[0].clk_portain[0] prim_ram_16Kx9[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]" output="prim_ram_16Kx9[0].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].portaaddr[13:0]"/>
              </complete>
              <direct input="prim_ram_16Kx9[0].portadataout[8:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[8:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_144K_16Kx9_composite_prim_ram_1x(16Kx9)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{14}" class="memory" name="prim_ram_16Kx9" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="14" port_class="address1"/>
              <output name="portadataout" num_pins="9" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16Kx9.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16Kx9.portaaddr"/>
              <delay_constant in_port="prim_ram_16Kx9.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <delay_constant in_port="prim_ram_16Kx9.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16Kx9.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16Kx9.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_16Kx9[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_16Kx9[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_16Kx9[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_16Kx9[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_16Kx9[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_16Kx9[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_16Kx9[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_16Kx9[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_16Kx9[0].clk_portain[0] prim_ram_16Kx9[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]" output="prim_ram_16Kx9[0].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16Kx9[0].portaaddr[13:0]"/>
              </complete>
              <direct input="prim_ram_16Kx9[0].portadataout[8:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[8:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_144K_8Kx18_composite_prim_ram_1x(8Kx18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{13}" class="memory" name="prim_ram_8Kx18" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="13" port_class="address1"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_8Kx18.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.portaaddr"/>
              <delay_constant in_port="prim_ram_8Kx18.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_8Kx18.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_8Kx18[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_8Kx18[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_8Kx18[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_8Kx18[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_8Kx18[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_8Kx18[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_8Kx18[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_8Kx18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_8Kx18[0].clk_portain[0] prim_ram_8Kx18[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[12:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[12:0]" output="prim_ram_8Kx18[0].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[12:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].portaaddr[12:0]"/>
              </complete>
              <direct input="prim_ram_8Kx18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[17:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_144K_8Kx18_composite_prim_ram_1x(8Kx18)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{13}" class="memory" name="prim_ram_8Kx18" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="13" port_class="address1"/>
              <output name="portadataout" num_pins="18" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8Kx18.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8Kx18.portaaddr"/>
              <delay_constant in_port="prim_ram_8Kx18.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <delay_constant in_port="prim_ram_8Kx18.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8Kx18.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8Kx18.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_8Kx18[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_8Kx18[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_8Kx18[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_8Kx18[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_8Kx18[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_8Kx18[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_8Kx18[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_8Kx18[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_8Kx18[0].clk_portain[0] prim_ram_8Kx18[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[12:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[12:0]" output="prim_ram_8Kx18[0].portaaddr[12:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[12:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8Kx18[0].portaaddr[12:0]"/>
              </complete>
              <direct input="prim_ram_8Kx18[0].portadataout[17:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[17:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_144K_4Kx36_composite_prim_ram_1x(4Kx36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{12}" class="memory" name="prim_ram_4Kx36" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="12" port_class="address1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_4Kx36.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.portaaddr"/>
              <delay_constant in_port="prim_ram_4Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_4Kx36.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_4Kx36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_4Kx36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_4Kx36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_4Kx36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_4Kx36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_4Kx36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_4Kx36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_4Kx36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_4Kx36[0].clk_portain[0] prim_ram_4Kx36[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[11:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[11:0]" output="prim_ram_4Kx36[0].portaaddr[11:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[11:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].portaaddr[11:0]"/>
              </complete>
              <direct input="prim_ram_4Kx36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_144K_4Kx36_composite_prim_ram_1x(4Kx36)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{12}" class="memory" name="prim_ram_4Kx36" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="12" port_class="address1"/>
              <output name="portadataout" num_pins="36" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4Kx36.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4Kx36.portaaddr"/>
              <delay_constant in_port="prim_ram_4Kx36.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <delay_constant in_port="prim_ram_4Kx36.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4Kx36.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4Kx36.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_4Kx36[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_4Kx36[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_4Kx36[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_4Kx36[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_4Kx36[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_4Kx36[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_4Kx36[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_4Kx36[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_4Kx36[0].clk_portain[0] prim_ram_4Kx36[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[11:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[11:0]" output="prim_ram_4Kx36[0].portaaddr[11:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[11:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4Kx36[0].portaaddr[11:0]"/>
              </complete>
              <direct input="prim_ram_4Kx36[0].portadataout[35:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[35:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_144K_2Kx72_composite_prim_ram_1x(2Kx72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{11}" class="memory" name="prim_ram_2Kx72" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="11" port_class="address1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_2Kx72.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.portaaddr"/>
              <delay_constant in_port="prim_ram_2Kx72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_2Kx72.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_2Kx72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_2Kx72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_2Kx72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_2Kx72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_2Kx72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_2Kx72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_2Kx72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_2Kx72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_2Kx72[0].clk_portain[0] prim_ram_2Kx72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[10:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[10:0]" output="prim_ram_2Kx72[0].portaaddr[10:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[10:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].portaaddr[10:0]"/>
              </complete>
              <direct input="prim_ram_2Kx72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_144K_2Kx72_composite_prim_ram_1x(2Kx72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{11}" class="memory" name="prim_ram_2Kx72" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="11" port_class="address1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2Kx72.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2Kx72.portaaddr"/>
              <delay_constant in_port="prim_ram_2Kx72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_2Kx72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2Kx72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2Kx72.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_2Kx72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_2Kx72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_2Kx72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_2Kx72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_2Kx72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_2Kx72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_2Kx72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_2Kx72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_2Kx72[0].clk_portain[0] prim_ram_2Kx72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[10:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[10:0]" output="prim_ram_2Kx72[0].portaaddr[10:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[10:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2Kx72[0].portaaddr[10:0]"/>
              </complete>
              <direct input="prim_ram_2Kx72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_72K_1Kx72_composite_prim_ram_1x(1Kx72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{10}" class="memory" name="prim_ram_1Kx72" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="10" port_class="address1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_1Kx72.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.portaaddr"/>
              <delay_constant in_port="prim_ram_1Kx72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_1Kx72.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_1Kx72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_1Kx72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_1Kx72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_1Kx72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_1Kx72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_1Kx72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_1Kx72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_1Kx72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_1Kx72[0].clk_portain[0] prim_ram_1Kx72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[9:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[9:0]" output="prim_ram_1Kx72[0].portaaddr[9:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[9:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].portaaddr[9:0]"/>
              </complete>
              <direct input="prim_ram_1Kx72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_72K_1Kx72_composite_prim_ram_1x(1Kx72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{10}" class="memory" name="prim_ram_1Kx72" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="10" port_class="address1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1Kx72.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1Kx72.portaaddr"/>
              <delay_constant in_port="prim_ram_1Kx72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <delay_constant in_port="prim_ram_1Kx72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1Kx72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1Kx72.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_1Kx72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_1Kx72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_1Kx72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_1Kx72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_1Kx72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_1Kx72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_1Kx72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_1Kx72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_1Kx72[0].clk_portain[0] prim_ram_1Kx72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[9:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[9:0]" output="prim_ram_1Kx72[0].portaaddr[9:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[9:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1Kx72[0].portaaddr[9:0]"/>
              </complete>
              <direct input="prim_ram_1Kx72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_36K_512x72_composite_prim_ram_1x(512x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{9}" class="memory" name="prim_ram_512x72" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="9" port_class="address1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_512x72.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.portaaddr"/>
              <delay_constant in_port="prim_ram_512x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_512x72.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_512x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_512x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_512x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_512x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_512x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_512x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_512x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_512x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_512x72[0].clk_portain[0] prim_ram_512x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[8:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[8:0]" output="prim_ram_512x72[0].portaaddr[8:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[8:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].portaaddr[8:0]"/>
              </complete>
              <direct input="prim_ram_512x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_36K_512x72_composite_prim_ram_1x(512x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{9}" class="memory" name="prim_ram_512x72" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="9" port_class="address1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_512x72.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_512x72.portaaddr"/>
              <delay_constant in_port="prim_ram_512x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <delay_constant in_port="prim_ram_512x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_512x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_512x72.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_512x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_512x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_512x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_512x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_512x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_512x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_512x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_512x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_512x72[0].clk_portain[0] prim_ram_512x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[8:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[8:0]" output="prim_ram_512x72[0].portaaddr[8:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[8:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_512x72[0].portaaddr[8:0]"/>
              </complete>
              <direct input="prim_ram_512x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_18K_256x72_composite_prim_ram_1x(256x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{8}" class="memory" name="prim_ram_256x72" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="8" port_class="address1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_256x72.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.portaaddr"/>
              <delay_constant in_port="prim_ram_256x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_256x72.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_256x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_256x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_256x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_256x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_256x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_256x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_256x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_256x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_256x72[0].clk_portain[0] prim_ram_256x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[7:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[7:0]" output="prim_ram_256x72[0].portaaddr[7:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[7:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].portaaddr[7:0]"/>
              </complete>
              <direct input="prim_ram_256x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_18K_256x72_composite_prim_ram_1x(256x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{8}" class="memory" name="prim_ram_256x72" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="8" port_class="address1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_256x72.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_256x72.portaaddr"/>
              <delay_constant in_port="prim_ram_256x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <delay_constant in_port="prim_ram_256x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_256x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_256x72.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_256x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_256x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_256x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_256x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_256x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_256x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_256x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_256x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_256x72[0].clk_portain[0] prim_ram_256x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[7:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[7:0]" output="prim_ram_256x72[0].portaaddr[7:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[7:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_256x72[0].portaaddr[7:0]"/>
              </complete>
              <direct input="prim_ram_256x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_9K_128x72_composite_prim_ram_1x(128x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{7}" class="memory" name="prim_ram_128x72" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="7" port_class="address1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_128x72.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.portaaddr"/>
              <delay_constant in_port="prim_ram_128x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_128x72.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_128x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_128x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_128x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_128x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_128x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_128x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_128x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_128x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_128x72[0].clk_portain[0] prim_ram_128x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[6:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[6:0]" output="prim_ram_128x72[0].portaaddr[6:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[6:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].portaaddr[6:0]"/>
              </complete>
              <direct input="prim_ram_128x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_9K_128x72_composite_prim_ram_1x(128x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{7}" class="memory" name="prim_ram_128x72" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="7" port_class="address1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_128x72.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_128x72.portaaddr"/>
              <delay_constant in_port="prim_ram_128x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <delay_constant in_port="prim_ram_128x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_128x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_128x72.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_128x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_128x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_128x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_128x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_128x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_128x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_128x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_128x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_128x72[0].clk_portain[0] prim_ram_128x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[6:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[6:0]" output="prim_ram_128x72[0].portaaddr[6:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[6:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_128x72[0].portaaddr[6:0]"/>
              </complete>
              <direct input="prim_ram_128x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_4K_64x72_composite_prim_ram_1x(64x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{6}" class="memory" name="prim_ram_64x72" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="6" port_class="address1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_64x72.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.portaaddr"/>
              <delay_constant in_port="prim_ram_64x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_64x72.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_64x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_64x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_64x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_64x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_64x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_64x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_64x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_64x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_64x72[0].clk_portain[0] prim_ram_64x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[5:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[5:0]" output="prim_ram_64x72[0].portaaddr[5:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[5:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].portaaddr[5:0]"/>
              </complete>
              <direct input="prim_ram_64x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_4K_64x72_composite_prim_ram_1x(64x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{6}" class="memory" name="prim_ram_64x72" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="6" port_class="address1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_64x72.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_64x72.portaaddr"/>
              <delay_constant in_port="prim_ram_64x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <delay_constant in_port="prim_ram_64x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_64x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_64x72.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_64x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_64x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_64x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_64x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_64x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_64x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_64x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_64x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_64x72[0].clk_portain[0] prim_ram_64x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[5:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[5:0]" output="prim_ram_64x72[0].portaaddr[5:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[5:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_64x72[0].portaaddr[5:0]"/>
              </complete>
              <direct input="prim_ram_64x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_2K_32x72_composite_prim_ram_1x(32x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{5}" class="memory" name="prim_ram_32x72" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="5" port_class="address1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_32x72.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.portaaddr"/>
              <delay_constant in_port="prim_ram_32x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_32x72.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_32x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_32x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_32x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_32x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_32x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_32x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_32x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_32x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_32x72[0].clk_portain[0] prim_ram_32x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[4:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[4:0]" output="prim_ram_32x72[0].portaaddr[4:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[4:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].portaaddr[4:0]"/>
              </complete>
              <direct input="prim_ram_32x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_2K_32x72_composite_prim_ram_1x(32x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{5}" class="memory" name="prim_ram_32x72" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="5" port_class="address1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_32x72.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_32x72.portaaddr"/>
              <delay_constant in_port="prim_ram_32x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <delay_constant in_port="prim_ram_32x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_32x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_32x72.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_32x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_32x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_32x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_32x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_32x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_32x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_32x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_32x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_32x72[0].clk_portain[0] prim_ram_32x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[4:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[4:0]" output="prim_ram_32x72[0].portaaddr[4:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[4:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_32x72[0].portaaddr[4:0]"/>
              </complete>
              <direct input="prim_ram_32x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_1K_16x72_composite_prim_ram_1x(16x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{4}" class="memory" name="prim_ram_16x72" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="4" port_class="address1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_16x72.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.portaaddr"/>
              <delay_constant in_port="prim_ram_16x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_16x72.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_16x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_16x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_16x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_16x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_16x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_16x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_16x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_16x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_16x72[0].clk_portain[0] prim_ram_16x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[3:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[3:0]" output="prim_ram_16x72[0].portaaddr[3:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[3:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].portaaddr[3:0]"/>
              </complete>
              <direct input="prim_ram_16x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_1K_16x72_composite_prim_ram_1x(16x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{4}" class="memory" name="prim_ram_16x72" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="4" port_class="address1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_16x72.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_16x72.portaaddr"/>
              <delay_constant in_port="prim_ram_16x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <delay_constant in_port="prim_ram_16x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_16x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_16x72.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_16x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_16x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_16x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_16x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_16x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_16x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_16x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_16x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_16x72[0].clk_portain[0] prim_ram_16x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[3:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[3:0]" output="prim_ram_16x72[0].portaaddr[3:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[3:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_16x72[0].portaaddr[3:0]"/>
              </complete>
              <direct input="prim_ram_16x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_576_8x72_composite_prim_ram_1x(8x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{3}" class="memory" name="prim_ram_8x72" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="3" port_class="address1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_8x72.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.portaaddr"/>
              <delay_constant in_port="prim_ram_8x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_8x72.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_8x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_8x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_8x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_8x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_8x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_8x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_8x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_8x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_8x72[0].clk_portain[0] prim_ram_8x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[2:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[2:0]" output="prim_ram_8x72[0].portaaddr[2:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[2:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].portaaddr[2:0]"/>
              </complete>
              <direct input="prim_ram_8x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_576_8x72_composite_prim_ram_1x(8x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{3}" class="memory" name="prim_ram_8x72" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="3" port_class="address1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_8x72.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_8x72.portaaddr"/>
              <delay_constant in_port="prim_ram_8x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <delay_constant in_port="prim_ram_8x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_8x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_8x72.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_8x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_8x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_8x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_8x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_8x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_8x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_8x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_8x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_8x72[0].clk_portain[0] prim_ram_8x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[2:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[2:0]" output="prim_ram_8x72[0].portaaddr[2:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[2:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_8x72[0].portaaddr[2:0]"/>
              </complete>
              <direct input="prim_ram_8x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_288_4x72_composite_prim_ram_1x(4x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{2}" class="memory" name="prim_ram_4x72" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="2" port_class="address1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_4x72.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.portaaddr"/>
              <delay_constant in_port="prim_ram_4x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_4x72.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_4x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_4x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_4x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_4x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_4x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_4x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_4x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_4x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_4x72[0].clk_portain[0] prim_ram_4x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[1:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[1:0]" output="prim_ram_4x72[0].portaaddr[1:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[1:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].portaaddr[1:0]"/>
              </complete>
              <direct input="prim_ram_4x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_288_4x72_composite_prim_ram_1x(4x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{2}" class="memory" name="prim_ram_4x72" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="2" port_class="address1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_4x72.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_4x72.portaaddr"/>
              <delay_constant in_port="prim_ram_4x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <delay_constant in_port="prim_ram_4x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_4x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_4x72.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_4x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_4x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_4x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_4x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_4x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_4x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_4x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_4x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_4x72[0].clk_portain[0] prim_ram_4x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[1:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[1:0]" output="prim_ram_4x72[0].portaaddr[1:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[1:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_4x72[0].portaaddr[1:0]"/>
              </complete>
              <direct input="prim_ram_4x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_144_2x72_composite_prim_ram_1x(2x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{1}" class="memory" name="prim_ram_2x72" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_2x72.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.portaaddr"/>
              <delay_constant in_port="prim_ram_2x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_2x72.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_2x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_2x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_2x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_2x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_2x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_2x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_2x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_2x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_2x72[0].clk_portain[0] prim_ram_2x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[0]" name="interconnect_common_ram_block_M144K_addr_a_in_[0]" output="prim_ram_2x72[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].portaaddr[0]"/>
              </complete>
              <direct input="prim_ram_2x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_144_2x72_composite_prim_ram_1x(2x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{1}" class="memory" name="prim_ram_2x72" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_2x72.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_2x72.portaaddr"/>
              <delay_constant in_port="prim_ram_2x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <delay_constant in_port="prim_ram_2x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_2x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_2x72.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_2x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_2x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_2x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_2x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_2x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_2x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_2x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_2x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_2x72[0].clk_portain[0] prim_ram_2x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[0]" name="interconnect_common_ram_block_M144K_addr_a_in_[0]" output="prim_ram_2x72[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_2x72[0].portaaddr[0]"/>
              </complete>
              <direct input="prim_ram_2x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_reg-out_class_size_72_1x72_composite_prim_ram_1x(1x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{0}" class="memory" name="prim_ram_1x72" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_1x72.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.portaaddr"/>
              <delay_constant in_port="prim_ram_1x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_1x72.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_1x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_1x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_1x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_1x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_1x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_1x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_1x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_1x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_1x72[0].clk_portain[0] prim_ram_1x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[0]" name="interconnect_common_ram_block_M144K_addr_a_in_[0]" output="prim_ram_1x72[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].portaaddr[0]"/>
              </complete>
              <direct input="prim_ram_1x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="rom_combout_class_size_72_1x72_composite_prim_ram_1x(1x72)">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{rom}.output_type{comb}.port_a_address_width{0}" class="memory" name="prim_ram_1x72" num_pb="1">
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portare" num_pins="1" port_class="read_en1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="1" port_class="address1"/>
              <output name="portadataout" num_pins="72" port_class="data_out1"/>
              <clock name="clk_portain" num_pins="1" port_class="clock"/>
              <clock name="clk_portaout" num_pins="1" port_class="clock"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_1x72.portaaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.ena2"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_1x72.portaaddr"/>
              <delay_constant in_port="prim_ram_1x72.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <delay_constant in_port="prim_ram_1x72.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_1x72.portadataout"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.ena2" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_1x72.portaaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_1x72[0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_1x72[0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_1x72[0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_1x72[0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_1x72[0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[5]" name="interconnect_common_ram_block_M144K_control_in_[5]" output="prim_ram_1x72[0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[6]" name="interconnect_common_ram_block_M144K_control_in_[6]" output="prim_ram_1x72[0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[6]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[7]" name="interconnect_common_ram_block_M144K_control_in_[7]" output="prim_ram_1x72[0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[7]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_1x72[0].clk_portain[0] prim_ram_1x72[0].clk_portaout[0] "/>
              <complete input="ram_block_M144K.addr_a_in[0]" name="interconnect_common_ram_block_M144K_addr_a_in_[0]" output="prim_ram_1x72[0].portaaddr[0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_1x72[0].portaaddr[0]"/>
              </complete>
              <direct input="prim_ram_1x72[0].portadataout[71:0]" name="interconnect_concat_ram_block_M144K_data_out_1" output="ram_block_M144K.data_out[71:0]"/>
            </interconnect>
          </mode>
          <mode name="dual_port_reg-out_mixed_width">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{reg}" name="prim_ram_dual_port_mixed_width" num_pb="36">
              <input name="portadatain" num_pins="72"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="14"/>
              <input name="portbre" num_pins="1"/>
              <input name="portawe" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="14"/>
              <output name="portbdataout" num_pins="72"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1"/>
              <clock name="clk_portain" num_pins="1"/>
              <clock name="clk_portaout" num_pins="1"/>
              <clock name="clk_portbout" num_pins="1"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_dual_port_mixed_width.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_dual_port_mixed_width.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_dual_port_mixed_width.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_dual_port_mixed_width.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_dual_port_mixed_width.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_dual_port_mixed_width.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_dual_port_mixed_width.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_dual_port_mixed_width.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.portbaddr"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_dual_port_mixed_width.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_dual_port_mixed_width.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_dual_port_mixed_width.eccstatus" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_dual_port_mixed_width.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_dual_port_mixed_width.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_dual_port_mixed_width.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_dual_port_mixed_width.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_dual_port_mixed_width.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_dual_port_mixed_width[35:0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35:0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_dual_port_mixed_width[35:0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35:0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_dual_port_mixed_width[35:0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35:0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_dual_port_mixed_width[35:0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35:0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_dual_port_mixed_width[35:0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35:0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_dual_port_mixed_width[35:0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35:0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_dual_port_mixed_width[35:0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35:0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_dual_port_mixed_width[35:0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35:0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_dual_port_mixed_width[35:0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35:0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_dual_port_mixed_width[35:0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35:0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.data_b_in" name="interconnect_full_ram_block_M144K_data_b_in_0" output="">
                <delay_constant in_port="ram_block_M144K.data_b_in" max="6.46e-10" min="1.25e-10" out_port=""/>
              </complete>
              <complete input="ram_block_M144K.data_a_in" name="interconnect_full_ram_block_M144K_data_a_in_0" output="prim_ram_dual_port_mixed_width[35:0].portadatain[71:0] ">
                <delay_constant in_port="ram_block_M144K.data_a_in" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35:0].portadatain[71:0] "/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_dual_port_mixed_width[35:0].clk_portbin[0] prim_ram_dual_port_mixed_width[35:0].clk_portain[0] prim_ram_dual_port_mixed_width[35:0].clk_portaout[0] prim_ram_dual_port_mixed_width[35:0].clk_portbout[0] "/>
              <complete input="prim_ram_dual_port_mixed_width[35:0].eccstatus[2:0] " name="interconnect_full_ram_block_M144K_control_out_0" output="ram_block_M144K.control_out"/>
              <complete input="prim_ram_dual_port_mixed_width[35:0].portbdataout[71:0] " name="interconnect_full_ram_block_M144K_data_out_0" output="ram_block_M144K.data_out"/>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_0" output="prim_ram_dual_port_mixed_width[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[0].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_1" output="prim_ram_dual_port_mixed_width[1].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[1].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_2" output="prim_ram_dual_port_mixed_width[2].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[2].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_3" output="prim_ram_dual_port_mixed_width[3].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[3].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_4" output="prim_ram_dual_port_mixed_width[4].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[4].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_5" output="prim_ram_dual_port_mixed_width[5].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[5].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_6" output="prim_ram_dual_port_mixed_width[6].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[6].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_7" output="prim_ram_dual_port_mixed_width[7].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[7].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_8" output="prim_ram_dual_port_mixed_width[8].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[8].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_9" output="prim_ram_dual_port_mixed_width[9].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[9].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_10" output="prim_ram_dual_port_mixed_width[10].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[10].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_11" output="prim_ram_dual_port_mixed_width[11].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[11].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_12" output="prim_ram_dual_port_mixed_width[12].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[12].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_13" output="prim_ram_dual_port_mixed_width[13].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[13].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_14" output="prim_ram_dual_port_mixed_width[14].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[14].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_15" output="prim_ram_dual_port_mixed_width[15].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[15].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_16" output="prim_ram_dual_port_mixed_width[16].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[16].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_17" output="prim_ram_dual_port_mixed_width[17].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[17].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_18" output="prim_ram_dual_port_mixed_width[18].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[18].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_19" output="prim_ram_dual_port_mixed_width[19].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[19].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_20" output="prim_ram_dual_port_mixed_width[20].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[20].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_21" output="prim_ram_dual_port_mixed_width[21].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[21].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_22" output="prim_ram_dual_port_mixed_width[22].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[22].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_23" output="prim_ram_dual_port_mixed_width[23].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[23].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_24" output="prim_ram_dual_port_mixed_width[24].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[24].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_25" output="prim_ram_dual_port_mixed_width[25].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[25].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_26" output="prim_ram_dual_port_mixed_width[26].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[26].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_27" output="prim_ram_dual_port_mixed_width[27].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[27].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_28" output="prim_ram_dual_port_mixed_width[28].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[28].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_29" output="prim_ram_dual_port_mixed_width[29].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[29].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_30" output="prim_ram_dual_port_mixed_width[30].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[30].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_31" output="prim_ram_dual_port_mixed_width[31].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[31].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_32" output="prim_ram_dual_port_mixed_width[32].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[32].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_33" output="prim_ram_dual_port_mixed_width[33].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[33].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_34" output="prim_ram_dual_port_mixed_width[34].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[34].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_35" output="prim_ram_dual_port_mixed_width[35].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_0" output="prim_ram_dual_port_mixed_width[0].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[0].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_1" output="prim_ram_dual_port_mixed_width[1].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[1].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_2" output="prim_ram_dual_port_mixed_width[2].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[2].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_3" output="prim_ram_dual_port_mixed_width[3].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[3].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_4" output="prim_ram_dual_port_mixed_width[4].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[4].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_5" output="prim_ram_dual_port_mixed_width[5].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[5].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_6" output="prim_ram_dual_port_mixed_width[6].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[6].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_7" output="prim_ram_dual_port_mixed_width[7].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[7].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_8" output="prim_ram_dual_port_mixed_width[8].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[8].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_9" output="prim_ram_dual_port_mixed_width[9].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[9].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_10" output="prim_ram_dual_port_mixed_width[10].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[10].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_11" output="prim_ram_dual_port_mixed_width[11].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[11].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_12" output="prim_ram_dual_port_mixed_width[12].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[12].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_13" output="prim_ram_dual_port_mixed_width[13].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[13].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_14" output="prim_ram_dual_port_mixed_width[14].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[14].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_15" output="prim_ram_dual_port_mixed_width[15].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[15].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_16" output="prim_ram_dual_port_mixed_width[16].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[16].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_17" output="prim_ram_dual_port_mixed_width[17].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[17].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_18" output="prim_ram_dual_port_mixed_width[18].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[18].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_19" output="prim_ram_dual_port_mixed_width[19].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[19].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_20" output="prim_ram_dual_port_mixed_width[20].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[20].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_21" output="prim_ram_dual_port_mixed_width[21].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[21].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_22" output="prim_ram_dual_port_mixed_width[22].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[22].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_23" output="prim_ram_dual_port_mixed_width[23].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[23].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_24" output="prim_ram_dual_port_mixed_width[24].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[24].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_25" output="prim_ram_dual_port_mixed_width[25].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[25].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_26" output="prim_ram_dual_port_mixed_width[26].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[26].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_27" output="prim_ram_dual_port_mixed_width[27].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[27].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_28" output="prim_ram_dual_port_mixed_width[28].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[28].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_29" output="prim_ram_dual_port_mixed_width[29].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[29].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_30" output="prim_ram_dual_port_mixed_width[30].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[30].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_31" output="prim_ram_dual_port_mixed_width[31].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[31].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_32" output="prim_ram_dual_port_mixed_width[32].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[32].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_33" output="prim_ram_dual_port_mixed_width[33].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[33].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_34" output="prim_ram_dual_port_mixed_width[34].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[34].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_35" output="prim_ram_dual_port_mixed_width[35].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_0" output="prim_ram_dual_port_mixed_width[0].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[0].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_1" output="prim_ram_dual_port_mixed_width[1].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[1].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_2" output="prim_ram_dual_port_mixed_width[2].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[2].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_3" output="prim_ram_dual_port_mixed_width[3].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[3].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_4" output="prim_ram_dual_port_mixed_width[4].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[4].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_5" output="prim_ram_dual_port_mixed_width[5].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[5].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_6" output="prim_ram_dual_port_mixed_width[6].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[6].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_7" output="prim_ram_dual_port_mixed_width[7].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[7].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_8" output="prim_ram_dual_port_mixed_width[8].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[8].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_9" output="prim_ram_dual_port_mixed_width[9].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[9].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_10" output="prim_ram_dual_port_mixed_width[10].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[10].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_11" output="prim_ram_dual_port_mixed_width[11].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[11].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_12" output="prim_ram_dual_port_mixed_width[12].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[12].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_13" output="prim_ram_dual_port_mixed_width[13].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[13].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_14" output="prim_ram_dual_port_mixed_width[14].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[14].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_15" output="prim_ram_dual_port_mixed_width[15].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[15].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_16" output="prim_ram_dual_port_mixed_width[16].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[16].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_17" output="prim_ram_dual_port_mixed_width[17].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[17].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_18" output="prim_ram_dual_port_mixed_width[18].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[18].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_19" output="prim_ram_dual_port_mixed_width[19].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[19].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_20" output="prim_ram_dual_port_mixed_width[20].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[20].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_21" output="prim_ram_dual_port_mixed_width[21].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[21].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_22" output="prim_ram_dual_port_mixed_width[22].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[22].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_23" output="prim_ram_dual_port_mixed_width[23].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[23].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_24" output="prim_ram_dual_port_mixed_width[24].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[24].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_25" output="prim_ram_dual_port_mixed_width[25].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[25].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_26" output="prim_ram_dual_port_mixed_width[26].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[26].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_27" output="prim_ram_dual_port_mixed_width[27].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[27].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_28" output="prim_ram_dual_port_mixed_width[28].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[28].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_29" output="prim_ram_dual_port_mixed_width[29].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[29].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_30" output="prim_ram_dual_port_mixed_width[30].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[30].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_31" output="prim_ram_dual_port_mixed_width[31].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[31].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_32" output="prim_ram_dual_port_mixed_width[32].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[32].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_33" output="prim_ram_dual_port_mixed_width[33].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[33].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_34" output="prim_ram_dual_port_mixed_width[34].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[34].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_35" output="prim_ram_dual_port_mixed_width[35].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35].portbaddr[13:0]"/>
              </direct>
            </interconnect>
          </mode>
          <mode name="dual_port_combout_mixed_width">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{dual_port}.output_type{comb}" name="prim_ram_dual_port_mixed_width" num_pb="36">
              <input name="portadatain" num_pins="72"/>
              <input name="clr1" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="14"/>
              <input name="portbre" num_pins="1"/>
              <input name="portawe" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portbaddr" num_pins="14"/>
              <output name="portbdataout" num_pins="72"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbin" num_pins="1"/>
              <clock name="clk_portain" num_pins="1"/>
              <clock name="clk_portaout" num_pins="1"/>
              <clock name="clk_portbout" num_pins="1"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_dual_port_mixed_width.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_dual_port_mixed_width.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_dual_port_mixed_width.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_dual_port_mixed_width.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_dual_port_mixed_width.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_dual_port_mixed_width.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_dual_port_mixed_width.portbaddr" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.portadatain"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.clr1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.ena1"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.portbre"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_dual_port_mixed_width.portbaddr"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_dual_port_mixed_width.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_dual_port_mixed_width.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.portadatain" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_dual_port_mixed_width.clr1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_dual_port_mixed_width.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_dual_port_mixed_width.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.ena1" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_dual_port_mixed_width.portbre" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_dual_port_mixed_width.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_dual_port_mixed_width.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_dual_port_mixed_width.portbaddr" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_dual_port_mixed_width[35:0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35:0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_dual_port_mixed_width[35:0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35:0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[10]" name="interconnect_common_ram_block_M144K_control_in_[10]" output="prim_ram_dual_port_mixed_width[35:0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[10]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35:0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[11]" name="interconnect_common_ram_block_M144K_control_in_[11]" output="prim_ram_dual_port_mixed_width[35:0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[11]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35:0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[12]" name="interconnect_common_ram_block_M144K_control_in_[12]" output="prim_ram_dual_port_mixed_width[35:0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[12]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35:0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_dual_port_mixed_width[35:0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35:0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_dual_port_mixed_width[35:0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35:0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_dual_port_mixed_width[35:0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35:0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_dual_port_mixed_width[35:0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35:0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_dual_port_mixed_width[35:0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35:0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.data_b_in" name="interconnect_full_ram_block_M144K_data_b_in_0" output="">
                <delay_constant in_port="ram_block_M144K.data_b_in" max="6.46e-10" min="1.25e-10" out_port=""/>
              </complete>
              <complete input="ram_block_M144K.data_a_in" name="interconnect_full_ram_block_M144K_data_a_in_0" output="prim_ram_dual_port_mixed_width[35:0].portadatain[71:0] ">
                <delay_constant in_port="ram_block_M144K.data_a_in" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35:0].portadatain[71:0] "/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_dual_port_mixed_width[35:0].clk_portbin[0] prim_ram_dual_port_mixed_width[35:0].clk_portain[0] prim_ram_dual_port_mixed_width[35:0].clk_portaout[0] prim_ram_dual_port_mixed_width[35:0].clk_portbout[0] "/>
              <complete input="prim_ram_dual_port_mixed_width[35:0].eccstatus[2:0] " name="interconnect_full_ram_block_M144K_control_out_0" output="ram_block_M144K.control_out"/>
              <complete input="prim_ram_dual_port_mixed_width[35:0].portbdataout[71:0] " name="interconnect_full_ram_block_M144K_data_out_0" output="ram_block_M144K.data_out"/>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_0" output="prim_ram_dual_port_mixed_width[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[0].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_1" output="prim_ram_dual_port_mixed_width[1].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[1].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_2" output="prim_ram_dual_port_mixed_width[2].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[2].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_3" output="prim_ram_dual_port_mixed_width[3].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[3].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_4" output="prim_ram_dual_port_mixed_width[4].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[4].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_5" output="prim_ram_dual_port_mixed_width[5].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[5].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_6" output="prim_ram_dual_port_mixed_width[6].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[6].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_7" output="prim_ram_dual_port_mixed_width[7].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[7].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_8" output="prim_ram_dual_port_mixed_width[8].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[8].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_9" output="prim_ram_dual_port_mixed_width[9].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[9].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_10" output="prim_ram_dual_port_mixed_width[10].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[10].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_11" output="prim_ram_dual_port_mixed_width[11].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[11].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_12" output="prim_ram_dual_port_mixed_width[12].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[12].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_13" output="prim_ram_dual_port_mixed_width[13].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[13].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_14" output="prim_ram_dual_port_mixed_width[14].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[14].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_15" output="prim_ram_dual_port_mixed_width[15].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[15].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_16" output="prim_ram_dual_port_mixed_width[16].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[16].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_17" output="prim_ram_dual_port_mixed_width[17].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[17].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_18" output="prim_ram_dual_port_mixed_width[18].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[18].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_19" output="prim_ram_dual_port_mixed_width[19].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[19].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_20" output="prim_ram_dual_port_mixed_width[20].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[20].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_21" output="prim_ram_dual_port_mixed_width[21].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[21].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_22" output="prim_ram_dual_port_mixed_width[22].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[22].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_23" output="prim_ram_dual_port_mixed_width[23].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[23].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_24" output="prim_ram_dual_port_mixed_width[24].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[24].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_25" output="prim_ram_dual_port_mixed_width[25].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[25].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_26" output="prim_ram_dual_port_mixed_width[26].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[26].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_27" output="prim_ram_dual_port_mixed_width[27].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[27].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_28" output="prim_ram_dual_port_mixed_width[28].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[28].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_29" output="prim_ram_dual_port_mixed_width[29].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[29].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_30" output="prim_ram_dual_port_mixed_width[30].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[30].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_31" output="prim_ram_dual_port_mixed_width[31].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[31].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_32" output="prim_ram_dual_port_mixed_width[32].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[32].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_33" output="prim_ram_dual_port_mixed_width[33].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[33].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_34" output="prim_ram_dual_port_mixed_width[34].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[34].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[9:2]" name="interconnect_common_ram_block_M144K_control_in_[9:2]_35" output="prim_ram_dual_port_mixed_width[35].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[9:2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_0" output="prim_ram_dual_port_mixed_width[0].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[0].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_1" output="prim_ram_dual_port_mixed_width[1].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[1].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_2" output="prim_ram_dual_port_mixed_width[2].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[2].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_3" output="prim_ram_dual_port_mixed_width[3].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[3].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_4" output="prim_ram_dual_port_mixed_width[4].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[4].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_5" output="prim_ram_dual_port_mixed_width[5].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[5].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_6" output="prim_ram_dual_port_mixed_width[6].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[6].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_7" output="prim_ram_dual_port_mixed_width[7].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[7].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_8" output="prim_ram_dual_port_mixed_width[8].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[8].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_9" output="prim_ram_dual_port_mixed_width[9].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[9].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_10" output="prim_ram_dual_port_mixed_width[10].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[10].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_11" output="prim_ram_dual_port_mixed_width[11].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[11].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_12" output="prim_ram_dual_port_mixed_width[12].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[12].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_13" output="prim_ram_dual_port_mixed_width[13].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[13].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_14" output="prim_ram_dual_port_mixed_width[14].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[14].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_15" output="prim_ram_dual_port_mixed_width[15].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[15].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_16" output="prim_ram_dual_port_mixed_width[16].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[16].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_17" output="prim_ram_dual_port_mixed_width[17].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[17].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_18" output="prim_ram_dual_port_mixed_width[18].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[18].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_19" output="prim_ram_dual_port_mixed_width[19].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[19].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_20" output="prim_ram_dual_port_mixed_width[20].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[20].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_21" output="prim_ram_dual_port_mixed_width[21].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[21].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_22" output="prim_ram_dual_port_mixed_width[22].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[22].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_23" output="prim_ram_dual_port_mixed_width[23].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[23].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_24" output="prim_ram_dual_port_mixed_width[24].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[24].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_25" output="prim_ram_dual_port_mixed_width[25].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[25].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_26" output="prim_ram_dual_port_mixed_width[26].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[26].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_27" output="prim_ram_dual_port_mixed_width[27].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[27].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_28" output="prim_ram_dual_port_mixed_width[28].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[28].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_29" output="prim_ram_dual_port_mixed_width[29].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[29].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_30" output="prim_ram_dual_port_mixed_width[30].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[30].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_31" output="prim_ram_dual_port_mixed_width[31].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[31].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_32" output="prim_ram_dual_port_mixed_width[32].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[32].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_33" output="prim_ram_dual_port_mixed_width[33].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[33].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_34" output="prim_ram_dual_port_mixed_width[34].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[34].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_35" output="prim_ram_dual_port_mixed_width[35].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_0" output="prim_ram_dual_port_mixed_width[0].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[0].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_1" output="prim_ram_dual_port_mixed_width[1].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[1].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_2" output="prim_ram_dual_port_mixed_width[2].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[2].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_3" output="prim_ram_dual_port_mixed_width[3].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[3].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_4" output="prim_ram_dual_port_mixed_width[4].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[4].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_5" output="prim_ram_dual_port_mixed_width[5].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[5].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_6" output="prim_ram_dual_port_mixed_width[6].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[6].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_7" output="prim_ram_dual_port_mixed_width[7].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[7].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_8" output="prim_ram_dual_port_mixed_width[8].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[8].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_9" output="prim_ram_dual_port_mixed_width[9].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[9].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_10" output="prim_ram_dual_port_mixed_width[10].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[10].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_11" output="prim_ram_dual_port_mixed_width[11].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[11].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_12" output="prim_ram_dual_port_mixed_width[12].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[12].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_13" output="prim_ram_dual_port_mixed_width[13].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[13].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_14" output="prim_ram_dual_port_mixed_width[14].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[14].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_15" output="prim_ram_dual_port_mixed_width[15].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[15].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_16" output="prim_ram_dual_port_mixed_width[16].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[16].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_17" output="prim_ram_dual_port_mixed_width[17].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[17].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_18" output="prim_ram_dual_port_mixed_width[18].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[18].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_19" output="prim_ram_dual_port_mixed_width[19].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[19].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_20" output="prim_ram_dual_port_mixed_width[20].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[20].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_21" output="prim_ram_dual_port_mixed_width[21].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[21].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_22" output="prim_ram_dual_port_mixed_width[22].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[22].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_23" output="prim_ram_dual_port_mixed_width[23].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[23].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_24" output="prim_ram_dual_port_mixed_width[24].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[24].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_25" output="prim_ram_dual_port_mixed_width[25].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[25].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_26" output="prim_ram_dual_port_mixed_width[26].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[26].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_27" output="prim_ram_dual_port_mixed_width[27].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[27].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_28" output="prim_ram_dual_port_mixed_width[28].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[28].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_29" output="prim_ram_dual_port_mixed_width[29].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[29].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_30" output="prim_ram_dual_port_mixed_width[30].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[30].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_31" output="prim_ram_dual_port_mixed_width[31].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[31].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_32" output="prim_ram_dual_port_mixed_width[32].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[32].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_33" output="prim_ram_dual_port_mixed_width[33].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[33].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_34" output="prim_ram_dual_port_mixed_width[34].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[34].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_35" output="prim_ram_dual_port_mixed_width[35].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_dual_port_mixed_width[35].portbaddr[13:0]"/>
              </direct>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_reg-out_mixed_width">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{reg}" name="prim_ram_bidir_dual_port_mixed_width" num_pb="36">
              <input name="portadatain" num_pins="36"/>
              <input name="portare" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="14"/>
              <input name="portbaddr" num_pins="14"/>
              <input name="portbre" num_pins="1"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1"/>
              <input name="portbdatain" num_pins="36"/>
              <output name="portadataout" num_pins="36"/>
              <output name="portbdataout" num_pins="36"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1"/>
              <clock name="clk_portbin" num_pins="1"/>
              <clock name="clk_portain" num_pins="1"/>
              <clock name="clk_portaout" num_pins="1"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portare" value="1.4e-11"/>
              <T_setup clock="clk_portaout" port="prim_ram_bidir_dual_port_mixed_width.portadataout" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_bidir_dual_port_mixed_width.portbdataout" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbout" port="prim_ram_bidir_dual_port_mixed_width.eccstatus" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portare"/>
              <T_clock_to_Q clock="clk_portaout" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portbwe"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portbout" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portbdatain"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portare" value="0.0"/>
              <T_hold clock="clk_portaout" port="prim_ram_bidir_dual_port_mixed_width.portadataout" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbwe" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_bidir_dual_port_mixed_width.portbdataout" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbout" port="prim_ram_bidir_dual_port_mixed_width.eccstatus" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_bidir_dual_port_mixed_width[35:0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_bidir_dual_port_mixed_width[35:0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_bidir_dual_port_mixed_width[35:0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_bidir_dual_port_mixed_width[35:0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_bidir_dual_port_mixed_width[35:0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_bidir_dual_port_mixed_width[35:0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_bidir_dual_port_mixed_width[35:0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_bidir_dual_port_mixed_width[35:0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_bidir_dual_port_mixed_width[35:0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_bidir_dual_port_mixed_width[35:0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_bidir_dual_port_mixed_width[35:0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_bidir_dual_port_mixed_width[35:0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.data_b_in" name="interconnect_full_ram_block_M144K_data_b_in_0" output="prim_ram_bidir_dual_port_mixed_width[35:0].portbdatain[35:0] ">
                <delay_constant in_port="ram_block_M144K.data_b_in" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].portbdatain[35:0] "/>
              </complete>
              <complete input="ram_block_M144K.data_a_in" name="interconnect_full_ram_block_M144K_data_a_in_0" output="prim_ram_bidir_dual_port_mixed_width[35:0].portadatain[35:0] ">
                <delay_constant in_port="ram_block_M144K.data_a_in" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].portadatain[35:0] "/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_bidir_dual_port_mixed_width[35:0].clk_portbout[0] prim_ram_bidir_dual_port_mixed_width[35:0].clk_portbin[0] prim_ram_bidir_dual_port_mixed_width[35:0].clk_portain[0] prim_ram_bidir_dual_port_mixed_width[35:0].clk_portaout[0] "/>
              <complete input="prim_ram_bidir_dual_port_mixed_width[35:0].eccstatus[2:0] " name="interconnect_full_ram_block_M144K_control_out_0" output="ram_block_M144K.control_out"/>
              <complete input="prim_ram_bidir_dual_port_mixed_width[35:0].portadataout[35:0] prim_ram_bidir_dual_port_mixed_width[35:0].portbdataout[35:0] " name="interconnect_full_ram_block_M144K_data_out_0" output="ram_block_M144K.data_out"/>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_0" output="prim_ram_bidir_dual_port_mixed_width[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[0].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_1" output="prim_ram_bidir_dual_port_mixed_width[1].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[1].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_2" output="prim_ram_bidir_dual_port_mixed_width[2].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[2].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_3" output="prim_ram_bidir_dual_port_mixed_width[3].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[3].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_4" output="prim_ram_bidir_dual_port_mixed_width[4].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[4].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_5" output="prim_ram_bidir_dual_port_mixed_width[5].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[5].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_6" output="prim_ram_bidir_dual_port_mixed_width[6].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[6].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_7" output="prim_ram_bidir_dual_port_mixed_width[7].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[7].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_8" output="prim_ram_bidir_dual_port_mixed_width[8].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[8].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_9" output="prim_ram_bidir_dual_port_mixed_width[9].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[9].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_10" output="prim_ram_bidir_dual_port_mixed_width[10].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[10].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_11" output="prim_ram_bidir_dual_port_mixed_width[11].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[11].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_12" output="prim_ram_bidir_dual_port_mixed_width[12].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[12].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_13" output="prim_ram_bidir_dual_port_mixed_width[13].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[13].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_14" output="prim_ram_bidir_dual_port_mixed_width[14].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[14].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_15" output="prim_ram_bidir_dual_port_mixed_width[15].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[15].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_16" output="prim_ram_bidir_dual_port_mixed_width[16].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[16].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_17" output="prim_ram_bidir_dual_port_mixed_width[17].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_18" output="prim_ram_bidir_dual_port_mixed_width[18].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[18].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_19" output="prim_ram_bidir_dual_port_mixed_width[19].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[19].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_20" output="prim_ram_bidir_dual_port_mixed_width[20].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[20].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_21" output="prim_ram_bidir_dual_port_mixed_width[21].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[21].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_22" output="prim_ram_bidir_dual_port_mixed_width[22].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[22].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_23" output="prim_ram_bidir_dual_port_mixed_width[23].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[23].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_24" output="prim_ram_bidir_dual_port_mixed_width[24].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[24].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_25" output="prim_ram_bidir_dual_port_mixed_width[25].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[25].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_26" output="prim_ram_bidir_dual_port_mixed_width[26].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[26].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_27" output="prim_ram_bidir_dual_port_mixed_width[27].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[27].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_28" output="prim_ram_bidir_dual_port_mixed_width[28].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[28].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_29" output="prim_ram_bidir_dual_port_mixed_width[29].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[29].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_30" output="prim_ram_bidir_dual_port_mixed_width[30].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[30].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_31" output="prim_ram_bidir_dual_port_mixed_width[31].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[31].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_32" output="prim_ram_bidir_dual_port_mixed_width[32].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[32].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_33" output="prim_ram_bidir_dual_port_mixed_width[33].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[33].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_34" output="prim_ram_bidir_dual_port_mixed_width[34].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[34].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_35" output="prim_ram_bidir_dual_port_mixed_width[35].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_0" output="prim_ram_bidir_dual_port_mixed_width[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[0].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_1" output="prim_ram_bidir_dual_port_mixed_width[1].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[1].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_2" output="prim_ram_bidir_dual_port_mixed_width[2].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[2].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_3" output="prim_ram_bidir_dual_port_mixed_width[3].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[3].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_4" output="prim_ram_bidir_dual_port_mixed_width[4].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[4].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_5" output="prim_ram_bidir_dual_port_mixed_width[5].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[5].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_6" output="prim_ram_bidir_dual_port_mixed_width[6].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[6].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_7" output="prim_ram_bidir_dual_port_mixed_width[7].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[7].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_8" output="prim_ram_bidir_dual_port_mixed_width[8].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[8].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_9" output="prim_ram_bidir_dual_port_mixed_width[9].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[9].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_10" output="prim_ram_bidir_dual_port_mixed_width[10].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[10].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_11" output="prim_ram_bidir_dual_port_mixed_width[11].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[11].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_12" output="prim_ram_bidir_dual_port_mixed_width[12].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[12].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_13" output="prim_ram_bidir_dual_port_mixed_width[13].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[13].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_14" output="prim_ram_bidir_dual_port_mixed_width[14].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[14].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_15" output="prim_ram_bidir_dual_port_mixed_width[15].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[15].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_16" output="prim_ram_bidir_dual_port_mixed_width[16].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[16].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_17" output="prim_ram_bidir_dual_port_mixed_width[17].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_18" output="prim_ram_bidir_dual_port_mixed_width[18].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[18].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_19" output="prim_ram_bidir_dual_port_mixed_width[19].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[19].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_20" output="prim_ram_bidir_dual_port_mixed_width[20].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[20].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_21" output="prim_ram_bidir_dual_port_mixed_width[21].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[21].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_22" output="prim_ram_bidir_dual_port_mixed_width[22].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[22].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_23" output="prim_ram_bidir_dual_port_mixed_width[23].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[23].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_24" output="prim_ram_bidir_dual_port_mixed_width[24].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[24].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_25" output="prim_ram_bidir_dual_port_mixed_width[25].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[25].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_26" output="prim_ram_bidir_dual_port_mixed_width[26].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[26].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_27" output="prim_ram_bidir_dual_port_mixed_width[27].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[27].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_28" output="prim_ram_bidir_dual_port_mixed_width[28].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[28].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_29" output="prim_ram_bidir_dual_port_mixed_width[29].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[29].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_30" output="prim_ram_bidir_dual_port_mixed_width[30].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[30].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_31" output="prim_ram_bidir_dual_port_mixed_width[31].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[31].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_32" output="prim_ram_bidir_dual_port_mixed_width[32].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[32].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_33" output="prim_ram_bidir_dual_port_mixed_width[33].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[33].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_34" output="prim_ram_bidir_dual_port_mixed_width[34].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[34].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_35" output="prim_ram_bidir_dual_port_mixed_width[35].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_0" output="prim_ram_bidir_dual_port_mixed_width[0].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[0].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_1" output="prim_ram_bidir_dual_port_mixed_width[1].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[1].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_2" output="prim_ram_bidir_dual_port_mixed_width[2].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[2].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_3" output="prim_ram_bidir_dual_port_mixed_width[3].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[3].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_4" output="prim_ram_bidir_dual_port_mixed_width[4].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[4].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_5" output="prim_ram_bidir_dual_port_mixed_width[5].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[5].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_6" output="prim_ram_bidir_dual_port_mixed_width[6].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[6].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_7" output="prim_ram_bidir_dual_port_mixed_width[7].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[7].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_8" output="prim_ram_bidir_dual_port_mixed_width[8].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[8].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_9" output="prim_ram_bidir_dual_port_mixed_width[9].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[9].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_10" output="prim_ram_bidir_dual_port_mixed_width[10].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[10].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_11" output="prim_ram_bidir_dual_port_mixed_width[11].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[11].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_12" output="prim_ram_bidir_dual_port_mixed_width[12].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[12].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_13" output="prim_ram_bidir_dual_port_mixed_width[13].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[13].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_14" output="prim_ram_bidir_dual_port_mixed_width[14].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[14].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_15" output="prim_ram_bidir_dual_port_mixed_width[15].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[15].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_16" output="prim_ram_bidir_dual_port_mixed_width[16].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[16].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_17" output="prim_ram_bidir_dual_port_mixed_width[17].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_18" output="prim_ram_bidir_dual_port_mixed_width[18].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[18].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_19" output="prim_ram_bidir_dual_port_mixed_width[19].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[19].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_20" output="prim_ram_bidir_dual_port_mixed_width[20].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[20].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_21" output="prim_ram_bidir_dual_port_mixed_width[21].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[21].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_22" output="prim_ram_bidir_dual_port_mixed_width[22].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[22].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_23" output="prim_ram_bidir_dual_port_mixed_width[23].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[23].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_24" output="prim_ram_bidir_dual_port_mixed_width[24].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[24].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_25" output="prim_ram_bidir_dual_port_mixed_width[25].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[25].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_26" output="prim_ram_bidir_dual_port_mixed_width[26].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[26].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_27" output="prim_ram_bidir_dual_port_mixed_width[27].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[27].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_28" output="prim_ram_bidir_dual_port_mixed_width[28].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[28].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_29" output="prim_ram_bidir_dual_port_mixed_width[29].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[29].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_30" output="prim_ram_bidir_dual_port_mixed_width[30].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[30].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_31" output="prim_ram_bidir_dual_port_mixed_width[31].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[31].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_32" output="prim_ram_bidir_dual_port_mixed_width[32].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[32].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_33" output="prim_ram_bidir_dual_port_mixed_width[33].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[33].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_34" output="prim_ram_bidir_dual_port_mixed_width[34].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[34].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_35" output="prim_ram_bidir_dual_port_mixed_width[35].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_0" output="prim_ram_bidir_dual_port_mixed_width[0].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[0].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_1" output="prim_ram_bidir_dual_port_mixed_width[1].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[1].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_2" output="prim_ram_bidir_dual_port_mixed_width[2].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[2].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_3" output="prim_ram_bidir_dual_port_mixed_width[3].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[3].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_4" output="prim_ram_bidir_dual_port_mixed_width[4].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[4].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_5" output="prim_ram_bidir_dual_port_mixed_width[5].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[5].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_6" output="prim_ram_bidir_dual_port_mixed_width[6].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[6].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_7" output="prim_ram_bidir_dual_port_mixed_width[7].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[7].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_8" output="prim_ram_bidir_dual_port_mixed_width[8].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[8].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_9" output="prim_ram_bidir_dual_port_mixed_width[9].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[9].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_10" output="prim_ram_bidir_dual_port_mixed_width[10].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[10].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_11" output="prim_ram_bidir_dual_port_mixed_width[11].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[11].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_12" output="prim_ram_bidir_dual_port_mixed_width[12].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[12].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_13" output="prim_ram_bidir_dual_port_mixed_width[13].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[13].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_14" output="prim_ram_bidir_dual_port_mixed_width[14].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[14].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_15" output="prim_ram_bidir_dual_port_mixed_width[15].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[15].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_16" output="prim_ram_bidir_dual_port_mixed_width[16].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[16].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_17" output="prim_ram_bidir_dual_port_mixed_width[17].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_18" output="prim_ram_bidir_dual_port_mixed_width[18].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[18].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_19" output="prim_ram_bidir_dual_port_mixed_width[19].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[19].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_20" output="prim_ram_bidir_dual_port_mixed_width[20].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[20].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_21" output="prim_ram_bidir_dual_port_mixed_width[21].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[21].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_22" output="prim_ram_bidir_dual_port_mixed_width[22].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[22].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_23" output="prim_ram_bidir_dual_port_mixed_width[23].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[23].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_24" output="prim_ram_bidir_dual_port_mixed_width[24].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[24].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_25" output="prim_ram_bidir_dual_port_mixed_width[25].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[25].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_26" output="prim_ram_bidir_dual_port_mixed_width[26].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[26].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_27" output="prim_ram_bidir_dual_port_mixed_width[27].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[27].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_28" output="prim_ram_bidir_dual_port_mixed_width[28].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[28].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_29" output="prim_ram_bidir_dual_port_mixed_width[29].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[29].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_30" output="prim_ram_bidir_dual_port_mixed_width[30].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[30].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_31" output="prim_ram_bidir_dual_port_mixed_width[31].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[31].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_32" output="prim_ram_bidir_dual_port_mixed_width[32].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[32].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_33" output="prim_ram_bidir_dual_port_mixed_width[33].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[33].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_34" output="prim_ram_bidir_dual_port_mixed_width[34].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[34].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_35" output="prim_ram_bidir_dual_port_mixed_width[35].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35].portbaddr[13:0]"/>
              </direct>
            </interconnect>
          </mode>
          <mode name="bidir_dual_port_combout_mixed_width">
            <pb_type blif_model=".subckt stratixiv_ram_block.opmode{bidir_dual_port}.output_type{comb}" name="prim_ram_bidir_dual_port_mixed_width" num_pb="36">
              <input name="portadatain" num_pins="36"/>
              <input name="portare" num_pins="1"/>
              <input name="clr0" num_pins="1"/>
              <input name="portaaddrstall" num_pins="1"/>
              <input name="portaaddr" num_pins="14"/>
              <input name="portbaddr" num_pins="14"/>
              <input name="portbre" num_pins="1"/>
              <input name="clr1" num_pins="1"/>
              <input name="portbbyteenamasks" num_pins="8"/>
              <input name="portbwe" num_pins="1"/>
              <input name="ena2" num_pins="1"/>
              <input name="ena3" num_pins="1"/>
              <input name="ena0" num_pins="1"/>
              <input name="ena1" num_pins="1"/>
              <input name="portbaddrstall" num_pins="1"/>
              <input name="portabyteenamasks" num_pins="8"/>
              <input name="portawe" num_pins="1"/>
              <input name="portbdatain" num_pins="36"/>
              <output name="portadataout" num_pins="36"/>
              <output name="portbdataout" num_pins="36"/>
              <output name="eccstatus" num_pins="3"/>
              <clock name="clk_portbout" num_pins="1"/>
              <clock name="clk_portbin" num_pins="1"/>
              <clock name="clk_portain" num_pins="1"/>
              <clock name="clk_portaout" num_pins="1"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portadatain" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portare" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.clr0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portaaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portaaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbaddr" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbre" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.clr1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbbyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbwe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.ena2" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.ena3" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.ena0" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.ena1" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbaddrstall" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portabyteenamasks" value="1.4e-11"/>
              <T_setup clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portawe" value="1.4e-11"/>
              <T_setup clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbdatain" value="1.4e-11"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portadatain"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portare"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.clr0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portaaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portaaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portbaddr"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portbre"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.clr1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portbbyteenamasks"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portbwe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.ena2"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.ena3"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.ena0"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.ena1"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portbaddrstall"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portabyteenamasks"/>
              <T_clock_to_Q clock="clk_portain" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portawe"/>
              <T_clock_to_Q clock="clk_portbin" max="2.31e-10" min="8.5e-11" port="prim_ram_bidir_dual_port_mixed_width.portbdatain"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portadatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portare" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.clr0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portaaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portaaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbaddr" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbre" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.clr1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbbyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbwe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena2" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena3" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena0" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.ena1" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbaddrstall" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portabyteenamasks" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portawe" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.eccstatus"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portadataout"/>
              <delay_constant in_port="prim_ram_bidir_dual_port_mixed_width.portbdatain" max="1.967e-09" min="1.814e-09" out_port="prim_ram_bidir_dual_port_mixed_width.portbdataout"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portadatain" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portare" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.clr0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portaaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portaaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbaddr" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbre" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.clr1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbbyteenamasks" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbwe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.ena2" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.ena3" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.ena0" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.ena1" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbaddrstall" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portabyteenamasks" value="0.0"/>
              <T_hold clock="clk_portain" port="prim_ram_bidir_dual_port_mixed_width.portawe" value="0.0"/>
              <T_hold clock="clk_portbin" port="prim_ram_bidir_dual_port_mixed_width.portbdatain" value="0.0"/>
            </pb_type>
            <interconnect>
              <complete input="ram_block_M144K.control_in[0]" name="interconnect_common_ram_block_M144K_control_in_[0]" output="prim_ram_bidir_dual_port_mixed_width[35:0].portare[0]">
                <delay_constant in_port="ram_block_M144K.control_in[0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].portare[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[1]" name="interconnect_common_ram_block_M144K_control_in_[1]" output="prim_ram_bidir_dual_port_mixed_width[35:0].clr0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[1]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].clr0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[2]" name="interconnect_common_ram_block_M144K_control_in_[2]" output="prim_ram_bidir_dual_port_mixed_width[35:0].portaaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[2]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].portaaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[3]" name="interconnect_common_ram_block_M144K_control_in_[3]" output="prim_ram_bidir_dual_port_mixed_width[35:0].portbre[0]">
                <delay_constant in_port="ram_block_M144K.control_in[3]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].portbre[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[4]" name="interconnect_common_ram_block_M144K_control_in_[4]" output="prim_ram_bidir_dual_port_mixed_width[35:0].clr1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[4]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].clr1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[13]" name="interconnect_common_ram_block_M144K_control_in_[13]" output="prim_ram_bidir_dual_port_mixed_width[35:0].portbwe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[13]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].portbwe[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[14]" name="interconnect_common_ram_block_M144K_control_in_[14]" output="prim_ram_bidir_dual_port_mixed_width[35:0].ena2[0]">
                <delay_constant in_port="ram_block_M144K.control_in[14]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].ena2[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[15]" name="interconnect_common_ram_block_M144K_control_in_[15]" output="prim_ram_bidir_dual_port_mixed_width[35:0].ena3[0]">
                <delay_constant in_port="ram_block_M144K.control_in[15]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].ena3[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[16]" name="interconnect_common_ram_block_M144K_control_in_[16]" output="prim_ram_bidir_dual_port_mixed_width[35:0].ena0[0]">
                <delay_constant in_port="ram_block_M144K.control_in[16]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].ena0[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[17]" name="interconnect_common_ram_block_M144K_control_in_[17]" output="prim_ram_bidir_dual_port_mixed_width[35:0].ena1[0]">
                <delay_constant in_port="ram_block_M144K.control_in[17]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].ena1[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[18]" name="interconnect_common_ram_block_M144K_control_in_[18]" output="prim_ram_bidir_dual_port_mixed_width[35:0].portbaddrstall[0]">
                <delay_constant in_port="ram_block_M144K.control_in[18]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].portbaddrstall[0]"/>
              </complete>
              <complete input="ram_block_M144K.control_in[27]" name="interconnect_common_ram_block_M144K_control_in_[27]" output="prim_ram_bidir_dual_port_mixed_width[35:0].portawe[0]">
                <delay_constant in_port="ram_block_M144K.control_in[27]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].portawe[0]"/>
              </complete>
              <complete input="ram_block_M144K.data_b_in" name="interconnect_full_ram_block_M144K_data_b_in_0" output="prim_ram_bidir_dual_port_mixed_width[35:0].portbdatain[35:0] ">
                <delay_constant in_port="ram_block_M144K.data_b_in" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].portbdatain[35:0] "/>
              </complete>
              <complete input="ram_block_M144K.data_a_in" name="interconnect_full_ram_block_M144K_data_a_in_0" output="prim_ram_bidir_dual_port_mixed_width[35:0].portadatain[35:0] ">
                <delay_constant in_port="ram_block_M144K.data_a_in" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35:0].portadatain[35:0] "/>
              </complete>
              <complete input="ram_block_M144K.clk_in[1:0]" name="interconnect_full_ram_block_M144K_clk_in_1" output="prim_ram_bidir_dual_port_mixed_width[35:0].clk_portbout[0] prim_ram_bidir_dual_port_mixed_width[35:0].clk_portbin[0] prim_ram_bidir_dual_port_mixed_width[35:0].clk_portain[0] prim_ram_bidir_dual_port_mixed_width[35:0].clk_portaout[0] "/>
              <complete input="prim_ram_bidir_dual_port_mixed_width[35:0].eccstatus[2:0] " name="interconnect_full_ram_block_M144K_control_out_0" output="ram_block_M144K.control_out"/>
              <complete input="prim_ram_bidir_dual_port_mixed_width[35:0].portadataout[35:0] prim_ram_bidir_dual_port_mixed_width[35:0].portbdataout[35:0] " name="interconnect_full_ram_block_M144K_data_out_0" output="ram_block_M144K.data_out"/>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_0" output="prim_ram_bidir_dual_port_mixed_width[0].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[0].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_1" output="prim_ram_bidir_dual_port_mixed_width[1].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[1].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_2" output="prim_ram_bidir_dual_port_mixed_width[2].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[2].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_3" output="prim_ram_bidir_dual_port_mixed_width[3].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[3].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_4" output="prim_ram_bidir_dual_port_mixed_width[4].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[4].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_5" output="prim_ram_bidir_dual_port_mixed_width[5].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[5].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_6" output="prim_ram_bidir_dual_port_mixed_width[6].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[6].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_7" output="prim_ram_bidir_dual_port_mixed_width[7].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[7].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_8" output="prim_ram_bidir_dual_port_mixed_width[8].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[8].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_9" output="prim_ram_bidir_dual_port_mixed_width[9].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[9].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_10" output="prim_ram_bidir_dual_port_mixed_width[10].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[10].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_11" output="prim_ram_bidir_dual_port_mixed_width[11].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[11].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_12" output="prim_ram_bidir_dual_port_mixed_width[12].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[12].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_13" output="prim_ram_bidir_dual_port_mixed_width[13].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[13].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_14" output="prim_ram_bidir_dual_port_mixed_width[14].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[14].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_15" output="prim_ram_bidir_dual_port_mixed_width[15].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[15].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_16" output="prim_ram_bidir_dual_port_mixed_width[16].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[16].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_17" output="prim_ram_bidir_dual_port_mixed_width[17].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_18" output="prim_ram_bidir_dual_port_mixed_width[18].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[18].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_19" output="prim_ram_bidir_dual_port_mixed_width[19].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[19].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_20" output="prim_ram_bidir_dual_port_mixed_width[20].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[20].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_21" output="prim_ram_bidir_dual_port_mixed_width[21].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[21].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_22" output="prim_ram_bidir_dual_port_mixed_width[22].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[22].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_23" output="prim_ram_bidir_dual_port_mixed_width[23].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[23].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_24" output="prim_ram_bidir_dual_port_mixed_width[24].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[24].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_25" output="prim_ram_bidir_dual_port_mixed_width[25].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[25].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_26" output="prim_ram_bidir_dual_port_mixed_width[26].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[26].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_27" output="prim_ram_bidir_dual_port_mixed_width[27].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[27].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_28" output="prim_ram_bidir_dual_port_mixed_width[28].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[28].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_29" output="prim_ram_bidir_dual_port_mixed_width[29].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[29].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_30" output="prim_ram_bidir_dual_port_mixed_width[30].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[30].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_31" output="prim_ram_bidir_dual_port_mixed_width[31].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[31].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_32" output="prim_ram_bidir_dual_port_mixed_width[32].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[32].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_33" output="prim_ram_bidir_dual_port_mixed_width[33].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[33].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_34" output="prim_ram_bidir_dual_port_mixed_width[34].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[34].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[12:5]" name="interconnect_common_ram_block_M144K_control_in_[12:5]_35" output="prim_ram_bidir_dual_port_mixed_width[35].portbbyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[12:5]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35].portbbyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_0" output="prim_ram_bidir_dual_port_mixed_width[0].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[0].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_1" output="prim_ram_bidir_dual_port_mixed_width[1].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[1].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_2" output="prim_ram_bidir_dual_port_mixed_width[2].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[2].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_3" output="prim_ram_bidir_dual_port_mixed_width[3].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[3].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_4" output="prim_ram_bidir_dual_port_mixed_width[4].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[4].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_5" output="prim_ram_bidir_dual_port_mixed_width[5].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[5].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_6" output="prim_ram_bidir_dual_port_mixed_width[6].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[6].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_7" output="prim_ram_bidir_dual_port_mixed_width[7].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[7].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_8" output="prim_ram_bidir_dual_port_mixed_width[8].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[8].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_9" output="prim_ram_bidir_dual_port_mixed_width[9].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[9].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_10" output="prim_ram_bidir_dual_port_mixed_width[10].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[10].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_11" output="prim_ram_bidir_dual_port_mixed_width[11].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[11].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_12" output="prim_ram_bidir_dual_port_mixed_width[12].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[12].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_13" output="prim_ram_bidir_dual_port_mixed_width[13].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[13].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_14" output="prim_ram_bidir_dual_port_mixed_width[14].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[14].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_15" output="prim_ram_bidir_dual_port_mixed_width[15].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[15].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_16" output="prim_ram_bidir_dual_port_mixed_width[16].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[16].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_17" output="prim_ram_bidir_dual_port_mixed_width[17].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_18" output="prim_ram_bidir_dual_port_mixed_width[18].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[18].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_19" output="prim_ram_bidir_dual_port_mixed_width[19].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[19].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_20" output="prim_ram_bidir_dual_port_mixed_width[20].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[20].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_21" output="prim_ram_bidir_dual_port_mixed_width[21].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[21].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_22" output="prim_ram_bidir_dual_port_mixed_width[22].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[22].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_23" output="prim_ram_bidir_dual_port_mixed_width[23].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[23].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_24" output="prim_ram_bidir_dual_port_mixed_width[24].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[24].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_25" output="prim_ram_bidir_dual_port_mixed_width[25].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[25].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_26" output="prim_ram_bidir_dual_port_mixed_width[26].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[26].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_27" output="prim_ram_bidir_dual_port_mixed_width[27].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[27].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_28" output="prim_ram_bidir_dual_port_mixed_width[28].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[28].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_29" output="prim_ram_bidir_dual_port_mixed_width[29].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[29].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_30" output="prim_ram_bidir_dual_port_mixed_width[30].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[30].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_31" output="prim_ram_bidir_dual_port_mixed_width[31].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[31].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_32" output="prim_ram_bidir_dual_port_mixed_width[32].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[32].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_33" output="prim_ram_bidir_dual_port_mixed_width[33].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[33].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_34" output="prim_ram_bidir_dual_port_mixed_width[34].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[34].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.control_in[26:19]" name="interconnect_common_ram_block_M144K_control_in_[26:19]_35" output="prim_ram_bidir_dual_port_mixed_width[35].portabyteenamasks[7:0]">
                <delay_constant in_port="ram_block_M144K.control_in[26:19]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35].portabyteenamasks[7:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_0" output="prim_ram_bidir_dual_port_mixed_width[0].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[0].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_1" output="prim_ram_bidir_dual_port_mixed_width[1].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[1].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_2" output="prim_ram_bidir_dual_port_mixed_width[2].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[2].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_3" output="prim_ram_bidir_dual_port_mixed_width[3].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[3].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_4" output="prim_ram_bidir_dual_port_mixed_width[4].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[4].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_5" output="prim_ram_bidir_dual_port_mixed_width[5].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[5].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_6" output="prim_ram_bidir_dual_port_mixed_width[6].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[6].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_7" output="prim_ram_bidir_dual_port_mixed_width[7].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[7].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_8" output="prim_ram_bidir_dual_port_mixed_width[8].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[8].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_9" output="prim_ram_bidir_dual_port_mixed_width[9].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[9].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_10" output="prim_ram_bidir_dual_port_mixed_width[10].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[10].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_11" output="prim_ram_bidir_dual_port_mixed_width[11].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[11].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_12" output="prim_ram_bidir_dual_port_mixed_width[12].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[12].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_13" output="prim_ram_bidir_dual_port_mixed_width[13].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[13].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_14" output="prim_ram_bidir_dual_port_mixed_width[14].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[14].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_15" output="prim_ram_bidir_dual_port_mixed_width[15].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[15].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_16" output="prim_ram_bidir_dual_port_mixed_width[16].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[16].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_17" output="prim_ram_bidir_dual_port_mixed_width[17].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_18" output="prim_ram_bidir_dual_port_mixed_width[18].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[18].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_19" output="prim_ram_bidir_dual_port_mixed_width[19].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[19].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_20" output="prim_ram_bidir_dual_port_mixed_width[20].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[20].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_21" output="prim_ram_bidir_dual_port_mixed_width[21].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[21].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_22" output="prim_ram_bidir_dual_port_mixed_width[22].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[22].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_23" output="prim_ram_bidir_dual_port_mixed_width[23].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[23].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_24" output="prim_ram_bidir_dual_port_mixed_width[24].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[24].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_25" output="prim_ram_bidir_dual_port_mixed_width[25].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[25].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_26" output="prim_ram_bidir_dual_port_mixed_width[26].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[26].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_27" output="prim_ram_bidir_dual_port_mixed_width[27].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[27].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_28" output="prim_ram_bidir_dual_port_mixed_width[28].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[28].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_29" output="prim_ram_bidir_dual_port_mixed_width[29].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[29].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_30" output="prim_ram_bidir_dual_port_mixed_width[30].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[30].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_31" output="prim_ram_bidir_dual_port_mixed_width[31].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[31].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_32" output="prim_ram_bidir_dual_port_mixed_width[32].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[32].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_33" output="prim_ram_bidir_dual_port_mixed_width[33].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[33].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_34" output="prim_ram_bidir_dual_port_mixed_width[34].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[34].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_a_in[13:0]" name="interconnect_common_ram_block_M144K_addr_a_in_[13:0]_35" output="prim_ram_bidir_dual_port_mixed_width[35].portaaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_a_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35].portaaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_0" output="prim_ram_bidir_dual_port_mixed_width[0].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[0].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_1" output="prim_ram_bidir_dual_port_mixed_width[1].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[1].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_2" output="prim_ram_bidir_dual_port_mixed_width[2].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[2].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_3" output="prim_ram_bidir_dual_port_mixed_width[3].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[3].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_4" output="prim_ram_bidir_dual_port_mixed_width[4].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[4].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_5" output="prim_ram_bidir_dual_port_mixed_width[5].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[5].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_6" output="prim_ram_bidir_dual_port_mixed_width[6].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[6].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_7" output="prim_ram_bidir_dual_port_mixed_width[7].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[7].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_8" output="prim_ram_bidir_dual_port_mixed_width[8].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[8].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_9" output="prim_ram_bidir_dual_port_mixed_width[9].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[9].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_10" output="prim_ram_bidir_dual_port_mixed_width[10].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[10].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_11" output="prim_ram_bidir_dual_port_mixed_width[11].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[11].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_12" output="prim_ram_bidir_dual_port_mixed_width[12].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[12].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_13" output="prim_ram_bidir_dual_port_mixed_width[13].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[13].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_14" output="prim_ram_bidir_dual_port_mixed_width[14].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[14].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_15" output="prim_ram_bidir_dual_port_mixed_width[15].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[15].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_16" output="prim_ram_bidir_dual_port_mixed_width[16].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[16].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_17" output="prim_ram_bidir_dual_port_mixed_width[17].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[17].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_18" output="prim_ram_bidir_dual_port_mixed_width[18].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[18].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_19" output="prim_ram_bidir_dual_port_mixed_width[19].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[19].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_20" output="prim_ram_bidir_dual_port_mixed_width[20].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[20].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_21" output="prim_ram_bidir_dual_port_mixed_width[21].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[21].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_22" output="prim_ram_bidir_dual_port_mixed_width[22].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[22].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_23" output="prim_ram_bidir_dual_port_mixed_width[23].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[23].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_24" output="prim_ram_bidir_dual_port_mixed_width[24].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[24].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_25" output="prim_ram_bidir_dual_port_mixed_width[25].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[25].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_26" output="prim_ram_bidir_dual_port_mixed_width[26].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[26].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_27" output="prim_ram_bidir_dual_port_mixed_width[27].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[27].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_28" output="prim_ram_bidir_dual_port_mixed_width[28].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[28].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_29" output="prim_ram_bidir_dual_port_mixed_width[29].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[29].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_30" output="prim_ram_bidir_dual_port_mixed_width[30].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[30].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_31" output="prim_ram_bidir_dual_port_mixed_width[31].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[31].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_32" output="prim_ram_bidir_dual_port_mixed_width[32].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[32].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_33" output="prim_ram_bidir_dual_port_mixed_width[33].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[33].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_34" output="prim_ram_bidir_dual_port_mixed_width[34].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[34].portbaddr[13:0]"/>
              </direct>
              <direct input="ram_block_M144K.addr_b_in[13:0]" name="interconnect_common_ram_block_M144K_addr_b_in_[13:0]_35" output="prim_ram_bidir_dual_port_mixed_width[35].portbaddr[13:0]">
                <delay_constant in_port="ram_block_M144K.addr_b_in[13:0]" max="6.46e-10" min="1.25e-10" out_port="prim_ram_bidir_dual_port_mixed_width[35].portbaddr[13:0]"/>
              </direct>
            </interconnect>
          </mode>
        </pb_type>
        <interconnect>
          <complete input="ram_block_M144K[0].data_out[71:0] " name="interconnect_full_M144K_data_out_1" output="M144K.data_out[119:0]">
            <delay_constant in_port="ram_block_M144K[0].data_out[71:0] " max="5.9e-11" min="4.4e-11" out_port="M144K.data_out[119:0]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[377:360] M144K.data_addr_control_in[179:162]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit0" output="ram_block_M144K[0].control_in[0]">
            <delay_constant in_port="M144K.data_addr_control_in[377:360] M144K.data_addr_control_in[179:162]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[0]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[35:18] M144K.data_addr_control_in[125:108]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit1" output="ram_block_M144K[0].control_in[1]">
            <delay_constant in_port="M144K.data_addr_control_in[35:18] M144K.data_addr_control_in[125:108]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[1]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[197:180] M144K.data_addr_control_in[359:342]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit2" output="ram_block_M144K[0].control_in[2]">
            <delay_constant in_port="M144K.data_addr_control_in[197:180] M144K.data_addr_control_in[359:342]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[2]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[377:360] M144K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit3" output="ram_block_M144K[0].control_in[3]">
            <delay_constant in_port="M144K.data_addr_control_in[377:360] M144K.data_addr_control_in[71:54]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[3]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[233:216] M144K.data_addr_control_in[287:270]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit4" output="ram_block_M144K[0].control_in[4]">
            <delay_constant in_port="M144K.data_addr_control_in[233:216] M144K.data_addr_control_in[287:270]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[4]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[161:144] M144K.data_addr_control_in[377:360]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit5" output="ram_block_M144K[0].control_in[5]">
            <delay_constant in_port="M144K.data_addr_control_in[161:144] M144K.data_addr_control_in[377:360]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[5]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[125:108] M144K.data_addr_control_in[17:0]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit6" output="ram_block_M144K[0].control_in[6]">
            <delay_constant in_port="M144K.data_addr_control_in[125:108] M144K.data_addr_control_in[17:0]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[6]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[17:0] M144K.data_addr_control_in[305:288]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit7" output="ram_block_M144K[0].control_in[7]">
            <delay_constant in_port="M144K.data_addr_control_in[17:0] M144K.data_addr_control_in[305:288]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[7]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[251:234] M144K.data_addr_control_in[413:396]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit8" output="ram_block_M144K[0].control_in[8]">
            <delay_constant in_port="M144K.data_addr_control_in[251:234] M144K.data_addr_control_in[413:396]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[8]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[413:396] M144K.data_addr_control_in[395:378]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit9" output="ram_block_M144K[0].control_in[9]">
            <delay_constant in_port="M144K.data_addr_control_in[413:396] M144K.data_addr_control_in[395:378]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[9]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[35:18] M144K.data_addr_control_in[323:306]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit10" output="ram_block_M144K[0].control_in[10]">
            <delay_constant in_port="M144K.data_addr_control_in[35:18] M144K.data_addr_control_in[323:306]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[10]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[305:288] M144K.data_addr_control_in[287:270]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit11" output="ram_block_M144K[0].control_in[11]">
            <delay_constant in_port="M144K.data_addr_control_in[305:288] M144K.data_addr_control_in[287:270]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[11]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[323:306] M144K.data_addr_control_in[395:378]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit12" output="ram_block_M144K[0].control_in[12]">
            <delay_constant in_port="M144K.data_addr_control_in[323:306] M144K.data_addr_control_in[395:378]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[12]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[287:270] M144K.data_addr_control_in[161:144]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit13" output="ram_block_M144K[0].control_in[13]">
            <delay_constant in_port="M144K.data_addr_control_in[287:270] M144K.data_addr_control_in[161:144]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[13]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[233:216] M144K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit14" output="ram_block_M144K[0].control_in[14]">
            <delay_constant in_port="M144K.data_addr_control_in[233:216] M144K.data_addr_control_in[89:72]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[14]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[269:252] M144K.data_addr_control_in[17:0]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit15" output="ram_block_M144K[0].control_in[15]">
            <delay_constant in_port="M144K.data_addr_control_in[269:252] M144K.data_addr_control_in[17:0]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[15]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[71:54] M144K.data_addr_control_in[161:144]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit16" output="ram_block_M144K[0].control_in[16]">
            <delay_constant in_port="M144K.data_addr_control_in[71:54] M144K.data_addr_control_in[161:144]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[16]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[341:324] M144K.data_addr_control_in[323:306]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit17" output="ram_block_M144K[0].control_in[17]">
            <delay_constant in_port="M144K.data_addr_control_in[341:324] M144K.data_addr_control_in[323:306]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[17]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[161:144] M144K.data_addr_control_in[269:252]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit18" output="ram_block_M144K[0].control_in[18]">
            <delay_constant in_port="M144K.data_addr_control_in[161:144] M144K.data_addr_control_in[269:252]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[18]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[17:0] M144K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit19" output="ram_block_M144K[0].control_in[19]">
            <delay_constant in_port="M144K.data_addr_control_in[17:0] M144K.data_addr_control_in[71:54]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[19]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[415:414] M144K.data_addr_control_in[125:108]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit20" output="ram_block_M144K[0].control_in[20]">
            <delay_constant in_port="M144K.data_addr_control_in[415:414] M144K.data_addr_control_in[125:108]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[20]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[179:162] M144K.data_addr_control_in[251:234]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit21" output="ram_block_M144K[0].control_in[21]">
            <delay_constant in_port="M144K.data_addr_control_in[179:162] M144K.data_addr_control_in[251:234]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[21]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[143:126] M144K.data_addr_control_in[215:198]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit22" output="ram_block_M144K[0].control_in[22]">
            <delay_constant in_port="M144K.data_addr_control_in[143:126] M144K.data_addr_control_in[215:198]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[22]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[107:90] M144K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit23" output="ram_block_M144K[0].control_in[23]">
            <delay_constant in_port="M144K.data_addr_control_in[107:90] M144K.data_addr_control_in[35:18]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[23]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[89:72] M144K.data_addr_control_in[233:216]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit24" output="ram_block_M144K[0].control_in[24]">
            <delay_constant in_port="M144K.data_addr_control_in[89:72] M144K.data_addr_control_in[233:216]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[24]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[35:18] M144K.data_addr_control_in[179:162]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit25" output="ram_block_M144K[0].control_in[25]">
            <delay_constant in_port="M144K.data_addr_control_in[35:18] M144K.data_addr_control_in[179:162]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[25]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[143:126] M144K.data_addr_control_in[179:162]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit26" output="ram_block_M144K[0].control_in[26]">
            <delay_constant in_port="M144K.data_addr_control_in[143:126] M144K.data_addr_control_in[179:162]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[26]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[53:36] M144K.data_addr_control_in[395:378]" name="interconnect_partial_xbar_M144K_data_addr_control_in_1_bit27" output="ram_block_M144K[0].control_in[27]">
            <delay_constant in_port="M144K.data_addr_control_in[53:36] M144K.data_addr_control_in[395:378]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].control_in[27]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[215:198] M144K.data_addr_control_in[377:360]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit0" output="ram_block_M144K[0].data_b_in[0]">
            <delay_constant in_port="M144K.data_addr_control_in[215:198] M144K.data_addr_control_in[377:360]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[0]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[415:414] M144K.data_addr_control_in[161:144]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit1" output="ram_block_M144K[0].data_b_in[1]">
            <delay_constant in_port="M144K.data_addr_control_in[415:414] M144K.data_addr_control_in[161:144]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[1]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[215:198] M144K.data_addr_control_in[305:288]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit2" output="ram_block_M144K[0].data_b_in[2]">
            <delay_constant in_port="M144K.data_addr_control_in[215:198] M144K.data_addr_control_in[305:288]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[2]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[197:180] M144K.data_addr_control_in[143:126]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit3" output="ram_block_M144K[0].data_b_in[3]">
            <delay_constant in_port="M144K.data_addr_control_in[197:180] M144K.data_addr_control_in[143:126]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[3]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[323:306] M144K.data_addr_control_in[395:378]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit4" output="ram_block_M144K[0].data_b_in[4]">
            <delay_constant in_port="M144K.data_addr_control_in[323:306] M144K.data_addr_control_in[395:378]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[4]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[413:396] M144K.data_addr_control_in[287:270]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit5" output="ram_block_M144K[0].data_b_in[5]">
            <delay_constant in_port="M144K.data_addr_control_in[413:396] M144K.data_addr_control_in[287:270]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[5]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[179:162] M144K.data_addr_control_in[415:414]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit6" output="ram_block_M144K[0].data_b_in[6]">
            <delay_constant in_port="M144K.data_addr_control_in[179:162] M144K.data_addr_control_in[415:414]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[6]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[287:270] M144K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit7" output="ram_block_M144K[0].data_b_in[7]">
            <delay_constant in_port="M144K.data_addr_control_in[287:270] M144K.data_addr_control_in[35:18]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[7]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[53:36] M144K.data_addr_control_in[323:306]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit8" output="ram_block_M144K[0].data_b_in[8]">
            <delay_constant in_port="M144K.data_addr_control_in[53:36] M144K.data_addr_control_in[323:306]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[8]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[35:18] M144K.data_addr_control_in[17:0]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit9" output="ram_block_M144K[0].data_b_in[9]">
            <delay_constant in_port="M144K.data_addr_control_in[35:18] M144K.data_addr_control_in[17:0]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[9]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[179:162] M144K.data_addr_control_in[233:216]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit10" output="ram_block_M144K[0].data_b_in[10]">
            <delay_constant in_port="M144K.data_addr_control_in[179:162] M144K.data_addr_control_in[233:216]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[10]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[197:180] M144K.data_addr_control_in[215:198]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit11" output="ram_block_M144K[0].data_b_in[11]">
            <delay_constant in_port="M144K.data_addr_control_in[197:180] M144K.data_addr_control_in[215:198]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[11]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[269:252] M144K.data_addr_control_in[305:288]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit12" output="ram_block_M144K[0].data_b_in[12]">
            <delay_constant in_port="M144K.data_addr_control_in[269:252] M144K.data_addr_control_in[305:288]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[12]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[197:180] M144K.data_addr_control_in[161:144]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit13" output="ram_block_M144K[0].data_b_in[13]">
            <delay_constant in_port="M144K.data_addr_control_in[197:180] M144K.data_addr_control_in[161:144]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[13]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[415:414] M144K.data_addr_control_in[125:108]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit14" output="ram_block_M144K[0].data_b_in[14]">
            <delay_constant in_port="M144K.data_addr_control_in[415:414] M144K.data_addr_control_in[125:108]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[14]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[341:324] M144K.data_addr_control_in[197:180]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit15" output="ram_block_M144K[0].data_b_in[15]">
            <delay_constant in_port="M144K.data_addr_control_in[341:324] M144K.data_addr_control_in[197:180]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[15]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[161:144] M144K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit16" output="ram_block_M144K[0].data_b_in[16]">
            <delay_constant in_port="M144K.data_addr_control_in[161:144] M144K.data_addr_control_in[35:18]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[16]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[377:360] M144K.data_addr_control_in[305:288]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit17" output="ram_block_M144K[0].data_b_in[17]">
            <delay_constant in_port="M144K.data_addr_control_in[377:360] M144K.data_addr_control_in[305:288]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[17]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[395:378] M144K.data_addr_control_in[197:180]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit18" output="ram_block_M144K[0].data_b_in[18]">
            <delay_constant in_port="M144K.data_addr_control_in[395:378] M144K.data_addr_control_in[197:180]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[18]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[305:288] M144K.data_addr_control_in[53:36]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit19" output="ram_block_M144K[0].data_b_in[19]">
            <delay_constant in_port="M144K.data_addr_control_in[305:288] M144K.data_addr_control_in[53:36]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[19]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[179:162] M144K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit20" output="ram_block_M144K[0].data_b_in[20]">
            <delay_constant in_port="M144K.data_addr_control_in[179:162] M144K.data_addr_control_in[89:72]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[20]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[35:18] M144K.data_addr_control_in[413:396]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit21" output="ram_block_M144K[0].data_b_in[21]">
            <delay_constant in_port="M144K.data_addr_control_in[35:18] M144K.data_addr_control_in[413:396]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[21]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[107:90] M144K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit22" output="ram_block_M144K[0].data_b_in[22]">
            <delay_constant in_port="M144K.data_addr_control_in[107:90] M144K.data_addr_control_in[71:54]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[22]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[89:72] M144K.data_addr_control_in[179:162]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit23" output="ram_block_M144K[0].data_b_in[23]">
            <delay_constant in_port="M144K.data_addr_control_in[89:72] M144K.data_addr_control_in[179:162]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[23]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[251:234] M144K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit24" output="ram_block_M144K[0].data_b_in[24]">
            <delay_constant in_port="M144K.data_addr_control_in[251:234] M144K.data_addr_control_in[71:54]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[24]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[415:414] M144K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit25" output="ram_block_M144K[0].data_b_in[25]">
            <delay_constant in_port="M144K.data_addr_control_in[415:414] M144K.data_addr_control_in[71:54]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[25]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[179:162] M144K.data_addr_control_in[305:288]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit26" output="ram_block_M144K[0].data_b_in[26]">
            <delay_constant in_port="M144K.data_addr_control_in[179:162] M144K.data_addr_control_in[305:288]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[26]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[395:378] M144K.data_addr_control_in[215:198]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit27" output="ram_block_M144K[0].data_b_in[27]">
            <delay_constant in_port="M144K.data_addr_control_in[395:378] M144K.data_addr_control_in[215:198]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[27]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[413:396] M144K.data_addr_control_in[143:126]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit28" output="ram_block_M144K[0].data_b_in[28]">
            <delay_constant in_port="M144K.data_addr_control_in[413:396] M144K.data_addr_control_in[143:126]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[28]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[215:198] M144K.data_addr_control_in[305:288]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit29" output="ram_block_M144K[0].data_b_in[29]">
            <delay_constant in_port="M144K.data_addr_control_in[215:198] M144K.data_addr_control_in[305:288]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[29]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[89:72] M144K.data_addr_control_in[269:252]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit30" output="ram_block_M144K[0].data_b_in[30]">
            <delay_constant in_port="M144K.data_addr_control_in[89:72] M144K.data_addr_control_in[269:252]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[30]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[107:90] M144K.data_addr_control_in[161:144]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit31" output="ram_block_M144K[0].data_b_in[31]">
            <delay_constant in_port="M144K.data_addr_control_in[107:90] M144K.data_addr_control_in[161:144]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[31]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[415:414] M144K.data_addr_control_in[395:378]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit32" output="ram_block_M144K[0].data_b_in[32]">
            <delay_constant in_port="M144K.data_addr_control_in[415:414] M144K.data_addr_control_in[395:378]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[32]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[359:342] M144K.data_addr_control_in[17:0]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit33" output="ram_block_M144K[0].data_b_in[33]">
            <delay_constant in_port="M144K.data_addr_control_in[359:342] M144K.data_addr_control_in[17:0]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[33]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[71:54] M144K.data_addr_control_in[125:108]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit34" output="ram_block_M144K[0].data_b_in[34]">
            <delay_constant in_port="M144K.data_addr_control_in[71:54] M144K.data_addr_control_in[125:108]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[34]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[341:324] M144K.data_addr_control_in[377:360]" name="interconnect_partial_xbar_M144K_data_addr_control_in_2_bit35" output="ram_block_M144K[0].data_b_in[35]">
            <delay_constant in_port="M144K.data_addr_control_in[341:324] M144K.data_addr_control_in[377:360]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_b_in[35]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[251:234] M144K.data_addr_control_in[323:306]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit0" output="ram_block_M144K[0].data_a_in[0]">
            <delay_constant in_port="M144K.data_addr_control_in[251:234] M144K.data_addr_control_in[323:306]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[0]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[359:342] M144K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit1" output="ram_block_M144K[0].data_a_in[1]">
            <delay_constant in_port="M144K.data_addr_control_in[359:342] M144K.data_addr_control_in[35:18]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[1]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[53:36] M144K.data_addr_control_in[377:360]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit2" output="ram_block_M144K[0].data_a_in[2]">
            <delay_constant in_port="M144K.data_addr_control_in[53:36] M144K.data_addr_control_in[377:360]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[2]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[17:0] M144K.data_addr_control_in[107:90]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit3" output="ram_block_M144K[0].data_a_in[3]">
            <delay_constant in_port="M144K.data_addr_control_in[17:0] M144K.data_addr_control_in[107:90]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[3]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[17:0] M144K.data_addr_control_in[377:360]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit4" output="ram_block_M144K[0].data_a_in[4]">
            <delay_constant in_port="M144K.data_addr_control_in[17:0] M144K.data_addr_control_in[377:360]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[4]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[143:126] M144K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit5" output="ram_block_M144K[0].data_a_in[5]">
            <delay_constant in_port="M144K.data_addr_control_in[143:126] M144K.data_addr_control_in[71:54]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[5]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[71:54] M144K.data_addr_control_in[287:270]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit6" output="ram_block_M144K[0].data_a_in[6]">
            <delay_constant in_port="M144K.data_addr_control_in[71:54] M144K.data_addr_control_in[287:270]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[6]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[415:414] M144K.data_addr_control_in[233:216]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit7" output="ram_block_M144K[0].data_a_in[7]">
            <delay_constant in_port="M144K.data_addr_control_in[415:414] M144K.data_addr_control_in[233:216]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[7]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[395:378] M144K.data_addr_control_in[233:216]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit8" output="ram_block_M144K[0].data_a_in[8]">
            <delay_constant in_port="M144K.data_addr_control_in[395:378] M144K.data_addr_control_in[233:216]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[8]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[251:234] M144K.data_addr_control_in[305:288]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit9" output="ram_block_M144K[0].data_a_in[9]">
            <delay_constant in_port="M144K.data_addr_control_in[251:234] M144K.data_addr_control_in[305:288]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[9]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[359:342] M144K.data_addr_control_in[341:324]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit10" output="ram_block_M144K[0].data_a_in[10]">
            <delay_constant in_port="M144K.data_addr_control_in[359:342] M144K.data_addr_control_in[341:324]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[10]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[415:414] M144K.data_addr_control_in[323:306]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit11" output="ram_block_M144K[0].data_a_in[11]">
            <delay_constant in_port="M144K.data_addr_control_in[415:414] M144K.data_addr_control_in[323:306]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[11]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[395:378] M144K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit12" output="ram_block_M144K[0].data_a_in[12]">
            <delay_constant in_port="M144K.data_addr_control_in[395:378] M144K.data_addr_control_in[89:72]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[12]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[233:216] M144K.data_addr_control_in[269:252]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit13" output="ram_block_M144K[0].data_a_in[13]">
            <delay_constant in_port="M144K.data_addr_control_in[233:216] M144K.data_addr_control_in[269:252]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[13]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[359:342] M144K.data_addr_control_in[215:198]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit14" output="ram_block_M144K[0].data_a_in[14]">
            <delay_constant in_port="M144K.data_addr_control_in[359:342] M144K.data_addr_control_in[215:198]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[14]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[341:324] M144K.data_addr_control_in[179:162]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit15" output="ram_block_M144K[0].data_a_in[15]">
            <delay_constant in_port="M144K.data_addr_control_in[341:324] M144K.data_addr_control_in[179:162]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[15]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[269:252] M144K.data_addr_control_in[377:360]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit16" output="ram_block_M144K[0].data_a_in[16]">
            <delay_constant in_port="M144K.data_addr_control_in[269:252] M144K.data_addr_control_in[377:360]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[16]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[359:342] M144K.data_addr_control_in[287:270]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit17" output="ram_block_M144K[0].data_a_in[17]">
            <delay_constant in_port="M144K.data_addr_control_in[359:342] M144K.data_addr_control_in[287:270]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[17]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[17:0] M144K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit18" output="ram_block_M144K[0].data_a_in[18]">
            <delay_constant in_port="M144K.data_addr_control_in[17:0] M144K.data_addr_control_in[89:72]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[18]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[233:216] M144K.data_addr_control_in[125:108]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit19" output="ram_block_M144K[0].data_a_in[19]">
            <delay_constant in_port="M144K.data_addr_control_in[233:216] M144K.data_addr_control_in[125:108]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[19]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[35:18] M144K.data_addr_control_in[377:360]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit20" output="ram_block_M144K[0].data_a_in[20]">
            <delay_constant in_port="M144K.data_addr_control_in[35:18] M144K.data_addr_control_in[377:360]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[20]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[413:396] M144K.data_addr_control_in[143:126]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit21" output="ram_block_M144K[0].data_a_in[21]">
            <delay_constant in_port="M144K.data_addr_control_in[413:396] M144K.data_addr_control_in[143:126]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[21]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[179:162] M144K.data_addr_control_in[359:342]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit22" output="ram_block_M144K[0].data_a_in[22]">
            <delay_constant in_port="M144K.data_addr_control_in[179:162] M144K.data_addr_control_in[359:342]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[22]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[35:18] M144K.data_addr_control_in[287:270]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit23" output="ram_block_M144K[0].data_a_in[23]">
            <delay_constant in_port="M144K.data_addr_control_in[35:18] M144K.data_addr_control_in[287:270]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[23]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[71:54] M144K.data_addr_control_in[125:108]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit24" output="ram_block_M144K[0].data_a_in[24]">
            <delay_constant in_port="M144K.data_addr_control_in[71:54] M144K.data_addr_control_in[125:108]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[24]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[359:342] M144K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit25" output="ram_block_M144K[0].data_a_in[25]">
            <delay_constant in_port="M144K.data_addr_control_in[359:342] M144K.data_addr_control_in[35:18]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[25]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[17:0] M144K.data_addr_control_in[197:180]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit26" output="ram_block_M144K[0].data_a_in[26]">
            <delay_constant in_port="M144K.data_addr_control_in[17:0] M144K.data_addr_control_in[197:180]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[26]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[215:198] M144K.data_addr_control_in[377:360]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit27" output="ram_block_M144K[0].data_a_in[27]">
            <delay_constant in_port="M144K.data_addr_control_in[215:198] M144K.data_addr_control_in[377:360]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[27]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[323:306] M144K.data_addr_control_in[305:288]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit28" output="ram_block_M144K[0].data_a_in[28]">
            <delay_constant in_port="M144K.data_addr_control_in[323:306] M144K.data_addr_control_in[305:288]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[28]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[71:54] M144K.data_addr_control_in[415:414]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit29" output="ram_block_M144K[0].data_a_in[29]">
            <delay_constant in_port="M144K.data_addr_control_in[71:54] M144K.data_addr_control_in[415:414]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[29]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[179:162] M144K.data_addr_control_in[269:252]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit30" output="ram_block_M144K[0].data_a_in[30]">
            <delay_constant in_port="M144K.data_addr_control_in[179:162] M144K.data_addr_control_in[269:252]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[30]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[179:162] M144K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit31" output="ram_block_M144K[0].data_a_in[31]">
            <delay_constant in_port="M144K.data_addr_control_in[179:162] M144K.data_addr_control_in[35:18]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[31]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[215:198] M144K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit32" output="ram_block_M144K[0].data_a_in[32]">
            <delay_constant in_port="M144K.data_addr_control_in[215:198] M144K.data_addr_control_in[71:54]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[32]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[17:0] M144K.data_addr_control_in[269:252]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit33" output="ram_block_M144K[0].data_a_in[33]">
            <delay_constant in_port="M144K.data_addr_control_in[17:0] M144K.data_addr_control_in[269:252]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[33]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[287:270] M144K.data_addr_control_in[53:36]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit34" output="ram_block_M144K[0].data_a_in[34]">
            <delay_constant in_port="M144K.data_addr_control_in[287:270] M144K.data_addr_control_in[53:36]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[34]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[251:234] M144K.data_addr_control_in[161:144]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit35" output="ram_block_M144K[0].data_a_in[35]">
            <delay_constant in_port="M144K.data_addr_control_in[251:234] M144K.data_addr_control_in[161:144]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[35]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[179:162] M144K.data_addr_control_in[341:324]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit36" output="ram_block_M144K[0].data_a_in[36]">
            <delay_constant in_port="M144K.data_addr_control_in[179:162] M144K.data_addr_control_in[341:324]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[36]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[215:198] M144K.data_addr_control_in[395:378]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit37" output="ram_block_M144K[0].data_a_in[37]">
            <delay_constant in_port="M144K.data_addr_control_in[215:198] M144K.data_addr_control_in[395:378]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[37]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[269:252] M144K.data_addr_control_in[215:198]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit38" output="ram_block_M144K[0].data_a_in[38]">
            <delay_constant in_port="M144K.data_addr_control_in[269:252] M144K.data_addr_control_in[215:198]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[38]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[287:270] M144K.data_addr_control_in[161:144]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit39" output="ram_block_M144K[0].data_a_in[39]">
            <delay_constant in_port="M144K.data_addr_control_in[287:270] M144K.data_addr_control_in[161:144]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[39]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[53:36] M144K.data_addr_control_in[305:288]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit40" output="ram_block_M144K[0].data_a_in[40]">
            <delay_constant in_port="M144K.data_addr_control_in[53:36] M144K.data_addr_control_in[305:288]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[40]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[269:252] M144K.data_addr_control_in[341:324]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit41" output="ram_block_M144K[0].data_a_in[41]">
            <delay_constant in_port="M144K.data_addr_control_in[269:252] M144K.data_addr_control_in[341:324]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[41]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[71:54] M144K.data_addr_control_in[395:378]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit42" output="ram_block_M144K[0].data_a_in[42]">
            <delay_constant in_port="M144K.data_addr_control_in[71:54] M144K.data_addr_control_in[395:378]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[42]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[359:342] M144K.data_addr_control_in[413:396]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit43" output="ram_block_M144K[0].data_a_in[43]">
            <delay_constant in_port="M144K.data_addr_control_in[359:342] M144K.data_addr_control_in[413:396]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[43]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[377:360] M144K.data_addr_control_in[305:288]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit44" output="ram_block_M144K[0].data_a_in[44]">
            <delay_constant in_port="M144K.data_addr_control_in[377:360] M144K.data_addr_control_in[305:288]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[44]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[359:342] M144K.data_addr_control_in[233:216]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit45" output="ram_block_M144K[0].data_a_in[45]">
            <delay_constant in_port="M144K.data_addr_control_in[359:342] M144K.data_addr_control_in[233:216]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[45]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[341:324] M144K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit46" output="ram_block_M144K[0].data_a_in[46]">
            <delay_constant in_port="M144K.data_addr_control_in[341:324] M144K.data_addr_control_in[89:72]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[46]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[341:324] M144K.data_addr_control_in[197:180]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit47" output="ram_block_M144K[0].data_a_in[47]">
            <delay_constant in_port="M144K.data_addr_control_in[341:324] M144K.data_addr_control_in[197:180]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[47]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[341:324] M144K.data_addr_control_in[197:180]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit48" output="ram_block_M144K[0].data_a_in[48]">
            <delay_constant in_port="M144K.data_addr_control_in[341:324] M144K.data_addr_control_in[197:180]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[48]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[341:324] M144K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit49" output="ram_block_M144K[0].data_a_in[49]">
            <delay_constant in_port="M144K.data_addr_control_in[341:324] M144K.data_addr_control_in[35:18]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[49]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[35:18] M144K.data_addr_control_in[413:396]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit50" output="ram_block_M144K[0].data_a_in[50]">
            <delay_constant in_port="M144K.data_addr_control_in[35:18] M144K.data_addr_control_in[413:396]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[50]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[215:198] M144K.data_addr_control_in[395:378]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit51" output="ram_block_M144K[0].data_a_in[51]">
            <delay_constant in_port="M144K.data_addr_control_in[215:198] M144K.data_addr_control_in[395:378]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[51]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[413:396] M144K.data_addr_control_in[287:270]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit52" output="ram_block_M144K[0].data_a_in[52]">
            <delay_constant in_port="M144K.data_addr_control_in[413:396] M144K.data_addr_control_in[287:270]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[52]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[251:234] M144K.data_addr_control_in[107:90]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit53" output="ram_block_M144K[0].data_a_in[53]">
            <delay_constant in_port="M144K.data_addr_control_in[251:234] M144K.data_addr_control_in[107:90]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[53]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[53:36] M144K.data_addr_control_in[359:342]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit54" output="ram_block_M144K[0].data_a_in[54]">
            <delay_constant in_port="M144K.data_addr_control_in[53:36] M144K.data_addr_control_in[359:342]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[54]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[395:378] M144K.data_addr_control_in[341:324]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit55" output="ram_block_M144K[0].data_a_in[55]">
            <delay_constant in_port="M144K.data_addr_control_in[395:378] M144K.data_addr_control_in[341:324]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[55]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[305:288] M144K.data_addr_control_in[197:180]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit56" output="ram_block_M144K[0].data_a_in[56]">
            <delay_constant in_port="M144K.data_addr_control_in[305:288] M144K.data_addr_control_in[197:180]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[56]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[143:126] M144K.data_addr_control_in[53:36]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit57" output="ram_block_M144K[0].data_a_in[57]">
            <delay_constant in_port="M144K.data_addr_control_in[143:126] M144K.data_addr_control_in[53:36]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[57]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[197:180] M144K.data_addr_control_in[251:234]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit58" output="ram_block_M144K[0].data_a_in[58]">
            <delay_constant in_port="M144K.data_addr_control_in[197:180] M144K.data_addr_control_in[251:234]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[58]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[413:396] M144K.data_addr_control_in[179:162]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit59" output="ram_block_M144K[0].data_a_in[59]">
            <delay_constant in_port="M144K.data_addr_control_in[413:396] M144K.data_addr_control_in[179:162]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[59]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[53:36] M144K.data_addr_control_in[341:324]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit60" output="ram_block_M144K[0].data_a_in[60]">
            <delay_constant in_port="M144K.data_addr_control_in[53:36] M144K.data_addr_control_in[341:324]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[60]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[323:306] M144K.data_addr_control_in[17:0]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit61" output="ram_block_M144K[0].data_a_in[61]">
            <delay_constant in_port="M144K.data_addr_control_in[323:306] M144K.data_addr_control_in[17:0]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[61]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[197:180] M144K.data_addr_control_in[305:288]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit62" output="ram_block_M144K[0].data_a_in[62]">
            <delay_constant in_port="M144K.data_addr_control_in[197:180] M144K.data_addr_control_in[305:288]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[62]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[17:0] M144K.data_addr_control_in[413:396]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit63" output="ram_block_M144K[0].data_a_in[63]">
            <delay_constant in_port="M144K.data_addr_control_in[17:0] M144K.data_addr_control_in[413:396]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[63]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[415:414] M144K.data_addr_control_in[323:306]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit64" output="ram_block_M144K[0].data_a_in[64]">
            <delay_constant in_port="M144K.data_addr_control_in[415:414] M144K.data_addr_control_in[323:306]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[64]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[35:18] M144K.data_addr_control_in[161:144]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit65" output="ram_block_M144K[0].data_a_in[65]">
            <delay_constant in_port="M144K.data_addr_control_in[35:18] M144K.data_addr_control_in[161:144]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[65]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[17:0] M144K.data_addr_control_in[161:144]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit66" output="ram_block_M144K[0].data_a_in[66]">
            <delay_constant in_port="M144K.data_addr_control_in[17:0] M144K.data_addr_control_in[161:144]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[66]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[17:0] M144K.data_addr_control_in[415:414]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit67" output="ram_block_M144K[0].data_a_in[67]">
            <delay_constant in_port="M144K.data_addr_control_in[17:0] M144K.data_addr_control_in[415:414]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[67]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[359:342] M144K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit68" output="ram_block_M144K[0].data_a_in[68]">
            <delay_constant in_port="M144K.data_addr_control_in[359:342] M144K.data_addr_control_in[35:18]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[68]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[395:378] M144K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit69" output="ram_block_M144K[0].data_a_in[69]">
            <delay_constant in_port="M144K.data_addr_control_in[395:378] M144K.data_addr_control_in[89:72]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[69]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[89:72] M144K.data_addr_control_in[305:288]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit70" output="ram_block_M144K[0].data_a_in[70]">
            <delay_constant in_port="M144K.data_addr_control_in[89:72] M144K.data_addr_control_in[305:288]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[70]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[413:396] M144K.data_addr_control_in[53:36]" name="interconnect_partial_xbar_M144K_data_addr_control_in_3_bit71" output="ram_block_M144K[0].data_a_in[71]">
            <delay_constant in_port="M144K.data_addr_control_in[413:396] M144K.data_addr_control_in[53:36]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].data_a_in[71]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[17:0] M144K.data_addr_control_in[161:144]" name="interconnect_partial_xbar_M144K_data_addr_control_in_4_bit0" output="ram_block_M144K[0].addr_a_in[0]">
            <delay_constant in_port="M144K.data_addr_control_in[17:0] M144K.data_addr_control_in[161:144]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_a_in[0]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[17:0] M144K.data_addr_control_in[269:252]" name="interconnect_partial_xbar_M144K_data_addr_control_in_4_bit1" output="ram_block_M144K[0].addr_a_in[1]">
            <delay_constant in_port="M144K.data_addr_control_in[17:0] M144K.data_addr_control_in[269:252]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_a_in[1]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[377:360] M144K.data_addr_control_in[89:72]" name="interconnect_partial_xbar_M144K_data_addr_control_in_4_bit2" output="ram_block_M144K[0].addr_a_in[2]">
            <delay_constant in_port="M144K.data_addr_control_in[377:360] M144K.data_addr_control_in[89:72]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_a_in[2]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[53:36] M144K.data_addr_control_in[161:144]" name="interconnect_partial_xbar_M144K_data_addr_control_in_4_bit3" output="ram_block_M144K[0].addr_a_in[3]">
            <delay_constant in_port="M144K.data_addr_control_in[53:36] M144K.data_addr_control_in[161:144]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_a_in[3]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[415:414] M144K.data_addr_control_in[71:54]" name="interconnect_partial_xbar_M144K_data_addr_control_in_4_bit4" output="ram_block_M144K[0].addr_a_in[4]">
            <delay_constant in_port="M144K.data_addr_control_in[415:414] M144K.data_addr_control_in[71:54]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_a_in[4]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[415:414] M144K.data_addr_control_in[161:144]" name="interconnect_partial_xbar_M144K_data_addr_control_in_4_bit5" output="ram_block_M144K[0].addr_a_in[5]">
            <delay_constant in_port="M144K.data_addr_control_in[415:414] M144K.data_addr_control_in[161:144]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_a_in[5]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[215:198] M144K.data_addr_control_in[143:126]" name="interconnect_partial_xbar_M144K_data_addr_control_in_4_bit6" output="ram_block_M144K[0].addr_a_in[6]">
            <delay_constant in_port="M144K.data_addr_control_in[215:198] M144K.data_addr_control_in[143:126]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_a_in[6]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[413:396] M144K.data_addr_control_in[287:270]" name="interconnect_partial_xbar_M144K_data_addr_control_in_4_bit7" output="ram_block_M144K[0].addr_a_in[7]">
            <delay_constant in_port="M144K.data_addr_control_in[413:396] M144K.data_addr_control_in[287:270]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_a_in[7]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[89:72] M144K.data_addr_control_in[415:414]" name="interconnect_partial_xbar_M144K_data_addr_control_in_4_bit8" output="ram_block_M144K[0].addr_a_in[8]">
            <delay_constant in_port="M144K.data_addr_control_in[89:72] M144K.data_addr_control_in[415:414]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_a_in[8]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[53:36] M144K.data_addr_control_in[251:234]" name="interconnect_partial_xbar_M144K_data_addr_control_in_4_bit9" output="ram_block_M144K[0].addr_a_in[9]">
            <delay_constant in_port="M144K.data_addr_control_in[53:36] M144K.data_addr_control_in[251:234]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_a_in[9]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[71:54] M144K.data_addr_control_in[395:378]" name="interconnect_partial_xbar_M144K_data_addr_control_in_4_bit10" output="ram_block_M144K[0].addr_a_in[10]">
            <delay_constant in_port="M144K.data_addr_control_in[71:54] M144K.data_addr_control_in[395:378]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_a_in[10]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[413:396] M144K.data_addr_control_in[359:342]" name="interconnect_partial_xbar_M144K_data_addr_control_in_4_bit11" output="ram_block_M144K[0].addr_a_in[11]">
            <delay_constant in_port="M144K.data_addr_control_in[413:396] M144K.data_addr_control_in[359:342]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_a_in[11]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[143:126] M144K.data_addr_control_in[107:90]" name="interconnect_partial_xbar_M144K_data_addr_control_in_4_bit12" output="ram_block_M144K[0].addr_a_in[12]">
            <delay_constant in_port="M144K.data_addr_control_in[143:126] M144K.data_addr_control_in[107:90]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_a_in[12]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[341:324] M144K.data_addr_control_in[125:108]" name="interconnect_partial_xbar_M144K_data_addr_control_in_4_bit13" output="ram_block_M144K[0].addr_a_in[13]">
            <delay_constant in_port="M144K.data_addr_control_in[341:324] M144K.data_addr_control_in[125:108]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_a_in[13]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[197:180] M144K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M144K_data_addr_control_in_5_bit0" output="ram_block_M144K[0].addr_b_in[0]">
            <delay_constant in_port="M144K.data_addr_control_in[197:180] M144K.data_addr_control_in[35:18]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_b_in[0]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[71:54] M144K.data_addr_control_in[17:0]" name="interconnect_partial_xbar_M144K_data_addr_control_in_5_bit1" output="ram_block_M144K[0].addr_b_in[1]">
            <delay_constant in_port="M144K.data_addr_control_in[71:54] M144K.data_addr_control_in[17:0]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_b_in[1]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[35:18] M144K.data_addr_control_in[197:180]" name="interconnect_partial_xbar_M144K_data_addr_control_in_5_bit2" output="ram_block_M144K[0].addr_b_in[2]">
            <delay_constant in_port="M144K.data_addr_control_in[35:18] M144K.data_addr_control_in[197:180]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_b_in[2]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[251:234] M144K.data_addr_control_in[323:306]" name="interconnect_partial_xbar_M144K_data_addr_control_in_5_bit3" output="ram_block_M144K[0].addr_b_in[3]">
            <delay_constant in_port="M144K.data_addr_control_in[251:234] M144K.data_addr_control_in[323:306]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_b_in[3]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[71:54] M144K.data_addr_control_in[197:180]" name="interconnect_partial_xbar_M144K_data_addr_control_in_5_bit4" output="ram_block_M144K[0].addr_b_in[4]">
            <delay_constant in_port="M144K.data_addr_control_in[71:54] M144K.data_addr_control_in[197:180]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_b_in[4]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[287:270] M144K.data_addr_control_in[53:36]" name="interconnect_partial_xbar_M144K_data_addr_control_in_5_bit5" output="ram_block_M144K[0].addr_b_in[5]">
            <delay_constant in_port="M144K.data_addr_control_in[287:270] M144K.data_addr_control_in[53:36]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_b_in[5]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[197:180] M144K.data_addr_control_in[161:144]" name="interconnect_partial_xbar_M144K_data_addr_control_in_5_bit6" output="ram_block_M144K[0].addr_b_in[6]">
            <delay_constant in_port="M144K.data_addr_control_in[197:180] M144K.data_addr_control_in[161:144]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_b_in[6]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[413:396] M144K.data_addr_control_in[35:18]" name="interconnect_partial_xbar_M144K_data_addr_control_in_5_bit7" output="ram_block_M144K[0].addr_b_in[7]">
            <delay_constant in_port="M144K.data_addr_control_in[413:396] M144K.data_addr_control_in[35:18]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_b_in[7]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[179:162] M144K.data_addr_control_in[197:180]" name="interconnect_partial_xbar_M144K_data_addr_control_in_5_bit8" output="ram_block_M144K[0].addr_b_in[8]">
            <delay_constant in_port="M144K.data_addr_control_in[179:162] M144K.data_addr_control_in[197:180]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_b_in[8]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[323:306] M144K.data_addr_control_in[143:126]" name="interconnect_partial_xbar_M144K_data_addr_control_in_5_bit9" output="ram_block_M144K[0].addr_b_in[9]">
            <delay_constant in_port="M144K.data_addr_control_in[323:306] M144K.data_addr_control_in[143:126]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_b_in[9]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[89:72] M144K.data_addr_control_in[143:126]" name="interconnect_partial_xbar_M144K_data_addr_control_in_5_bit10" output="ram_block_M144K[0].addr_b_in[10]">
            <delay_constant in_port="M144K.data_addr_control_in[89:72] M144K.data_addr_control_in[143:126]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_b_in[10]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[215:198] M144K.data_addr_control_in[413:396]" name="interconnect_partial_xbar_M144K_data_addr_control_in_5_bit11" output="ram_block_M144K[0].addr_b_in[11]">
            <delay_constant in_port="M144K.data_addr_control_in[215:198] M144K.data_addr_control_in[413:396]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_b_in[11]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[359:342] M144K.data_addr_control_in[125:108]" name="interconnect_partial_xbar_M144K_data_addr_control_in_5_bit12" output="ram_block_M144K[0].addr_b_in[12]">
            <delay_constant in_port="M144K.data_addr_control_in[359:342] M144K.data_addr_control_in[125:108]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_b_in[12]"/>
          </complete>
          <complete input="M144K.data_addr_control_in[251:234] M144K.data_addr_control_in[305:288]" name="interconnect_partial_xbar_M144K_data_addr_control_in_5_bit13" output="ram_block_M144K[0].addr_b_in[13]">
            <delay_constant in_port="M144K.data_addr_control_in[251:234] M144K.data_addr_control_in[305:288]" max="2.01e-10" min="1.71e-10" out_port="ram_block_M144K[0].addr_b_in[13]"/>
          </complete>
          <direct input="M144K.clk_in[1:0]" name="interconnect_full_M144K_clk_in_1" output="ram_block_M144K[0].clk_in[1:0] "/>
          <direct input="ram_block_M144K[0].control_out[2:0] " name="interconnect_full_M144K_control_out_1" output="M144K.control_out[2:0]">
            <delay_constant in_port="ram_block_M144K[0].control_out[2:0] " max="5.9e-11" min="4.4e-11" out_port="M144K.control_out[2:0]"/>
          </direct>
        </interconnect>
      </mode>
    </pb_type>
  </complexblocklist>
  <switchblocklist>
    <!-- Stratix IV uses a uni-directional routing architecture with a Driver Input Mux (DIM) size of 12 (i.e.
           each wire can be driven by one of 12 block/outputs or wires) for the L4s.
           
           In the Stratix IV architecture the long wires (L16 here) are accessible only from the short wires, 
           and are not connected to the block pins (i.e. connection blocks). Furthermore, they only connect 
           to switch blocks every 4 LABs (to avoid expensive deep via stacks).
           We approximate the L16 DIM size as 40:1 (in reality it is a pair of 20:1 (?) muxes with a 2:1 swap mux
           in front, which has nearly the same connectivity as a full 40:1).

           L4 wires
           ================
           At a channel width of 300 there are 260 L4/L4prime wires. At an effective Fc_out of 0.075 
           and 40 LAB outputs this yeilds:

                40 * 2 = 80 outputs per channel  [2 LABs per-channel]

                80 * 0.075 = 6 outputs drive each L4 wire [output connection block]

           This leaves:

                12 - 6 = 6 inputs to the DIMs from other routing wires [switch block]

           Since L4s connect at every switch block, there are:

                260 L16 wires per channel + direction which can drive wires at a particular switchblock
                (via switchpoints 0, 1, 2, 3)

           And for each direction (260 wires) only:

               260 / 4 = 65 wires starting/ending per channel + direction at each switch block
               (i.e. from each direction, north/south/east/west, there are 32 L4s starting, and 32 L4s ending; + 1 wire for the 65th)

           Which we allocate as follows:

                L4
                =====
                straight-through connection: 2 (from L4 or L16)
                clock-wise turn            : 2 (from L4 or L16)
                counter-clock-wise turn    : 2 (from L4 or L16)

           L16 wires
           =========
           At a channel width of 300 there are 40 L16 wires (20 in each direction), which do not connect to the input/output connection blocks.
           This leaves 40 inputs to the DIM to select from routing wires (long wires use larger DIMs to improve reachability,
           the area cost is relatively small since they are so rare).

           Since L16s only connect at every 4th switch block there are:

                40 / 4 = 10 L16 wires per channel (5 in each direction) which can drive wires at a particular switchblock
                (via switchpoints 0, 4, 8, 12)

           And for each direction (20 wires) only:

               40 / 16 = 2.25 => 2 wires starting/ending per channel + direction at each switch block
               (i.e. from each direction, north/south/east/west, there is one L16 starting, and one L16 ending)
           
           We assign the 40 DIM inputs as follows:

                L16
                =====
                straight-through connection:  3 (from L16)
                straight-through connection: 11 (from L4)
                clock-wise turn            :  3 (from L16)
                clock-wise turn            : 10 (from L4)
                counter clock-wise turn    :  3 (from L16)
                counter clock-wise turn    : 10 (from L4)

           Switch pattern
           ==============
           This switch block is based on the Wilton switch block (see Page 103 of Steve Wilton's PhD Thesis 
           "Architecture and Algorithms for Field-Programmable Gate Arrays with Embedded Memory", 1997):

                left-to-top: W - t
                top-to-right: t + 1
                right-to-bottom: 2*W - 2 - t
                bottom-to-left: t + 1
                left-to-right: t
                top-to-bottom: t

           Since Wilton assumed bidirection routing (while we use unidirectional routing),
           we mirror the clock-wise turns to match the conter-clock-wise specification.
           -->
    <switchblock name="wilton_turn_clockwise_core" type="unidir">
      <switchblock_location type="CORE"/>
      <switchfuncs>
        <!-- Clock-wise turns -->
        <func type="tl" formula="W-t"/>
        <!-- top to left -->
        <func type="rt" formula="t+1"/>
        <!-- right to top -->
        <func type="br" formula="2*W-2-t"/>
        <!-- bottom to right -->
        <func type="lb" formula="t+1"/>
        <!-- left to bottom -->
      </switchfuncs>
      <!-- L16 drivers -->
      <wireconn num_conns="3*to" from_type="L16" from_switchpoint="0,12,8,4" to_type="L16" to_switchpoint="0"/>
      <wireconn num_conns="10*to" from_type="L4" from_switchpoint="0" to_type="L16" to_switchpoint="0"/>
      <!-- L4 drivers 

               Driving from L16 (few) to L4 (many) preferr driving from end-point of L16, although since there are many they will
               all be multiply connected.
               
               Driving from L4 (many) to L4 (many) shuffle the switchpoints so the L4's are driven from a variety of switchpoints.
               Since the actual number L4s starting/ending are equal, using 'fixed' from_order would mean only switchpoint 0 -> 0
               connections. A 'shuffled' order will mix-up the from switchpoints for more diversity.
               -->
      <wireconn num_conns="2*to" from_order="shuffled">
        <from type="L16" switchpoint="0,12,8,4"/>
        <from type="L4" switchpoint="0,1,2,3"/>
        <to type="L4" switchpoint="0"/>
      </wireconn>
    </switchblock>
    <switchblock name="wilton_turn_counter_clockwise_core" type="unidir">
      <switchblock_location type="CORE"/>
      <switchfuncs>
        <!-- Counter-clock-wise turns -->
        <func type="lt" formula="W-t"/>
        <!-- left to top -->
        <func type="tr" formula="t+1"/>
        <!-- top to right -->
        <func type="rb" formula="2*W-2-t"/>
        <!-- right to bottom -->
        <func type="bl" formula="t+1"/>
        <!-- bottom to left -->
      </switchfuncs>
      <!-- L16 drivers -->
      <wireconn num_conns="3*to" from_type="L16" from_switchpoint="0,12,8,4" to_type="L16" to_switchpoint="0"/>
      <wireconn num_conns="10*to" from_type="L4" from_switchpoint="0" to_type="L16" to_switchpoint="0"/>
      <!-- L4 drivers 

               Driving from L16 (few) to L4 (many) preferr driving from end-point of L16, although since there are many they will
               all be multiply connected.
               
               Driving from L4 (many) to L4 (many) shuffle the switchpoints so the L4's are driven from a variety of switchpoints.
               Since the actual number L4s starting/ending are equal, using 'fixed' from_order would mean only switchpoint 0 -> 0
               connections. A 'shuffled' order will mix-up the from switchpoints for more diversity.

               Note that a different from_switchpoints ordering is used to ensure a different shuffling occurs compared to 
               wilton_turn_clockwise_core.
               -->
      <wireconn num_conns="2*to" from_order="shuffled">
        <from type="L16" switchpoint="0,12,8,4"/>
        <from type="L4" switchpoint="0,1,2,3"/>
        <to type="L4" switchpoint="0"/>
      </wireconn>
    </switchblock>
    <switchblock name="wilton_straight" type="unidir">
      <switchblock_location type="EVERYWHERE"/>
      <switchfuncs>
        <!-- Straight -->
        <func type="lr" formula="t"/>
        <!-- left to right -->
        <func type="tb" formula="t"/>
        <!-- top to bottom -->
        <func type="rl" formula="t"/>
        <!-- right to left -->
        <func type="bt" formula="t"/>
        <!-- bottom to top -->
      </switchfuncs>
      <!-- L16 Drivers 
                Note that we order the switchpoints in order of preference, since VPR currently
                iterates through the source sets in order, such that we connect first to wires
                ending at the switchblock (switchpoint 0), and then fallback to switchpoints
                in decreasing distance from the drive point (if we have more to's than from's
                it then wraps around).

                Note also that we multiply the number of expected connections by 'to', since while usually
                there is only one 'to' wire, ocasionally there may be more, and we want to ensure they all
                get the same number of connections.

                For L16->L16:
                  We allow any valid switchpoint to be used as the 'from' point.
                  Allow 'low' switchpoints like '4' may seem counter-intuitive (i.e. why not use a cheaper L4)
                  this makes it easier to bypass once on the L16 network (e.g. to get around congestion).
           -->
      <wireconn num_conns="3*to" from_type="L16" from_switchpoint="0,12,8,4" to_type="L16" to_switchpoint="0"/>
      <wireconn num_conns="11*to" from_type="L4" from_switchpoint="0,3,2,1" to_type="L16" to_switchpoint="0"/>
      <!-- L4 Drivers -->
      <wireconn num_conns="2*to" from_order="shuffled">
        <from type="L16" switchpoint="0,12,8,4"/>
        <from type="L4" switchpoint="0"/>
        <to type="L4" switchpoint="0"/>
      </wireconn>
      <!--<wireconn num_conns="1*to" from_type="L4" from_switchpoint="0" to_type="L4" to_switchpoint="0"/>-->
      <!--<wireconn num_conns="1*to" from_type="L16" from_switchpoint="0,12,8,4" to_type="L4" to_switchpoint="0"/>-->
    </switchblock>
    <switchblock name="wilton_straight_corner" type="unidir">
      <!-- Same as wilton straight, but turning around a corner -->
      <switchblock_location type="CORNER"/>
      <switchfuncs>
        <!-- Counter-clock-wise turns -->
        <func type="lt" formula="t"/>
        <!-- left to top -->
        <func type="tr" formula="t"/>
        <!-- top to right -->
        <func type="rb" formula="t"/>
        <!-- right to bottom -->
        <func type="bl" formula="t"/>
        <!-- bottom to left -->
        <!-- Clock-wise turns -->
        <func type="tl" formula="t"/>
        <!-- top to left -->
        <func type="rt" formula="t"/>
        <!-- right to top -->
        <func type="br" formula="t"/>
        <!-- bottom to right -->
        <func type="lb" formula="t"/>
        <!-- left to bottom -->
      </switchfuncs>
      <!-- L16 Drivers -->
      <wireconn num_conns="3*to" from_type="L16" from_switchpoint="0,12,8,4" to_type="L16" to_switchpoint="0"/>
      <wireconn num_conns="11*to" from_type="L4" from_switchpoint="0,3,2,1" to_type="L16" to_switchpoint="0"/>
      <!-- L4 Drivers -->
      <wireconn num_conns="2*to" from_order="shuffled">
        <from type="L16" switchpoint="0,12,8,4"/>
        <from type="L4" switchpoint="0"/>
        <to type="L4" switchpoint="0"/>
      </wireconn>
      <!--<wireconn num_conns="1*to" from_type="L4" from_switchpoint="0" to_type="L4" to_switchpoint="0"/>-->
      <!--<wireconn num_conns="1*to" from_type="L16" from_switchpoint="0,12,8,4" to_type="L4" to_switchpoint="0"/>-->
    </switchblock>
    <switchblock name="wilton_turn_fringe" type="unidir">
      <!-- Non-corner perimeter SBs -->
      <switchblock_location type="FRINGE"/>
      <switchfuncs>
        <!-- Counter-clock-wise turns -->
        <func type="lt" formula="W-t"/>
        <!-- left to top -->
        <func type="tr" formula="t+1"/>
        <!-- top to right -->
        <func type="rb" formula="2*W-2-t"/>
        <!-- right to bottom -->
        <func type="bl" formula="t+1"/>
        <!-- bottom to left -->
        <!-- Clock-wise turns -->
        <func type="tl" formula="W-t"/>
        <!-- top to left -->
        <func type="rt" formula="t+1"/>
        <!-- right to top -->
        <func type="br" formula="2*W-2-t"/>
        <!-- bottom to right -->
        <func type="lb" formula="t+1"/>
        <!-- left to bottom -->
      </switchfuncs>
      <!-- We use 'max' style connections here to ensure there are no dangling wires, otherwise like core turns -->
      <!-- L16 drivers -->
      <wireconn num_conns="3*max(from,to)" from_type="L16" from_switchpoint="0,12,8,4" to_type="L16" to_switchpoint="0"/>
      <wireconn num_conns="21*max(from,to)" from_type="L4" from_switchpoint="0" to_type="L16" to_switchpoint="0"/>
      <!-- L4 drivers -->
      <wireconn num_conns="1*max(from,to)" from_type="L16" from_switchpoint="0,12,8,4" from_order="fixed" to_type="L4" to_switchpoint="0"/>
      <wireconn num_conns="1*max(from,to)" from_type="L4" from_switchpoint="0,1,2,3" from_order="shuffled" to_type="L4" to_switchpoint="0"/>
    </switchblock>
  </switchblocklist>
</architecture>