tree 4e2e7cca9ef3541b940b16b644677b34c7c2064b
parent 67b66d35146348c4f9cca33b39af0a340d4e724e
author kmurray <k.murray@utoronto.ca> 1572285931 -0400
committer kmurray <k.murray@utoronto.ca> 1572289500 -0400

vpr: Add support for tracing clock nets through general logic

Previously we only traced clocks back through explicit .names buffers.

Instead, we now trace clocks back through any primitive combinational connections,
effectively assuming that those connections represent non-inverting
buffers which are independent.

This maintains the current behaviour of tracing back through .names
buffers, and should also handle the case of a black-box buffer
correctly.

In the case this is not the behaviour the end-user desires, they can
explicitly specify (via an SDC file) upon which (potentially
inter-mediate) pins in the netlist the clocks should be created.