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foss-fpga-tools/third_party/vtr-verilog-to-routing/5317abd54c23b8a1fbb7a47a06b29e70c6e541b8/./vtr_flow/arch/timing/fixed_size
tree: 9e14694fd84dd02c5aa393d06294b35a58bfefa2
  1. fixed_k6_frac_2ripple_N8_22nm.xml
  2. fixed_k6_frac_2uripple_N8_22nm.xml
  3. fixed_k6_frac_N8_22nm.xml
  4. fixed_k6_frac_ripple_N8_22nm.xml
  5. fixed_k6_frac_uripple_N8_22nm.xml
  6. fixed_k6_N8_gate_boost_0.2V_22nm.xml
  7. fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml
  8. fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml
  9. fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml
  10. fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml
  11. fixed_nointerclb_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml
  12. fixed_nointerclb_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml
  13. fixed_nointerclb_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml
  14. fixed_nointerclb_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml