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foss-fpga-tools
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third_party
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vtr-verilog-to-routing
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637c3c953181efdb71652479d2a566ef7ff7f4e0
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.
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vtr_flow
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arch
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timing
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fixed_size
tree: f002618d95748c9a2458347a8c9fd00e453a3b7d [
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fixed_k6_frac_2ripple_N8_22nm.xml
fixed_k6_frac_2uripple_N8_22nm.xml
fixed_k6_frac_N8_22nm.xml
fixed_k6_frac_ripple_N8_22nm.xml
fixed_k6_frac_uripple_N8_22nm.xml
fixed_k6_N8_gate_boost_0.2V_22nm.xml
fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml
fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml
fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml
fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml
fixed_nointerclb_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml
fixed_nointerclb_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml
fixed_nointerclb_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml
fixed_nointerclb_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml
