  <architecture>

  <!-- jluu and ken: ODIN II specific config -->
  <models>
    <model name="multiply">
      <input_ports>
      <port name="a"/>
      <port name="b"/>
      </input_ports>
      <output_ports>
      <port name="out"/>
      </output_ports>
    </model>

    <model name="single_port_ram">
      <input_ports>
      <port name="we"/>     <!-- control -->
      <port name="addr"/>  <!-- address lines -->
      <port name="data"/>  <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
      <port name="clk" is_clock="1"/>  <!-- memories are often clocked -->
      </input_ports>
      <output_ports>
      <port name="out"/>   <!-- output can be broken down into smaller bit widths minimum size 1 -->
      </output_ports>
    </model>

    <model name="dual_port_ram">
      <input_ports>
      <port name="we1"/>     <!-- write enable -->
      <port name="we2"/>     <!-- write enable -->
      <port name="addr1"/>  <!-- address lines -->
      <port name="addr2"/>  <!-- address lines -->
      <port name="data1"/>  <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
      <port name="data2"/>  <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
      <port name="clk" is_clock="1"/>  <!-- memories are often clocked -->
      </input_ports>
      <output_ports>
      <port name="out1"/>   <!-- output can be broken down into smaller bit widths minimum size 1 -->
      <port name="out2"/>   <!-- output can be broken down into smaller bit widths minimum size 1 -->
      </output_ports>
    </model>
  </models>
  <!-- jluu and ken: ODIN II specific config ends -->

  <!-- jluu and ken: Physical descriptions begin -->
<!-- <layout width="20" height="20"/> -->
<layout auto="1.0"/>
    <device>
      <sizing R_minW_nmos="5726.870117" R_minW_pmos="15491.700195" ipin_mux_trans_size="1.000000"/>
      <timing C_ipin_cblock="1.191000e-14" T_ipin_cblock="1.482000e-10"/>
      <area grid_logic_tile_area="30000.000000"/>
      <chan_width_distr>
        <io width="1.000000"/>
        <x distr="uniform" peak="1.000000"/>
        <y distr="uniform" peak="1.000000"/>
      </chan_width_distr>
      <switch_block type="wilton" fs="3"/>
    </device>
    <switchlist>
      <switch type="mux" name="0" R="94.841003" Cin="1.537000e-14" Cout="2.194000e-13" Tdel="6.562000e-11" mux_trans_size="10.000000" buf_size="1"/>
    </switchlist>
    <segmentlist>
      <segment freq="1.000000" length="4" type="unidir" Rmetal="11.064550" Cmetal="4.727860e-14">
        <mux name="0"/>
        <sb type="pattern">1 1 1 1 1</sb>
        <cb type="pattern">1 1 1 1</cb>
      </segment>
    </segmentlist>
    <complexblocklist>
      <pb_type name="io" capacity="7">
        <input name="outpad" num_pins="1" equivalent="false"/>
        <output name="inpad" num_pins="1"/>
        <clock name="clock" num_pins="1"/>

        <!-- IOs can operate as either inputs or outputs -->
        <mode name="inpad">
          <pb_type name="inpad" blif_model=".input" num_pb="1">
            <output name="inpad" num_pins="1"/>
          </pb_type>
          <interconnect>
            <direct name="inpad" input="inpad.inpad" output="io.inpad"/>
          </interconnect>
      
        </mode>
        <mode name="outpad">
          <pb_type name="outpad" blif_model=".output" num_pb="1">
            <input name="outpad" num_pins="1"/>
          </pb_type>
          <interconnect>
            <direct name="outpad" input="io.outpad" output="outpad.outpad"/>
          </interconnect>
        </mode>

        <fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.125"/>

        <!-- IOs go on the periphery of the FPGA, for consistency, 
          make it physically equivalent on all sides so that only one definition of I/Os is needed.
          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
        -->
        <pinlocations pattern="custom">
          <loc side="left">io.outpad io.inpad io.clock</loc>
          <loc side="top">io.outpad io.inpad io.clock</loc>
          <loc side="right">io.outpad io.inpad io.clock</loc>
          <loc side="bottom">io.outpad io.inpad io.clock</loc>
        </pinlocations>

        <gridlocations>
          <loc type="perimeter" priority="10"/>
        </gridlocations>

      </pb_type>
      <pb_type name="clb">
        
          <input name="I" num_pins="56" equivalent="true"/>
          <output name="O" num_pins="16"/>
          <clock name="clk" num_pins="1"/>
          <pb_type name="ble" num_pb="8">
             <input name="in" num_pins="7"/>
             <output name="out" num_pins="2"/>
             <clock name="clk" num_pins="1"/>
             <pb_type name="soft_logic" num_pb="1">
               <input name="in" num_pins="7"/>
               <output name="out" num_pins="2"/>
            <mode name="n2_lut5">
              <pb_type name="lut5" blif_model=".names" num_pb="2" class="lut">
                <input name="in" num_pins="5" port_class="lut_in"/>
                <output name="out" num_pins="1" port_class="lut_out"/>
              </pb_type>
              <interconnect>
                <direct name="direct1" input="soft_logic.in[4:0]" output="lut5[0:0].in[4:0]"/>
                <direct name="direct2" input="lut5[0:0].out" output="soft_logic.out[0:0]"/>
                <direct name="direct3" input="soft_logic.in[6:2]" output="lut5[1:1].in[4:0]"/>
                <direct name="direct4" input="lut5[1:1].out" output="soft_logic.out[1:1]"/>
              </interconnect>
            </mode>
            <mode name="n1_lut6">
              <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
                <input name="in" num_pins="6" port_class="lut_in"/>
                <output name="out" num_pins="1" port_class="lut_out"/>
              </pb_type>
              <interconnect>
                <direct name="direct1" input="soft_logic.in[5:0]" output="lut6[0:0].in[5:0]"/>
                <direct name="direct2" input="lut6[0:0].out" output="soft_logic.out[0:0]"/>
              </interconnect>
            </mode>
             </pb_type>
          <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
            <input name="D" num_pins="1" port_class="D"/>
            <output name="Q" num_pins="1" port_class="Q"/>
            <clock name="clk" num_pins="1" port_class="clock"/>
          </pb_type>
            <interconnect>
              <!-- Two ff, make ff available to only corresponding luts -->
              <direct name="direct1" input="ble.in" output="soft_logic.in"/>
              <direct name="direct2" input="soft_logic.out[0:0]" output="ff[0:0].D"/>
              <direct name="direct3" input="soft_logic.out[1:1]" output="ff[1:1].D"/>
              <direct name="direct4" input="ble.clk" output="ff[0:0].clk"/>
              <direct name="direct5" input="ble.clk" output="ff[1:1].clk"/>
              <mux name="mux1" input="ff[0:0].Q soft_logic.out[0:0]" output="ble.out[0:0]"/>
              <mux name="mux2" input="ff[1:1].Q soft_logic.out[1:1]" output="ble.out[1:1]"/>
             </interconnect>
          </pb_type>

          <interconnect>
            <complete name="complete1" input="clb.I ble[7:0].out" output="ble[7:0].in"/>
            <complete name="complete2" input="clb.clk" output="ble[7:0].clk"/>
            <direct name="direct1" input="ble[7:0].out" output="clb.O"/>
          </interconnect>
        <fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.125"/>
        <pinlocations pattern="spread"/>
        <gridlocations>
          <loc type="fill" priority="1"/>
        </gridlocations>
      </pb_type>

      <pb_type name="memory" height="4">
          <input name="addr1" num_pins="16"/>
          <input name="addr2" num_pins="16"/>
          <input name="data" num_pins="64"/>
          <input name="we1" num_pins="1"/>
          <input name="we2" num_pins="1"/>
          <output name="out" num_pins="64"/>
          <clock name="clk" num_pins="1"/>

          <mode name="mem_1024x64_sp">
            <pb_type name="mem_1024x64_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1" area="1000">
              <input name="addr" num_pins="10" port_class="address"/>
              <input name="data" num_pins="64" port_class="data_in"/>
              <input name="we" num_pins="1" port_class="write_en"/>
              <output name="out" num_pins="64" port_class="data_out"/>
              <clock name="clk" num_pins="1" port_class="clock"/>
            </pb_type>
            <interconnect>
              <direct name="address1" input="memory.addr1[9:0]" output="mem_1024x64_sp.addr">
              </direct>
              <direct name="data1" input="memory.data[63:0]" output="mem_1024x64_sp.data">
              </direct>
              <direct name="writeen1" input="memory.we1" output="mem_1024x64_sp.we">
              </direct>
              <direct name="dataout1" input="mem_1024x64_sp.out" output="memory.out[63:0]">
              </direct>
              <direct name="clk" input="memory.clk" output="mem_1024x64_sp.clk">
              </direct>
            </interconnect>
          </mode>
          <mode name="mem_2048x32_dp">
            <pb_type name="mem_2048x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1" area="1000">
              <input name="addr1" num_pins="11" port_class="address1"/>
              <input name="addr2" num_pins="11" port_class="address2"/>
              <input name="data1" num_pins="32" port_class="data_in1"/>
              <input name="data2" num_pins="32" port_class="data_in2"/>
              <input name="we1" num_pins="1" port_class="write_en1"/>
              <input name="we2" num_pins="1" port_class="write_en2"/>
              <output name="out1" num_pins="32" port_class="data_out1"/>
              <output name="out2" num_pins="32" port_class="data_out2"/>
              <clock name="clk" num_pins="1" port_class="clock"/>
            </pb_type>
            <interconnect>
              <direct name="address1" input="memory.addr1[10:0]" output="mem_2048x32_dp.addr1">
              </direct>
              <direct name="address2" input="memory.addr2[10:0]" output="mem_2048x32_dp.addr2">
              </direct>
              <direct name="data1" input="memory.data[31:0]" output="mem_2048x32_dp.data1">
              </direct>
              <direct name="data2" input="memory.data[63:32]" output="mem_2048x32_dp.data2">
              </direct>
              <direct name="writeen1" input="memory.we1" output="mem_2048x32_dp.we1">
              </direct>
              <direct name="writeen2" input="memory.we2" output="mem_2048x32_dp.we2">
              </direct>
              <direct name="dataout1" input="mem_2048x32_dp.out1" output="memory.out[31:0]">
              </direct>
              <direct name="dataout2" input="mem_2048x32_dp.out2" output="memory.out[63:32]">
              </direct>
              <direct name="clk" input="memory.clk" output="mem_2048x32_dp.clk">
              </direct>
            </interconnect>
          </mode>

          <mode name="mem_2048x32_sp">
            <pb_type name="mem_2048x32_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1" area="1000">
              <input name="addr" num_pins="11" port_class="address"/>
              <input name="data" num_pins="32" port_class="data_in"/>
              <input name="we" num_pins="1" port_class="write_en"/>
              <output name="out" num_pins="32" port_class="data_out"/>
              <clock name="clk" num_pins="1" port_class="clock"/>
            </pb_type>
            <interconnect>
              <direct name="address1" input="memory.addr1[10:0]" output="mem_2048x32_sp.addr">
              </direct>
              <direct name="data1" input="memory.data[31:0]" output="mem_2048x32_sp.data">
              </direct>
              <direct name="writeen1" input="memory.we1" output="mem_2048x32_sp.we">
              </direct>
              <direct name="dataout1" input="mem_2048x32_sp.out" output="memory.out[31:0]">
              </direct>
              <direct name="clk" input="memory.clk" output="mem_2048x32_sp.clk">
              </direct>
            </interconnect>
          </mode>
          <mode name="mem_4096x16_dp">
            <pb_type name="mem_4096x16_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1" area="1000">
              <input name="addr1" num_pins="12" port_class="address1"/>
              <input name="addr2" num_pins="12" port_class="address2"/>
              <input name="data1" num_pins="16" port_class="data_in1"/>
              <input name="data2" num_pins="16" port_class="data_in2"/>
              <input name="we1" num_pins="1" port_class="write_en1"/>
              <input name="we2" num_pins="1" port_class="write_en2"/>
              <output name="out1" num_pins="16" port_class="data_out1"/>
              <output name="out2" num_pins="16" port_class="data_out2"/>
              <clock name="clk" num_pins="1" port_class="clock"/>
            </pb_type>
            <interconnect>
              <direct name="address1" input="memory.addr1[11:0]" output="mem_4096x16_dp.addr1">
              </direct>
              <direct name="address2" input="memory.addr2[11:0]" output="mem_4096x16_dp.addr2">
              </direct>
              <direct name="data1" input="memory.data[15:0]" output="mem_4096x16_dp.data1">
              </direct>
              <direct name="data2" input="memory.data[31:16]" output="mem_4096x16_dp.data2">
              </direct>
              <direct name="writeen1" input="memory.we1" output="mem_4096x16_dp.we1">
              </direct>
              <direct name="writeen2" input="memory.we2" output="mem_4096x16_dp.we2">
              </direct>
              <direct name="dataout1" input="mem_4096x16_dp.out1" output="memory.out[15:0]">
              </direct>
              <direct name="dataout2" input="mem_4096x16_dp.out2" output="memory.out[31:16]">
              </direct>
              <direct name="clk" input="memory.clk" output="mem_4096x16_dp.clk">
              </direct>
            </interconnect>
          </mode>

          <mode name="mem_4096x16_sp">
            <pb_type name="mem_4096x16_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1" area="1000">
              <input name="addr" num_pins="12" port_class="address"/>
              <input name="data" num_pins="16" port_class="data_in"/>
              <input name="we" num_pins="1" port_class="write_en"/>
              <output name="out" num_pins="16" port_class="data_out"/>
              <clock name="clk" num_pins="1" port_class="clock"/>
            </pb_type>
            <interconnect>
              <direct name="address1" input="memory.addr1[11:0]" output="mem_4096x16_sp.addr">
              </direct>
              <direct name="data1" input="memory.data[15:0]" output="mem_4096x16_sp.data">
              </direct>
              <direct name="writeen1" input="memory.we1" output="mem_4096x16_sp.we">
              </direct>
              <direct name="dataout1" input="mem_4096x16_sp.out" output="memory.out[15:0]">
              </direct>
              <direct name="clk" input="memory.clk" output="mem_4096x16_sp.clk">
              </direct>
            </interconnect>
          </mode>
          <mode name="mem_8192x8_dp">
            <pb_type name="mem_8192x8_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1" area="1000">
              <input name="addr1" num_pins="13" port_class="address1"/>
              <input name="addr2" num_pins="13" port_class="address2"/>
              <input name="data1" num_pins="8" port_class="data_in1"/>
              <input name="data2" num_pins="8" port_class="data_in2"/>
              <input name="we1" num_pins="1" port_class="write_en1"/>
              <input name="we2" num_pins="1" port_class="write_en2"/>
              <output name="out1" num_pins="8" port_class="data_out1"/>
              <output name="out2" num_pins="8" port_class="data_out2"/>
              <clock name="clk" num_pins="1" port_class="clock"/>
            </pb_type>
            <interconnect>
              <direct name="address1" input="memory.addr1[12:0]" output="mem_8192x8_dp.addr1">
              </direct>
              <direct name="address2" input="memory.addr2[12:0]" output="mem_8192x8_dp.addr2">
              </direct>
              <direct name="data1" input="memory.data[7:0]" output="mem_8192x8_dp.data1">
              </direct>
              <direct name="data2" input="memory.data[15:8]" output="mem_8192x8_dp.data2">
              </direct>
              <direct name="writeen1" input="memory.we1" output="mem_8192x8_dp.we1">
              </direct>
              <direct name="writeen2" input="memory.we2" output="mem_8192x8_dp.we2">
              </direct>
              <direct name="dataout1" input="mem_8192x8_dp.out1" output="memory.out[7:0]">
              </direct>
              <direct name="dataout2" input="mem_8192x8_dp.out2" output="memory.out[15:8]">
              </direct>
              <direct name="clk" input="memory.clk" output="mem_8192x8_dp.clk">
              </direct>
            </interconnect>
          </mode>

          <mode name="mem_8192x8_sp">
            <pb_type name="mem_8192x8_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1" area="1000">
              <input name="addr" num_pins="13" port_class="address"/>
              <input name="data" num_pins="8" port_class="data_in"/>
              <input name="we" num_pins="1" port_class="write_en"/>
              <output name="out" num_pins="8" port_class="data_out"/>
              <clock name="clk" num_pins="1" port_class="clock"/>
            </pb_type>
            <interconnect>
              <direct name="address1" input="memory.addr1[12:0]" output="mem_8192x8_sp.addr">
              </direct>
              <direct name="data1" input="memory.data[7:0]" output="mem_8192x8_sp.data">
              </direct>
              <direct name="writeen1" input="memory.we1" output="mem_8192x8_sp.we">
              </direct>
              <direct name="dataout1" input="mem_8192x8_sp.out" output="memory.out[7:0]">
              </direct>
              <direct name="clk" input="memory.clk" output="mem_8192x8_sp.clk">
              </direct>
            </interconnect>
          </mode>
          <mode name="mem_16384x4_dp">
            <pb_type name="mem_16384x4_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1" area="1000">
              <input name="addr1" num_pins="14" port_class="address1"/>
              <input name="addr2" num_pins="14" port_class="address2"/>
              <input name="data1" num_pins="4" port_class="data_in1"/>
              <input name="data2" num_pins="4" port_class="data_in2"/>
              <input name="we1" num_pins="1" port_class="write_en1"/>
              <input name="we2" num_pins="1" port_class="write_en2"/>
              <output name="out1" num_pins="4" port_class="data_out1"/>
              <output name="out2" num_pins="4" port_class="data_out2"/>
              <clock name="clk" num_pins="1" port_class="clock"/>
            </pb_type>
            <interconnect>
              <direct name="address1" input="memory.addr1[13:0]" output="mem_16384x4_dp.addr1">
              </direct>
              <direct name="address2" input="memory.addr2[13:0]" output="mem_16384x4_dp.addr2">
              </direct>
              <direct name="data1" input="memory.data[3:0]" output="mem_16384x4_dp.data1">
              </direct>
              <direct name="data2" input="memory.data[7:4]" output="mem_16384x4_dp.data2">
              </direct>
              <direct name="writeen1" input="memory.we1" output="mem_16384x4_dp.we1">
              </direct>
              <direct name="writeen2" input="memory.we2" output="mem_16384x4_dp.we2">
              </direct>
              <direct name="dataout1" input="mem_16384x4_dp.out1" output="memory.out[3:0]">
              </direct>
              <direct name="dataout2" input="mem_16384x4_dp.out2" output="memory.out[7:4]">
              </direct>
              <direct name="clk" input="memory.clk" output="mem_16384x4_dp.clk">
              </direct>
            </interconnect>
          </mode>

          <mode name="mem_16384x4_sp">
            <pb_type name="mem_16384x4_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1" area="1000">
              <input name="addr" num_pins="14" port_class="address"/>
              <input name="data" num_pins="4" port_class="data_in"/>
              <input name="we" num_pins="1" port_class="write_en"/>
              <output name="out" num_pins="4" port_class="data_out"/>
              <clock name="clk" num_pins="1" port_class="clock"/>
            </pb_type>
            <interconnect>
              <direct name="address1" input="memory.addr1[13:0]" output="mem_16384x4_sp.addr">
              </direct>
              <direct name="data1" input="memory.data[3:0]" output="mem_16384x4_sp.data">
              </direct>
              <direct name="writeen1" input="memory.we1" output="mem_16384x4_sp.we">
              </direct>
              <direct name="dataout1" input="mem_16384x4_sp.out" output="memory.out[3:0]">
              </direct>
              <direct name="clk" input="memory.clk" output="mem_16384x4_sp.clk">
              </direct>
            </interconnect>
          </mode>
          <mode name="mem_32768x2_dp">
            <pb_type name="mem_32768x2_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1" area="1000">
              <input name="addr1" num_pins="15" port_class="address1"/>
              <input name="addr2" num_pins="15" port_class="address2"/>
              <input name="data1" num_pins="2" port_class="data_in1"/>
              <input name="data2" num_pins="2" port_class="data_in2"/>
              <input name="we1" num_pins="1" port_class="write_en1"/>
              <input name="we2" num_pins="1" port_class="write_en2"/>
              <output name="out1" num_pins="2" port_class="data_out1"/>
              <output name="out2" num_pins="2" port_class="data_out2"/>
              <clock name="clk" num_pins="1" port_class="clock"/>
            </pb_type>
            <interconnect>
              <direct name="address1" input="memory.addr1[14:0]" output="mem_32768x2_dp.addr1">
              </direct>
              <direct name="address2" input="memory.addr2[14:0]" output="mem_32768x2_dp.addr2">
              </direct>
              <direct name="data1" input="memory.data[1:0]" output="mem_32768x2_dp.data1">
              </direct>
              <direct name="data2" input="memory.data[3:2]" output="mem_32768x2_dp.data2">
              </direct>
              <direct name="writeen1" input="memory.we1" output="mem_32768x2_dp.we1">
              </direct>
              <direct name="writeen2" input="memory.we2" output="mem_32768x2_dp.we2">
              </direct>
              <direct name="dataout1" input="mem_32768x2_dp.out1" output="memory.out[1:0]">
              </direct>
              <direct name="dataout2" input="mem_32768x2_dp.out2" output="memory.out[3:2]">
              </direct>
              <direct name="clk" input="memory.clk" output="mem_32768x2_dp.clk">
              </direct>
            </interconnect>
          </mode>

          <mode name="mem_32768x2_sp">
            <pb_type name="mem_32768x2_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1" area="1000">
              <input name="addr" num_pins="15" port_class="address"/>
              <input name="data" num_pins="2" port_class="data_in"/>
              <input name="we" num_pins="1" port_class="write_en"/>
              <output name="out" num_pins="2" port_class="data_out"/>
              <clock name="clk" num_pins="1" port_class="clock"/>
            </pb_type>
            <interconnect>
              <direct name="address1" input="memory.addr1[14:0]" output="mem_32768x2_sp.addr">
              </direct>
              <direct name="data1" input="memory.data[1:0]" output="mem_32768x2_sp.data">
              </direct>
              <direct name="writeen1" input="memory.we1" output="mem_32768x2_sp.we">
              </direct>
              <direct name="dataout1" input="mem_32768x2_sp.out" output="memory.out[1:0]">
              </direct>
              <direct name="clk" input="memory.clk" output="mem_32768x2_sp.clk">
              </direct>
            </interconnect>
          </mode>
          <mode name="mem_65536x1_dp">
            <pb_type name="mem_65536x1_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1" area="1000">
              <input name="addr1" num_pins="16" port_class="address1"/>
              <input name="addr2" num_pins="16" port_class="address2"/>
              <input name="data1" num_pins="1" port_class="data_in1"/>
              <input name="data2" num_pins="1" port_class="data_in2"/>
              <input name="we1" num_pins="1" port_class="write_en1"/>
              <input name="we2" num_pins="1" port_class="write_en2"/>
              <output name="out1" num_pins="1" port_class="data_out1"/>
              <output name="out2" num_pins="1" port_class="data_out2"/>
              <clock name="clk" num_pins="1" port_class="clock"/>
            </pb_type>
            <interconnect>
              <direct name="address1" input="memory.addr1[15:0]" output="mem_65536x1_dp.addr1">
              </direct>
              <direct name="address2" input="memory.addr2[15:0]" output="mem_65536x1_dp.addr2">
              </direct>
              <direct name="data1" input="memory.data[0:0]" output="mem_65536x1_dp.data1">
              </direct>
              <direct name="data2" input="memory.data[1:1]" output="mem_65536x1_dp.data2">
              </direct>
              <direct name="writeen1" input="memory.we1" output="mem_65536x1_dp.we1">
              </direct>
              <direct name="writeen2" input="memory.we2" output="mem_65536x1_dp.we2">
              </direct>
              <direct name="dataout1" input="mem_65536x1_dp.out1" output="memory.out[0:0]">
              </direct>
              <direct name="dataout2" input="mem_65536x1_dp.out2" output="memory.out[1:1]">
              </direct>
              <direct name="clk" input="memory.clk" output="mem_65536x1_dp.clk">
              </direct>
            </interconnect>
          </mode>

          <mode name="mem_65536x1_sp">
            <pb_type name="mem_65536x1_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1" area="1000">
              <input name="addr" num_pins="16" port_class="address"/>
              <input name="data" num_pins="1" port_class="data_in"/>
              <input name="we" num_pins="1" port_class="write_en"/>
              <output name="out" num_pins="1" port_class="data_out"/>
              <clock name="clk" num_pins="1" port_class="clock"/>
            </pb_type>
            <interconnect>
              <direct name="address1" input="memory.addr1[15:0]" output="mem_65536x1_sp.addr">
              </direct>
              <direct name="data1" input="memory.data[0:0]" output="mem_65536x1_sp.data">
              </direct>
              <direct name="writeen1" input="memory.we1" output="mem_65536x1_sp.we">
              </direct>
              <direct name="dataout1" input="mem_65536x1_sp.out" output="memory.out[0:0]">
              </direct>
              <direct name="clk" input="memory.clk" output="mem_65536x1_sp.clk">
              </direct>
            </interconnect>
          </mode>


        <fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.125"/>
        <pinlocations pattern="spread"/>
        <gridlocations>
          <loc type="col" start="2" repeat="5" priority="2"/>
        </gridlocations>
      </pb_type>

      <!-- This is the 36*36 uniform mult -->
      <pb_type name="mult_36" height="3">
          <input name="a" num_pins="36"/>
          <input name="b" num_pins="36"/>
          <output name="out" num_pins="72"/>

          <mode name="two_divisible_mult_18x18">
            <pb_type name="divisible_mult_18x18" num_pb="2">
              <input name="a" num_pins="18"/>
              <input name="b" num_pins="18"/>
              <output name="out" num_pins="36"/>

              <mode name="two_mult_9x9">
                <pb_type name="mult_9x9_slice" num_pb="2">
                  <input name="A_cfg" num_pins="9"/>
                  <input name="B_cfg" num_pins="9"/>
                  <output name="OUT_cfg" num_pins="18"/>

                  <pb_type name="mult_9x9" blif_model=".subckt multiply" num_pb="1" area="300">
                    <input name="a" num_pins="9"/>
                    <input name="b" num_pins="9"/>
                    <output name="out" num_pins="18"/>
                    <delay_constant max="2.03e-13" min="1.89e-13" in_port="{a b}" out_port="out"/>
                  </pb_type>

                  <interconnect>
                    <direct name="a2a" input="mult_9x9_slice.A_cfg" output="mult_9x9.a">
                      <delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_9x9_slice.A_cfg" out_port="mult_9x9.a"/>
                      <C_constant C="1.89e-13" in_port="mult_9x9_slice.A_cfg" out_port="mult_9x9.a"/>
                    </direct>
                    <direct name="b2b" input="mult_9x9_slice.B_cfg" output="mult_9x9.b">
                      <delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_9x9_slice.B_cfg" out_port="mult_9x9.b"/>
                      <C_constant C="1.89e-13" in_port="mult_9x9_slice.B_cfg" out_port="mult_9x9.b"/>
                    </direct>
                    <direct name="out2out" input="mult_9x9.out" output="mult_9x9_slice.OUT_cfg">
                      <delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_9x9.out" out_port="mult_9x9_slice.OUT_cfg"/>
                      <C_constant C="1.89e-13" in_port="mult_9x9.out" out_port="mult_9x9_slice.OUT_cfg"/>
                    </direct>
                  </interconnect>
                </pb_type>
                <interconnect>
                  <direct name="a2a" input="divisible_mult_18x18.a" output="mult_9x9_slice[1:0].A_cfg">
                    <delay_constant max="2.03e-13" min="1.89e-13" in_port="divisible_mult_18x18.a" out_port="mult_9x9_slice[1:0].A_cfg"/>
                    <C_constant C="1.89e-13" in_port="divisible_mult_18x18.a" out_port="mult_9x9_slice[1:0].A_cfg"/>
                  </direct>
                  <direct name="b2b" input="divisible_mult_18x18.b" output="mult_9x9_slice[1:0].B_cfg">
                    <delay_constant max="2.03e-13" min="1.89e-13" in_port="divisible_mult_18x18.b" out_port="mult_9x9_slice[1:0].B_cfg"/>
                    <C_constant C="1.89e-13" in_port="divisible_mult_18x18.b" out_port="mult_9x9_slice[1:0].B_cfg"/>
                  </direct>
                  <direct name="out2out" input="mult_9x9_slice[1:0].OUT_cfg" output="divisible_mult_18x18.out">
                    <delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_9x9_slice[1:0].OUT_cfg" out_port ="divisible_mult_18x18.out"/>
                    <C_constant C="1.89e-13" in_port="mult_9x9_slice[1:0].OUT_cfg" out_port="divisible_mult_18x18.out"/>
                  </direct>
                </interconnect>
              </mode>

              <mode name="mult_18x18">
                <pb_type name="mult_18x18_slice" num_pb="1">
                  <input name="A_cfg" num_pins="18"/>
                  <input name="B_cfg" num_pins="18"/>
                  <output name="OUT_cfg" num_pins="36"/>

                  <pb_type name="mult_18x18" blif_model=".subckt multiply" num_pb="1"  area="1000">
                    <input name="a" num_pins="18"/>
                    <input name="b" num_pins="18"/>
                    <output name="out" num_pins="36"/>
                    <delay_constant max="2.03e-13" min="1.89e-13" in_port="{a b}" out_port="out"/>
                  </pb_type>

                  <interconnect>
                    <direct name="a2a" input="mult_18x18_slice.A_cfg" output="mult_18x18.a">
                      <delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_18x18_slice.A_cfg" out_port="mult_18x18.a"/>
                      <C_constant C="1.89e-13" in_port="mult_18x18_slice.A_cfg" out_port="mult_18x18.a"/>
                    </direct>
                    <direct name="b2b" input="mult_18x18_slice.B_cfg" output="mult_18x18.b">
                      <delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_18x18_slice.B_cfg" out_port="mult_18x18.b"/>
                      <C_constant C="1.89e-13" in_port="mult_18x18_slice.B_cfg" out_port="mult_18x18.b"/>
                    </direct>
                    <direct name="out2out" input="mult_18x18.out" output="mult_18x18_slice.OUT_cfg">
                      <delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_18x18.out" out_port="mult_18x18_slice.OUT_cfg"/>
                      <C_constant C="1.89e-13" in_port="mult_18x18.out" out_port="mult_18x18_slice.OUT_cfg"/>
                    </direct>
                  </interconnect>
                </pb_type>
                <interconnect>
                  <direct name="a2a" input="divisible_mult_18x18.a" output="mult_18x18_slice.A_cfg">
                    <delay_constant max="2.03e-13" min="1.89e-13" in_port="divisible_mult_18x18.a" out_port="mult_18x18_slice.A_cfg"/>
                    <C_constant C="1.89e-13" in_port="divisible_mult_18x18.a" out_port="mult_18x18_slice.A_cfg"/>
                  </direct>
                  <direct name="b2b" input="divisible_mult_18x18.b" output="mult_18x18_slice.B_cfg">
                    <delay_constant max="2.03e-13" min="1.89e-13" in_port="divisible_mult_18x18.b" out_port="mult_18x18_slice.B_cfg"/>
                    <C_constant C="1.89e-13" in_port="divisible_mult_18x18.b" out_port="mult_18x18_slice.B_cfg"/>
                  </direct>
                  <direct name="out2out" input="mult_18x18_slice.OUT_cfg" output="divisible_mult_18x18.out">
                    <delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_18x18_slice.OUT_cfg" out_port="divisible_mult_18x18.out"/>
                    <C_constant C="1.89e-13" in_port="mult_18x18_slice.OUT_cfg" out_port="divisible_mult_18x18.out"/>
                  </direct>
                </interconnect>
              </mode>
            </pb_type>
            <interconnect>
              <direct name="a2a" input="mult_36.a" output="divisible_mult_18x18[1:0].a">
                <delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_36.a" out_port="divisible_mult_18x18[1:0].a"/>
                <C_constant C="1.89e-13" in_port="mult_36.a" out_port="divisible_mult_18x18[1:0].a"/>
              </direct>
              <direct name="b2b" input="mult_36.b" output="divisible_mult_18x18[1:0].a">
                <delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_36.b" out_port="divisible_mult_18x18[1:0].a"/>
                <C_constant C="1.89e-13" in_port="mult_36.b" out_port="divisible_mult_18x18[1:0].a"/>
              </direct>
              <direct name="out2out" input="divisible_mult_18x18[1:0].out" output="mult_36.out">
                <delay_constant max="2.03e-13" min="1.89e-13" in_port="divisible_mult_18x18[1:0].out" out_port ="mult_36.out"/>
                <C_constant C="1.89e-13" in_port="divisible_mult_18x18[1:0].out" out_port="mult_36.out"/>
              </direct>
            </interconnect>
          </mode>

          <mode name="mult_36x36">
            <pb_type name="mult_36x36_slice" num_pb="1">
              <input name="A_cfg" num_pins="36"/>
              <input name="B_cfg" num_pins="36"/>
              <output name="OUT_cfg" num_pins="72"/>

              <pb_type name="mult_36x36" blif_model=".subckt multiply" num_pb="1" area="4000">
                <input name="a" num_pins="36"/>
                <input name="b" num_pins="36"/>
                <output name="out" num_pins="72"/>
                <delay_constant max="2.03e-13" min="1.89e-13" in_port="{a b}" out_port="out"/>
              </pb_type>

              <interconnect>
                <direct name="a2a" input="mult_36x36_slice.A_cfg" output="mult_36x36.a">
                  <delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_36x36_slice.A_cfg" out_port="mult_36x36.a"/>
                  <C_constant C="1.89e-13" in_port="mult_36x36_slice.A_cfg" out_port="mult_36x36.a"/>
                </direct>
                <direct name="b2b" input="mult_36x36_slice.B_cfg" output="mult_36x36.b">
                  <delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_36x36_slice.B_cfg" out_port="mult_36x36.b"/>
                  <C_constant C="1.89e-13" in_port="mult_36x36_slice.B_cfg" out_port="mult_36x36.b"/>
                </direct>
                <direct name="out2out" input="mult_36x36.out" output="mult_36x36_slice.OUT_cfg">
                  <delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_36x36.out" out_port="mult_36x36_slice.OUT_cfg"/>
                  <C_constant C="1.89e-13" in_port="mult_36x36.out" out_port="mult_36x36_slice.OUT_cfg"/>
                </direct>
              </interconnect>
            </pb_type>
            <interconnect>
              <direct name="a2a" input="mult_36.a" output="mult_36x36_slice.A_cfg">
                <delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_36.a" out_port="mult_36x36_slice.A_cfg"/>
                <C_constant C="1.89e-13" in_port="mult_36.a" out_port="mult_36x36_slice.A_cfg"/>
              </direct>
              <direct name="b2b" input="mult_36.b" output="mult_36x36_slice.B_cfg">
                <delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_36.b" out_port="mult_36x36_slice.B_cfg"/>
                <C_constant C="1.89e-13" in_port="mult_36.b" out_port="mult_36x36_slice.B_cfg"/>
              </direct>
              <direct name="out2out" input="mult_36x36_slice.OUT_cfg" output="mult_36.out">
                <delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_36x36_slice.OUT_cfg" out_port="mult_36.out"/>
                <C_constant C="1.89e-13" in_port="mult_36x36_slice.OUT_cfg" out_port="mult_36.out"/>
              </direct>
            </interconnect>
          </mode>


        <fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.125"/>
        <pinlocations pattern="spread"/>

        <gridlocations>
          <loc type="col" start="4" repeat="5" priority="2"/>
        </gridlocations>
      </pb_type>
    </complexblocklist>
  </architecture>