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foss-fpga-tools / third_party / vtr-verilog-to-routing / 954be24355ace41670a508749ecb955c19f86471 / . / vtr_flow / arch / timing
tree: 67c1a03e7c1de5d9a22726d19a1fcf668af9d9b0 [path history] [tgz]
  1. fixed_size/
  2. fraclut_carrychain/
  3. EArch.xml
  4. hard_fpu_arch_timing.xml
  5. k4_N4_90nm.xml
  6. k4_N8_legacy_45nm.xml
  7. k6_frac_N10_40nm.xml
  8. k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml
  9. k6_frac_N10_frac_chain_mem32K_40nm.xml
  10. k6_frac_N10_mem32K_40nm.xml
  11. k6_N10_40nm.xml
  12. k6_N10_gate_boost_0.2V_22nm.xml
  13. k6_N10_legacy_45nm.xml
  14. k6_N10_mem32K_40nm.xml
  15. k6_N10_ripple_chain_gate_boost_0.2V_22nm.xml
  16. k6_N10_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml
  17. k6_N8_gate_boost_0.2V_22nm.xml
  18. k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml
  19. k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml
  20. k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml
  21. k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml
  22. soft_fpu_arch_timing.xml
  23. soft_fpu_arch_timing_chain.xml