fix bm tool and fix clock input for always blocks
diff --git a/ODIN_II/SRC/ast_util.cpp b/ODIN_II/SRC/ast_util.cpp
index 12a0659..0cf3142 100644
--- a/ODIN_II/SRC/ast_util.cpp
+++ b/ODIN_II/SRC/ast_util.cpp
@@ -467,11 +467,11 @@
rnode[2] = resolve_node(NULL, instance_name_prefix, ((ast_node_t*)local_symbol_table_sc->data[sc_spot])->children[2]);
oassert(rnode[1]->type == NUMBERS && rnode[2]->type == NUMBERS);
- ///TODO WHats this?? comapreo bit string but usesd value ??? value is honestly not the right thing to look for...
+ ///TODO WHats this?? compareo bit string but uses value ??? value is honestly not the right thing to look for...
// we should restrict ODIN to use binary representation only for easier support of 'x' and 'z' value..
// or at least it's the only thing that makes sense.
- // also this gives us the ability to write our own math class for binary and ave better control of what is happening and better sense of it TO.
- // this causes bugs.. theres a patchy workaround put in bit string but we need a better permannet fix.
+ // also this gives us the ability to write our own math class for binary and ave better control of what is happening and better sense of it.
+ // this causes bugs.. theres a patchy workaround, put in bit string but we need a better permanent fix.
for (j = rnode[1]->types.number.value - rnode[2]->types.number.value; j >= 0; j--)
{
concat_top->types.concat.num_bit_strings ++;
@@ -915,7 +915,7 @@
*--------------------------------------------------------------------------*/
/**
* Recursively resolves an IDENTIFIER to a parameter into its actual value,
- * by looking it up in the global_param_table_sc
+ * by looking it up in the local_param_table_sc
* Also try and fold any BINARY_OPERATIONs now that an IDENTIFIER has been
* resolved
*/
@@ -924,6 +924,7 @@
{
long sc_spot = -1;
+ // Not sure this should even be used.
if(local_param_table_sc == NULL
&& module_name != NULL)
{
@@ -997,7 +998,7 @@
*--------------------------------------------------------------------------*/
/**
* Recursively resolves an IDENTIFIER to a parameter into its actual value,
- * by looking it up in the global_param_table_sc
+ * by looking it up in the local_param_table_sc
* Also try and fold any BINARY_OPERATIONs now that an IDENTIFIER has been
* resolved
*/
diff --git a/ODIN_II/SRC/enum_str.cpp b/ODIN_II/SRC/enum_str.cpp
index d9ad732..7834365 100644
--- a/ODIN_II/SRC/enum_str.cpp
+++ b/ODIN_II/SRC/enum_str.cpp
@@ -1,5 +1,10 @@
#include "odin_types.h"
+const char *file_extension_supported_STR[] =
+{
+ ".v"
+};
+
const char *signedness_STR[] =
{
"SIGNED",
diff --git a/ODIN_II/SRC/include/odin_types.h b/ODIN_II/SRC/include/odin_types.h
index 7dfa3f2..fc44b79 100644
--- a/ODIN_II/SRC/include/odin_types.h
+++ b/ODIN_II/SRC/include/odin_types.h
@@ -169,6 +169,8 @@
/**
* defined in enum_str.cpp
*/
+extern const char *file_extension_supported_STR[];
+
extern const char *ZERO_GND_ZERO;
extern const char *ONE_VCC_CNS;
extern const char *ZERO_PAD_ZERO;
@@ -183,6 +185,12 @@
typedef enum
{
+ VERILOG,
+ file_extension_supported_END
+} file_extension_supported;
+
+typedef enum
+{
DEC = 10,
HEX = 16,
OCT = 8,
diff --git a/ODIN_II/SRC/include/odin_util.h b/ODIN_II/SRC/include/odin_util.h
index afa5a3f..9b55dcc 100644
--- a/ODIN_II/SRC/include/odin_util.h
+++ b/ODIN_II/SRC/include/odin_util.h
@@ -49,6 +49,8 @@
long shift_left_value_with_overflow_check(long input_value, long shift_by);
+std::string get_file_extension(std::string input_file);
+
const char *node_name_based_on_op(nnode_t *node);
const char *name_based_on_op(operation_list op);
diff --git a/ODIN_II/SRC/include/parse_making_ast.h b/ODIN_II/SRC/include/parse_making_ast.h
index a382f79..c82e4db 100644
--- a/ODIN_II/SRC/include/parse_making_ast.h
+++ b/ODIN_II/SRC/include/parse_making_ast.h
@@ -4,10 +4,12 @@
/* INITIALISATIONS */
void init_parser();
-void cleanup_parser();
+
void cleanup_hard_blocks();
+
void init_parser_for_file();
-void clean_up_parser_for_file();
+void cleanup_parser_for_file();
+
/* GENERAL PARSER NODES */
ast_node_t *newSymbolNode(char *id, int line_number);
@@ -76,7 +78,6 @@
ast_node_t *newFunction(ast_node_t *list_of_ports, ast_node_t *list_of_module_items, int line_number);
void next_module();
void next_function();
-void newConstant(char *id, ast_node_t *number, int line_number);
ast_node_t *newDefparam(ids id, ast_node_t *val, int line_number);
void next_parsed_verilog_file(ast_node_t *file_items_list);
diff --git a/ODIN_II/SRC/netlist_create_from_ast.cpp b/ODIN_II/SRC/netlist_create_from_ast.cpp
index 753245f..732785e 100644
--- a/ODIN_II/SRC/netlist_create_from_ast.cpp
+++ b/ODIN_II/SRC/netlist_create_from_ast.cpp
@@ -57,33 +57,35 @@
#define INSTANTIATE_DRIVERS 1
#define ALIAS_INPUTS 2
-STRING_CACHE *output_nets_sc;
-STRING_CACHE *input_nets_sc;
+STRING_CACHE *output_nets_sc = NULL;
+STRING_CACHE *input_nets_sc = NULL;
-STRING_CACHE *local_symbol_table_sc;
-STRING_CACHE *function_local_symbol_table_sc;
-STRING_CACHE *global_param_table_sc;
-ast_node_t** local_symbol_table;
-ast_node_t** function_local_symbol_table;
-int num_local_symbol_table;
-int function_num_local_symbol_table;
-signal_list_t *local_clock_list;
-short local_clock_found;
-int local_clock_idx;
+STRING_CACHE *global_param_table_sc = NULL;
+
+STRING_CACHE *local_symbol_table_sc = NULL;
+ast_node_t** local_symbol_table = NULL;
+int num_local_symbol_table = 0;
+
+STRING_CACHE *function_local_symbol_table_sc = NULL;
+ast_node_t** function_local_symbol_table = NULL;
+int function_num_local_symbol_table = 0;
+
+signal_list_t *local_clock_list = NULL;
+int local_clock_idx = -1;
/* CONSTANT NET ELEMENTS */
-char *one_string;
-char *zero_string;
-char *pad_string;
+char *one_string = NULL;
+char *zero_string = NULL;
+char *pad_string = NULL;
-ast_node_t *top_module;
+ast_node_t *top_module = NULL;
-netlist_t *verilog_netlist;
+netlist_t *verilog_netlist = NULL;
int netlist_create_line_number = -2;
-circuit_type_e type_of_circuit;
-edge_type_e circuit_edge;
+circuit_type_e type_of_circuit = COMBINATIONAL;
+edge_type_e circuit_edge = UNDEFINED_SENSITIVITY;
/* PROTOTYPES */
void create_param_table_for_module(ast_node_t* parent_parameter_list, ast_node_t *module_items, char *module_name, char *parent_module);
@@ -147,6 +149,11 @@
char *make_chunk_size_name(char *instance_name_prefix, char *array_name);
ast_node_t *get_chunk_size_node(char *instance_name_prefix, char *array_name);
+void cleanup_function_local_symbol();
+void init_function_local_symbol();
+void cleanup_local_symbol();
+void init_local_symbol();
+
/*----------------------------------------------------------------------------
* (function: create_param_table_for_module)
*--------------------------------------------------------------------------*/
@@ -374,7 +381,67 @@
}
}
+void cleanup_function_local_symbol()
+{
+ if(function_local_symbol_table_sc)
+ {
+ function_local_symbol_table_sc = sc_free_string_cache(function_local_symbol_table_sc);
+ }
+ if(function_local_symbol_table)
+ {
+ vtr::free(function_local_symbol_table);
+ function_local_symbol_table = NULL;
+ }
+
+ function_num_local_symbol_table = 0;
+}
+
+void init_function_local_symbol()
+{
+ // make sure we cleanup first
+ cleanup_function_local_symbol();
+ function_local_symbol_table_sc = sc_new_string_cache();
+}
+
+void cleanup_local_symbol()
+{
+ if(local_symbol_table_sc)
+ {
+ local_symbol_table_sc = sc_free_string_cache(local_symbol_table_sc);
+ }
+
+ if(local_symbol_table)
+ {
+ vtr::free(local_symbol_table);
+ local_symbol_table = NULL;
+ }
+
+ num_local_symbol_table = 0;
+}
+
+void init_local_symbol()
+{
+ // make sure we cleanup first
+ cleanup_local_symbol();
+ local_symbol_table_sc = sc_new_string_cache();
+}
+
+void cleanup_local_clock_list()
+{
+ if(local_clock_list)
+ {
+ free_signal_list(local_clock_list);
+ local_clock_list = NULL;
+ }
+
+ local_clock_idx = -1;
+}
+
+void init_local_clock_list()
+{
+ cleanup_local_clock_list();
+}
/*---------------------------------------------------------------------------------------------
* (function: create_netlist)
@@ -758,14 +825,10 @@
case MODULE_ITEMS:
/* items include: wire, reg, input, outputs, assign, gate, module_instance, always */
-
/* make the symbol table */
- local_symbol_table_sc = sc_new_string_cache();
- local_symbol_table = NULL;
- num_local_symbol_table = 0;
- create_symbol_table_for_module(node, instance_name_prefix);
- local_clock_found = FALSE;
+ init_local_symbol();
+ create_symbol_table_for_module(node, instance_name_prefix);
/* check for initial register values set in initial block.*/
for (i = 0; i < node->num_children; i++)
{
@@ -848,11 +911,8 @@
case FUNCTION_ITEMS:
/* items include: wire, reg, input, outputs, assign, gate, always */
/* make the symbol table */
- function_local_symbol_table_sc = sc_new_string_cache();
- function_local_symbol_table = NULL;
- function_num_local_symbol_table = 0;
+ init_function_local_symbol();
create_symbol_table_for_function(node, instance_name_prefix);
- local_clock_found = FALSE;
/* create all the driven nets based on the "reg" registers */
create_all_driver_nets_in_this_function(instance_name_prefix);
@@ -991,20 +1051,14 @@
}
/* free the symbol table for this module since we're done processing */
- local_symbol_table_sc = sc_free_string_cache(local_symbol_table_sc);
- vtr::free(local_symbol_table);
- local_symbol_table_sc = NULL;
- num_local_symbol_table = 0;
+ cleanup_local_symbol();
break;
}
case FUNCTION_ITEMS:
{
/* free the symbol table for this module since we're done processing */
- function_local_symbol_table_sc = sc_free_string_cache(function_local_symbol_table_sc);
- vtr::free(function_local_symbol_table);
- function_local_symbol_table = NULL;
- function_num_local_symbol_table = 0;
+ cleanup_function_local_symbol();
}
break;
case FUNCTION_INSTANCE:
@@ -1049,8 +1103,7 @@
}
- if (local_clock_list)
- free_signal_list(local_clock_list);
+ cleanup_local_clock_list();
break;
case BINARY_OPERATION:
@@ -1531,7 +1584,8 @@
temp_string = make_chunk_size_name(instance_name_prefix, name);
- if ((sc_spot = sc_add_string(local_param_table_sc, temp_string)) == -1)
+ sc_spot = sc_add_string(local_param_table_sc, temp_string);
+ if (local_param_table_sc->data[sc_spot] != NULL)
error_message(NETLIST_ERROR, var_declare->children[0]->line_number, var_declare->children[0]->file_number,
"%s: name conflicts with Odin internal reference\n", temp_string);
@@ -1624,6 +1678,7 @@
output_nets_sc->data[sc_spot] = (void*)new_net;
new_net->name = temp_string;
+ // TODO: What is this ?
/* Assign initial value to this net if it exists */
if(var_declare->types.variable.is_initialized){
new_net->has_initial_value = TRUE;
@@ -3695,59 +3750,77 @@
npin_t **list_dependence_pin = (npin_t **)vtr::calloc(assignment->count,sizeof(npin_t *));
ids *list_dependence_type = (ids *)vtr::calloc(assignment->count,sizeof(ids));
/* figure out which one is the clock */
- if (local_clock_found == FALSE)
+ if (local_clock_idx < 0)
{
- int i;
- for (i = 0; i < potential_clocks->count; i++)
+ if(potential_clocks->count == 1)
{
- nnet_t *temp_net;
- /* searching for the clock with no net */
- long sc_spot = sc_lookup_string(output_nets_sc, potential_clocks->pins[i]->name);
- if (sc_spot == -1)
+ /* If this element is the only item in the sensitivity list then its the clock */
+ local_clock_idx = 0;
+ }
+ else
+ {
+ int i;
+ for (i = 0; i < potential_clocks->count; i++)
{
- sc_spot = sc_lookup_string(input_nets_sc, potential_clocks->pins[i]->name);
+ nnet_t *temp_net;
+ /* searching for the clock with no net */
+ long sc_spot = sc_lookup_string(output_nets_sc, potential_clocks->pins[i]->name);
if (sc_spot == -1)
{
- error_message(NETLIST_ERROR, always_node->line_number, always_node->file_number,
- "Sensitivity list element (%s) is not a driver or net ... must be\n", potential_clocks->pins[i]->name);
+ sc_spot = sc_lookup_string(input_nets_sc, potential_clocks->pins[i]->name);
+ if (sc_spot == -1)
+ {
+ error_message(NETLIST_ERROR, always_node->line_number, always_node->file_number,
+ "Sensitivity list element (%s) is not a driver or net ... must be\n", potential_clocks->pins[i]->name);
+ }
+ temp_net = (nnet_t*)input_nets_sc->data[sc_spot];
}
- temp_net = (nnet_t*)input_nets_sc->data[sc_spot];
- }
- else
- {
- temp_net = (nnet_t*)output_nets_sc->data[sc_spot];
- }
+ else
+ {
+ temp_net = (nnet_t*)output_nets_sc->data[sc_spot];
+ }
- if ((((temp_net->num_fanout_pins == 1) && (temp_net->fanout_pins[0]->node == NULL)) || (temp_net->num_fanout_pins == 0))
- && (local_clock_found == TRUE))
- {
- error_message(NETLIST_ERROR, always_node->line_number, always_node->file_number,
- "Suspected second clock (%s). In a sequential sensitivity list, Odin expects the "
- "clock not to drive anything and any other signals in this list to drive stuff. "
- "For example, a reset in the sensitivy list has to be hooked up to something in the always block.\n",
- potential_clocks->pins[i]->name);
+ if (
+ (((temp_net->num_fanout_pins == 1) && (temp_net->fanout_pins[0]->node == NULL))
+ || (temp_net->num_fanout_pins == 0))
+ && (local_clock_idx >= 0))
+ {
+ error_message(NETLIST_ERROR, always_node->line_number, always_node->file_number,
+ "Suspected second clock (%s). In a sequential sensitivity list, Odin expects the "
+ "clock not to drive anything and any other signals in this list to drive stuff. "
+ "For example, a reset in the sensitivy list has to be hooked up to something in the always block.\n",
+ potential_clocks->pins[i]->name);
+ }
+ else if (temp_net->num_fanout_pins == 0)
+ {
+ /* If this element is in the sensitivity list and doesn't drive anything it's the clock */
+ local_clock_idx = i;
+ }
+ else if ((temp_net->num_fanout_pins == 1) && (temp_net->fanout_pins[0]->node == NULL))
+ {
+ /* If this element is in the sensitivity list and doesn't drive anything it's the clock */
+ local_clock_idx = i;
+ }
}
- else if (temp_net->num_fanout_pins == 0)
- {
- /* If this element is in the sensitivity list and doesn't drive anything it's the clock */
- local_clock_found = TRUE;
- local_clock_idx = i;
- }
- else if ((temp_net->num_fanout_pins == 1) && (temp_net->fanout_pins[0]->node == NULL))
- {
- /* If this element is in the sensitivity list and doesn't drive anything it's the clock */
- local_clock_found = TRUE;
- local_clock_idx = i;
- }
-
}
}
- nnet_t *clock_net = potential_clocks->pins[local_clock_idx]->net;
+ npin_t *local_clock_pin = NULL;
+
+ if(local_clock_idx >= 0)
+ {
+ local_clock_pin = potential_clocks->pins[local_clock_idx];
+ }
+ else
+ {
+ error_message(NETLIST_ERROR, always_node->line_number, always_node->file_number,
+ "%s\n", "No clock found"
+ );
+ }
+
signal_list_t *memory_inputs = init_signal_list();
- char *ref_string;
int i, j, dependence_variable_position;
for (i = 0; i < assignment->count; i++)
{
@@ -3779,9 +3852,9 @@
/* HERE create the ff node and hookup everything */
nnode_t *ff_node = allocate_nnode();
ff_node->related_ast_node = always_node;
-
ff_node->type = FF_NODE;
- ff_node->edge_type = potential_clocks->pins[local_clock_idx]->sensitivity;
+ ff_node->edge_type = local_clock_pin->sensitivity;
+
/* create the unique name for this gate */
//ff_node->name = node_name(ff_node, instance_name_prefix);
/* Name the flipflop based on the name of its output pin */
@@ -3790,28 +3863,23 @@
odin_sprintf(ff_node->name, "%s_%s", pin->name, ff_base_name);
/* Copy over the initial value information from the net */
- ref_string = (char *)vtr::calloc(strlen(pin->name)+100,sizeof(char));
- strcpy(ref_string,pin->name);
- strcat(ref_string,"_latch_initial_value");
+ std::string ref_string(pin->name);
+ ref_string += "_latch_initial_value";
- sc_spot = sc_lookup_string(local_symbol_table_sc, ref_string);
- if(sc_spot != -1){
+ sc_spot = sc_add_string(local_symbol_table_sc, ref_string.c_str());
- ff_node->has_initial_value = 1;
- // TODO: ?? what is this?
- ff_node->initial_value = ((char *)(local_symbol_table_sc->data[sc_spot]))[0];
- }
- else{
-
- sc_spot = sc_add_string(local_symbol_table_sc, ref_string);
+ if(local_symbol_table_sc->data[sc_spot] == NULL)
+ {
local_symbol_table_sc->data[sc_spot] = (void *)ff_node;
-
ff_node->has_initial_value = net->has_initial_value;
ff_node->initial_value = net->initial_value;
}
- /* free the reference string */
- vtr::free(ref_string);
-
+ else
+ {
+ nnode_t *parent_symbol_node = (nnode_t *)local_symbol_table_sc->data[sc_spot];
+ ff_node->has_initial_value = parent_symbol_node->has_initial_value;
+ ff_node->initial_value = parent_symbol_node->initial_value;
+ }
/* allocate the pins needed */
allocate_more_input_pins(ff_node, 2);
@@ -3824,7 +3892,7 @@
/* add the clock to the flip_flop */
/* add a fanout pin */
npin_t *fanout_pin_of_clock = allocate_npin();
- add_fanout_pin_to_net(clock_net, fanout_pin_of_clock);
+ add_fanout_pin_to_net(local_clock_pin->net, fanout_pin_of_clock);
add_input_pin_to_node(ff_node, fanout_pin_of_clock, 1);
/* hookup the driver pin (the in_1) to to this net (the lookup) */
@@ -3852,8 +3920,9 @@
npin_t *pin = assignment->pins[i];
dependence_variable_position = -1;
- if(pin->net->driver_pin){
- ref_string = pin->net->driver_pin->node->name;
+ if(pin->net->driver_pin)
+ {
+ char *ref_string = pin->net->driver_pin->node->name;
for(j = i-1; j >= 0; j--){
@@ -3894,7 +3963,7 @@
if (!memory->clock_added)
{
npin_t *clock_pin = allocate_npin();
- add_fanout_pin_to_net(clock_net, clock_pin);
+ add_fanout_pin_to_net(local_clock_pin->net, clock_pin);
signal_list_t *clock = init_signal_list();
add_pin_to_signal_list(clock, clock_pin);
add_input_port_to_implicit_memory(memory, clock, "clk");
diff --git a/ODIN_II/SRC/odin_ii.cpp b/ODIN_II/SRC/odin_ii.cpp
index dbbc899..e11969b 100644
--- a/ODIN_II/SRC/odin_ii.cpp
+++ b/ODIN_II/SRC/odin_ii.cpp
@@ -104,6 +104,7 @@
read_soft_def_file(hard_adders);
global_param_table_sc = sc_new_string_cache();
+ module_names_to_idx = sc_new_string_cache();
/* parse to abstract syntax tree */
printf("Parser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)\n");
@@ -171,9 +172,6 @@
/* Find any unused logic in the netlist and remove it */
remove_unused_logic(verilog_netlist);
- sc_free_string_cache(global_param_table_sc);
-
-
/**
* point for outputs. This includes soft and hard mapping all structures to the
* target format. Some of these could be considred optimizations
@@ -183,6 +181,10 @@
output_blif(output_file, verilog_netlist);
+
+ global_param_table_sc = sc_free_string_cache(global_param_table_sc);
+ module_names_to_idx = sc_free_string_cache(module_names_to_idx);
+
elaboration_time = wall_time() - elaboration_time;
printf("Successful High-level synthesis by Odin\n\tBlif file available at %s\n\tRan in ",output_file);
diff --git a/ODIN_II/SRC/odin_util.cpp b/ODIN_II/SRC/odin_util.cpp
index 790aa89..8ece26f 100644
--- a/ODIN_II/SRC/odin_util.cpp
+++ b/ODIN_II/SRC/odin_util.cpp
@@ -53,6 +53,19 @@
return input_value << shift_by;
}
+std::string get_file_extension(std::string input_file)
+{
+ auto dot_location = input_file.find_last_of('.');
+ if( dot_location != std::string::npos )
+ {
+ return input_file.substr(dot_location);
+ }
+ else
+ {
+ return "";
+ }
+}
+
/*---------------------------------------------------------------------------------------------
* (function: node_name_based_on_op)
* Get the string version of a node
diff --git a/ODIN_II/SRC/parse_making_ast.cpp b/ODIN_II/SRC/parse_making_ast.cpp
index a0ced39..9f37b74 100644
--- a/ODIN_II/SRC/parse_making_ast.cpp
+++ b/ODIN_II/SRC/parse_making_ast.cpp
@@ -40,7 +40,6 @@
extern int yylineno;
-STRING_CACHE *defines_for_file_sc;
//for module
STRING_CACHE **defines_for_module_sc;
STRING_CACHE *modules_inputs_sc;
@@ -107,6 +106,32 @@
rewind(yyin);
}
+static void assert_supported_file_extension(std::string input_file, int file_number)
+{
+ bool supported = false;
+ std::string extension = get_file_extension(input_file);
+ for(int i = 0; i< file_extension_supported_END && ! supported; i++)
+ {
+ supported = (extension == std::string(file_extension_supported_STR[i]) );
+ }
+
+ if(! supported)
+ {
+ std::string supported_extension_list = "";
+ for(int i=0; i<file_extension_supported_END; i++)
+ {
+ supported_extension_list += " ";
+ supported_extension_list += file_extension_supported_STR[i];
+ }
+
+ error_message(ARG_ERROR, -1, file_number,
+ "File (%s) has an unsupported extension (%s), Odin only support { %s }",
+ input_file,
+ extension,
+ supported_extension_list.c_str()
+ );
+ }
+}
/*---------------------------------------------------------------------------------------------
* (function: parse_to_ast)
@@ -121,27 +146,21 @@
/* initialize the parser */
init_parser();
-
+ init_veri_preproc();
+
/* read all the files in the configuration file */
current_parse_file =0;
while (current_parse_file < configuration.list_of_file_names.size())
{
+ assert_supported_file_extension(configuration.list_of_file_names[current_parse_file], current_parse_file);
+
yyin = fopen(configuration.list_of_file_names[current_parse_file].c_str(), "r");
if (yyin == NULL)
{
error_message(ARG_ERROR, -1, -1, "cannot open file: %s\n", configuration.list_of_file_names[current_parse_file].c_str());
}
- /*Testing preprocessor - Paddy O'Brien*/
-
- /**
- * TODO shouldnt we push defines throughout multiple files ? just like includes?
- * Verify documentation for this
- */
-
- init_veri_preproc();
yyin = veri_preproc(yyin);
- cleanup_veri_preproc();
/* write out the pre-processed file */
if (configuration.output_preproc_source)
@@ -158,11 +177,9 @@
fclose(yyin);
current_parse_file++;
}
- /* cleanup the defines hash */
- sc_free_string_cache(defines_for_file_sc);
/* clean up all the structures in the parser */
- cleanup_parser();
+ cleanup_veri_preproc();
/* for error messages - this is in case we use any of the parser functions after parsing (i.e. create_case_control_signals()) */
current_parse_file = -1;
@@ -210,7 +227,6 @@
*-------------------------------------------------------------------------------------------*/
void init_parser()
{
- defines_for_file_sc = sc_new_string_cache();
defines_for_module_sc = NULL;
@@ -221,7 +237,6 @@
num_functions = 0;
ast_modules = NULL;
ast_functions = NULL;
- module_names_to_idx = sc_new_string_cache();
module_instantiations_instance = NULL;
function_instantiations_instance = NULL;
module_variables_not_defined = NULL;
@@ -276,9 +291,13 @@
/*---------------------------------------------------------------------------------------------
* (function: clean_up_parser_for_file)
*-------------------------------------------------------------------------------------------*/
-void clean_up_parser_for_file()
+void cleanup_parser_for_file()
{
-
+ /* create string caches to hookup PORTS with INPUT and OUTPUTs. This is made per module and will be cleaned and remade at next_module */
+ modules_inputs_sc = sc_free_string_cache(modules_inputs_sc);
+ modules_outputs_sc = sc_free_string_cache(modules_outputs_sc);
+ functions_inputs_sc = sc_free_string_cache(functions_inputs_sc);
+ functions_outputs_sc = sc_free_string_cache(functions_outputs_sc);
}
/*---------------------------------------------------------------------------------------------
@@ -311,35 +330,7 @@
*-------------------------------------------------------------------------------------------*/
ast_node_t *newSymbolNode(char *id, int line_number)
{
- long sc_spot;
- ast_node_t *current_node;
-
- if(id != NULL) {
- if (id[0] == '`')
- {
- /* IF - this is a define replace with number constant */
- /* def_reduct */
-
- /* get the define symbol from the string cache */
- if ((sc_spot = sc_lookup_string(defines_for_file_sc, (id+1))) == -1)
- {
- error_message(PARSE_ERROR, line_number, current_parse_file, "Define \"%s\" used but not declared\n", id);
- }
-
- /* return the number node */
- return (ast_node_t*)defines_for_file_sc->data[sc_spot];
- }
- else
- {
- /* create node */
- current_node = create_tree_node_id(id, line_number, current_parse_file);
- }
- }
- else {
- current_node = create_tree_node_id(id, line_number, current_parse_file);
- }
-
- return current_node;
+ return create_tree_node_id(id, line_number, current_parse_file);
}
@@ -1713,8 +1704,8 @@
/* clean up */
vtr::free(module_variables_not_defined);
-
- if ((sc_spot = sc_add_string(module_names_to_idx, module_name)) == -1)
+ sc_spot = sc_add_string(module_names_to_idx, module_name);
+ if (module_names_to_idx->data[sc_spot] != NULL)
{
error_message(PARSE_ERROR, line_number, current_parse_file, "module names with the same name -> %s\n", module_name);
}
@@ -1802,8 +1793,8 @@
/* record this module in the list of modules (for evaluation later in terms of just nodes) */
ast_modules = (ast_node_t **)vtr::realloc(ast_modules, sizeof(ast_node_t*)*(num_modules+1));
ast_modules[num_modules] = new_node;
-
- if ((sc_spot = sc_add_string(module_names_to_idx, function_name)) == -1)
+ sc_spot = sc_add_string(module_names_to_idx, function_name);
+ if (module_names_to_idx->data[sc_spot] != NULL)
{
error_message(PARSE_ERROR, line_number, current_parse_file, "module names with the same name -> %s\n", function_name);
}
@@ -1941,24 +1932,6 @@
return NULL;
}
-/*--------------------------------------------------------------------------
- * (function: newConstant)
- *------------------------------------------------------------------------*/
-void newConstant(char *id, ast_node_t *number_node, int line_number)
-{
- long sc_spot;
- /* add the define character string to the parser and maintain the number around */
- /* def_reduct */
- if ((sc_spot = sc_add_string(defines_for_file_sc, id)) == -1)
- {
- error_message(PARSE_ERROR, current_parse_file, line_number, "define with same name (%s) on line %d\n", id, ((ast_node_t*)(defines_for_file_sc->data[sc_spot]))->line_number);
- }
- /* store the data */
- defines_for_file_sc->data[sc_spot] = (void*)number_node;
- /* mark node as shared */
- number_node->shared_node = TRUE;
-}
-
/* --------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
diff --git a/ODIN_II/regression_test/benchmark/arch/both_ram.v b/ODIN_II/regression_test/benchmark/arch/both_ram.v
index abdc9f1..64f88f3 100644
--- a/ODIN_II/regression_test/benchmark/arch/both_ram.v
+++ b/ODIN_II/regression_test/benchmark/arch/both_ram.v
@@ -17,6 +17,10 @@
dpram2_out2
);
+wafq
+
+;;;
+
// SIGNAL DECLARATIONS
input clock;
diff --git a/ODIN_II/verify_odin.sh b/ODIN_II/verify_odin.sh
index a18e3b8..dd5f7d2 100755
--- a/ODIN_II/verify_odin.sh
+++ b/ODIN_II/verify_odin.sh
@@ -60,6 +60,9 @@
# Exit Functions
function exit_program() {
+ FAIL_COUNT=$(wc -l ${NEW_RUN_DIR}/test_failures.log | cut -d ' ' -f 1)
+ FAILURE=$(( ${FAIL_COUNT} ))
+
if [ "_${FAILURE}" != "_0" ]
then
echo "Failed ${FAILURE} benchmarks"
@@ -213,29 +216,46 @@
}
+function disable_failed() {
+ failed_dir=$1
+ log_file="${failed_dir}.log"
+
+ if [ -e ${log_file} ]
+ then
+
+ for failed_benchmark in $(cat ${log_file})
+ do
+ THIS_BM="${NEW_RUN_DIR}/${failed_benchmark}/sim_param"
+ if [ -f ${THIS_BM} ]
+ then
+ mv ${THIS_BM} ${THIS_BM}_disabled
+ fi
+ done
+ fi
+}
+
function mv_failed() {
failed_dir=$1
log_file="${failed_dir}.log"
if [ -e ${log_file} ]
then
+ echo "Linking failed benchmark in failures $(basename ${failed_dir})"
+
for failed_benchmark in $(cat ${log_file})
do
- if [ ! -e ${target_dir}/${target_link} ]
+ target="${failed_dir}/${failed_benchmark}"
+ target_dir=$(dirname ${target})
+ target_link=$(basename ${target})
+
+ mkdir -p ${target_dir}
+
+ if [ ! -L "${target}" ]
then
- target_dir=$(dirname ${failed_dir}/${failed_benchmark})
- target_link=$(basename ${failed_benchmark})
-
- mkdir -p ${target_dir}
- echo "Linking failed benchmark ${failed_benchmark} -> in failures ${target_link}"
-
-
- ln -s ${NEW_RUN_DIR}/${failed_benchmark} ${target_dir}/${target_link}
-
- FAILURE=$(( ${FAILURE} + 1 ))
+ ln -s ${NEW_RUN_DIR}/${failed_benchmark} ${target}
+ echo "${failed_benchmark}" >> ${NEW_RUN_DIR}/test_failures.log
fi
done
- cat ${log_file} >> ${NEW_RUN_DIR}/test_failures.log
fi
}
@@ -667,18 +687,26 @@
done
#synthesize the circuits
- if [ "${_SYNTHESIS}" == "on" ]
+ SYNTH_LIST=$(find ${NEW_RUN_DIR}/${bench_type}/ -name cmd_param)
+ if [ "${_SYNTHESIS}" == "on" ] && [ "_${SYNTH_LIST}" != "_" ]
then
echo " ========= Synthesizing Circuits"
find ${NEW_RUN_DIR}/${bench_type}/ -name cmd_param | xargs -n1 -P$threads -I test_cmd ${SHELL} -c '$(cat test_cmd)'
+ # disable simulations on failure
+ disable_failed ${global_synthesis_failure}
+
mv_failed ${global_synthesis_failure}
fi
- if [ "${_SIMULATE}" == "on" ]
+ SIM_LIST=$(find ${NEW_RUN_DIR}/${bench_type}/ -name sim_param)
+ if [ "${_SIMULATE}" == "on" ] && [ "_${SIM_LIST}" != "_" ]
then
+ echo " ========= Simulating Circuits"
+
for i in $(seq 1 1 ${_SIM_COUNT}); do
+ echo " Itteration: ${i}"
+
#run the simulation
- echo " ========= Simulating Circuits"
find ${NEW_RUN_DIR}/${bench_type}/ -name sim_param | xargs -n1 -P$threads -I sim_cmd ${SHELL} -c '$(cat sim_cmd)'
# move the log
@@ -687,6 +715,8 @@
mv ${sim_log} "${sim_log}_${i}"
done
+ disable_failed ${global_simulation_failure}
+
done
mkdir -p ${NEW_RUN_DIR}/${bench_type}/vectors
