)]}'
{
  "id": "0e09f4092dbdfef9ab160a624493d4892570f3f5",
  "repo": "third_party/vtr-verilog-to-routing",
  "revision": "e3ba50265c283643ce235ed2fba66f678da0124a",
  "path": "vpr/src/base/clock_modeling.cpp"
}