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foss-fpga-tools / third_party / vtr-verilog-to-routing / e826f57b27df591f83a2845a638636875713f938^! / .
commite826f57b27df591f83a2845a638636875713f938[log] [tgz]
authorkmurray <k.murray@utoronto.ca>Wed Nov 20 15:16:05 2019 -0500
committerkmurray <k.murray@utoronto.ca>Wed Nov 20 15:16:05 2019 -0500
tree46809059131ae3d7b2b5f42e244239f22767906a
parent68877d9a6593ab2daedeb1a5c2c9aaab39f3f8d8 [diff]
infra: Update Travis Status Icon URL

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 # Verilog to Routing (VTR)
-[![Build Status](https://travis-ci.org/verilog-to-routing/vtr-verilog-to-routing.svg?branch=master)](https://travis-ci.org/verilog-to-routing/vtr-verilog-to-routing) [![Documentation Status](https://readthedocs.org/projects/vtr/badge/?version=latest)](http://docs.verilogtorouting.org/en/latest/?badge=latest)
+[![Build Status](https://travis-ci.com/verilog-to-routing/vtr-verilog-to-routing.svg?branch=master)](https://travis-ci.org/verilog-to-routing/vtr-verilog-to-routing) [![Documentation Status](https://readthedocs.org/projects/vtr/badge/?version=latest)](http://docs.verilogtorouting.org/en/latest/?badge=latest)
 
 ## Introduction
 The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development.