diff --git a/doc/src/vpr/timing_constraints.rst b/doc/src/vpr/timing_constraints.rst
index 4f3c7d7..fe57265 100644
--- a/doc/src/vpr/timing_constraints.rst
+++ b/doc/src/vpr/timing_constraints.rst
@@ -6,6 +6,7 @@
 The subset of SDC supported by VPR is described in :ref:`sdc_commands`.
 Additional SDC examples are shown in :ref:`sdc_examples`.
 
+.. seealso:: The :ref:`Primitive Timing Modelling Tutorial <arch_model_timing_tutorial>` which covers how to describe the timing characteristics of architecture primitives.
 
 .. _default_timing_constraints: