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foss-fpga-tools / third_party / vtr-verilog-to-routing / refs/heads/clock_modeling / . / vtr_flow / benchmarks / microbenchmarks
tree: 7f77f0d7c00f0276b27ad7e57c5187383925d2af [path history] [tgz]
  1. always_false.blif
  2. always_true.blif
  3. and.blif
  4. and_latch.blif
  5. const_false.blif
  6. const_true.blif
  7. constant_outputs_only.blif
  8. d_flip_flop.v
  9. false_path_mux.blif
  10. mult_2x2.blif
  11. mult_3x3.blif
  12. mult_3x4.blif
  13. mult_4x4.blif
  14. mult_5x5.blif
  15. mult_5x6.blif
  16. multiconnected_lut.blif
  17. multiconnected_lut2.blif
  18. rca_1bit.blif
  19. rca_2bit.blif
  20. rca_3bit.blif
  21. rca_4bit.blif
  22. rca_5bit.blif