diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/config.txt
new file mode 100644
index 0000000..3b2b2f4
--- /dev/null
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/config.txt
@@ -0,0 +1,36 @@
+##############################################
+# Configuration file for running experiments
+##############################################
+
+# Path to directory of circuits to use
+circuits_dir=benchmarks/
+
+# Path to directory of architectures to use
+archs_dir=arch/
+
+# Path to directory of SDC files to use
+sdc_dir=sdc
+
+# Add circuits to list to sweep
+circuit_list_add=verilog/mkPktMerge.v
+
+# Add architectures to list to sweep
+arch_list_add=timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml
+arch_list_add=timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml
+
+# Parse info and how to parse
+parse_file=vpr_clock_modeling.txt
+
+# How to parse QoR info
+qor_parse_file=qor_standard.txt
+
+# Pass requirements
+# A pass requirement to check that the number of routed nets
+# are equal can change if the circuit is synthesized
+# differently. At that point a new golden results file must
+# be created and checked to see that using the route option
+# increases the number of routed nets.
+pass_requirements_file=pass_requirements_clock_modeling.txt
+
+# Script parameters
+script_params_list_add= --clock_modeling dedicated_network
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt
new file mode 100644
index 0000000..2f2b4c8
--- /dev/null
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt
@@ -0,0 +1,3 @@
+arch                                                          	circuit             	script_params                            	vtr_flow_elapsed_time	error	odin_synth_time	max_odin_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_revision	vpr_status	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_time	placed_wirelength_est	place_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	crit_path_route_time	num_global_nets	num_routed_nets
+timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml          	verilog/mkPktMerge.v	common_--clock_modeling_dedicated_network	15.31                	     	0.27           	17264       	2        	0.20          	-1          	-1          	38808      	-1      	-1         	29     	311   	15          	0       	2794983     	success   	58388      	311               	156                	1019               	1160                 	1                 	959                 	511                   	28          	28           	784              	memory                   	auto       	0.66     	8880                 	1.68      	4.41469       	-3469.19            	-4.41469            	40            	15329            	21                                    	4.25198e+07           	9.78293e+06          	2.15488e+06                      	2748.57                             	8.99                     	14277                      	15                               	2423                       	2745                              	3123957                    	1155970                  	4.53868            	-4222.64 	-4.53868 	-289.158	-1.06119	2.69199e+06                 	3433.66                        	1.01                	15             	944            
+timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml	verilog/mkPktMerge.v	common_--clock_modeling_dedicated_network	14.68                	     	0.26           	17244       	2        	0.11          	-1          	-1          	38804      	-1      	-1         	29     	311   	15          	0       	2794983     	success   	56712      	311               	156                	1019               	1160                 	1                 	959                 	511                   	28          	28           	784              	memory                   	auto       	0.65     	9074                 	1.61      	4.47993       	-3873.73            	-4.47993            	40            	15165            	32                                    	4.25198e+07           	9.78293e+06          	2.18945e+06                      	2792.66                             	8.96                     	14287                      	14                               	2531                       	2886                              	3171344                    	1017880                  	5.0251             	-4259.91 	-5.0251  	-555.634	-2.3667 	2.74222e+06                 	3497.72                        	1.03                	15             	944