Google Git
Sign in
foss-fpga-tools / third_party / vtr-verilog-to-routing / refs/heads/hz_bfs_lookup / . / vtr_flow / sdc / samples
tree: bed6600c89d7805f27babd61e78ba10dc3236b54 [path history] [tgz]
  1. A.sdc
  2. B.sdc
  3. C.sdc
  4. combinational.blif
  5. combinational_default.sdc
  6. D.sdc
  7. E.sdc
  8. multiclock.blif
  9. multiclock_default.sdc
  10. singleclock.blif
  11. singleclock_default.sdc