)]}'
{
  "id": "8213e0b31856671071ff9355378cb7029b37d31b",
  "entries": [
    {
      "mode": 16384,
      "type": "tree",
      "id": "01218a2387c645487610c272159a3aa0121f6e66",
      "name": "FPGAPaper"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "80c26ca53a6c80bc68c21ea58fd7e38a63ae9831",
      "name": "fpga2014_interposer.pdf"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "eca7a108f6cf993656b595e4a4d2b5a8771b3170",
      "name": "fpga2014paper.pdf"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "7c8bae0d29d040956cbac3f370f66a9ffcb2104c",
      "name": "fpga2014paper.tex"
    }
  ]
}