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foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
bb5a5a809ec21879e4eefc197c134b11cd3ac80e
/
.
/
ODIN_II
/
SANDBOX
/
default_out.blif
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.
model third
.
inputs top
^
clock top
^
reset_n top
^
in
.
outputs top
^
out
.
names gnd
.
names hbpad
.
names vcc
1
.
latch top
^
in
top
^
FF_NODE
~
0
re top
^
clock
0
.
latch top
^
FF_NODE
~
0
top
^
FF_NODE
~
1
re top
^
clock
0
.
names top
^
FF_NODE
~
1
top
^
out
1
1
.
end
