made golden results incorrect such that it should fail
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt
index 8c1d73c..88dfd02 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt
@@ -1,5 +1,5 @@
arch circuit script_params vpr_revision vpr_status error num_pre_packed_nets num_pre_packed_blocks num_post_packed_nets num_post_packed_blocks device_width device_height num_clb num_io num_outputs num_memories num_mult placed_wirelength_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est num_global_nets num_routed_nets min_chan_width routed_wirelength min_chan_width_route_success_iteration crit_path_routed_wirelength crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile crit_path_routing_area_total crit_path_routing_area_per_tile odin_synth_time abc_synth_time abc_cec_time abc_sec_time ace_time pack_time place_time min_chan_width_route_time crit_path_route_time vtr_flow_elapsed_time max_vpr_mem max_odin_mem max_abc_mem
-timing/k6_N10_40nm.xml d_flip_flop.v common_--clock_modeling_method_ideal 7149779-dirty success 3 4 3 4 3 3 1 2 1 -1 -1 4 0.570641 -0.944653 -0.570641 1 2 2 3 2 3 2 0.576831 -1.04028 -0.576831 0 0 53894 53894 1165.58 129.509 1165.58 129.509 0.00 0.00 -1 -1 -1 0.01 0.00 0.00 0.00 0.17 10448 5188 32732
+timing/k6_N10_40nm.xml d_flip_flop.v common_--clock_modeling_method_ideal 7149779-dirty success 3 4 3 4 3 3 1 2 1 -1 -1 4 0.570641 -0.944653 -0.570641 5 2 2 3 2 3 2 0.576831 -1.04028 -0.576831 0 0 53894 53894 1165.58 129.509 1165.58 129.509 0.00 0.00 -1 -1 -1 0.01 0.00 0.00 0.00 0.17 10448 5188 32732
timing/k6_N10_40nm.xml d_flip_flop.v common_--clock_modeling_method_route 7149779-dirty success 3 4 3 4 3 3 1 2 1 -1 -1 6 0.524421 -0.946421 -0.524421 0 3 14 17 2 7 2 0.839717 -0.949074 -0.839717 -0.378643 -0.378643 53894 53894 3674.13 408.237 5249.31 583.257 0.00 0.00 -1 -1 -1 0.01 0.00 0.00 0.00 0.17 10648 5296 32744
timing/k6_N10_40nm.xml mkPktMerge.v common_--clock_modeling_method_ideal 7149779-dirty success 191 347 163 179 8 8 18 5 156 -1 -1 46 1.10064 -11.3912 -1.10064 154 9 8 62 17 46 11 1.12213 -12.816 -1.12213 0 0 1.94018e+06 970092 31896.9 498.390 38234.5 597.414 0.24 0.16 -1 -1 -1 0.03 0.07 0.03 0.01 1.76 17360 48924 55092
timing/k6_N10_40nm.xml mkPktMerge.v common_--clock_modeling_method_route 7149779-dirty success 191 347 163 179 8 8 18 5 156 -1 -1 52 1.07989 -11.71 -1.07989 153 10 14 94 7 57 5 1.39384 -13.0997 -1.39384 -2.70752 -0.350803 1.94018e+06 970092 55056.7 860.261 74677.5 1166.84 0.24 0.15 -1 -1 -1 0.03 0.06 0.05 0.01 1.79 17692 48928 55204
