)]}'
{
  "id": "1bc2778760e46c70333382930b772061c3f52fa0",
  "repo": "third_party/yosys",
  "revision": "32f0296df1b97ff5b3bcc442ac38f27a786947d6",
  "path": "manual/APPNOTE_012_Verilog_to_BTOR.tex"
}