)]}'
{
  "id": "e9ca6114e01a98f890f166b7d425c5591a586791",
  "repo": "third_party/yosys",
  "revision": "3b405d985e789ecf0082f724d2d62d3752e4b60c",
  "path": "manual/CHAPTER_Verilog.tex"
}