)]}'
{
  "id": "0ecdf61942245810f0663fc674da99ad96e44713",
  "repo": "third_party/yosys",
  "revision": "3e0ffe05a79d3196b3644cddf422edb927673b04",
  "path": "manual/APPNOTE_010_Verilog_to_BLIF.tex"
}