Merge pull request #1501 from YosysHQ/dave/mem_copy_attr
memory_collect: Copy attr from RTLIL::Memory to cell
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index 6acbce6..9dcb3f0 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -218,6 +218,10 @@
mem->setPort("\\RD_DATA", sig_rd_data);
mem->setPort("\\RD_EN", sig_rd_en);
+ // Copy attributes from RTLIL memory to $mem
+ for (auto attr : memory->attributes)
+ mem->attributes[attr.first] = attr.second;
+
for (auto c : memcells)
module->remove(c);
