read_verilog latches.v

proc
flatten
# Can't run any sort of equivalence check because latches are blown to LUTs
#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check

#design -load preopt
synth_ice40
cd top
select -assert-count 4 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D