)]}'
{
  "id": "e176c3e2cd44faa9812669a9f95703805406c611",
  "entries": [
    {
      "mode": 33188,
      "type": "blob",
      "id": "aadbcdcdd51512e5917e74772f92ba667c81ac0f",
      "name": ".gitignore"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "6a8462b4189ab968a98235f2095e5da6e72464ec",
      "name": "Makefile.inc"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "4bf5b1cf53cd788283517924bab7245ddf3d1140",
      "name": "const2ast.cc"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "dea22ee8a946f482d3a391f4570b9aab58778f67",
      "name": "preproc.cc"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "0e2bead6f905a99dd1d2e146235038c18052d152",
      "name": "verilog_frontend.cc"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "a7c9b2fe6ab71303f037d7c0ee5dfb2896766d76",
      "name": "verilog_frontend.h"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "57e55b1f4a0e03753a6077805e804305ca339718",
      "name": "verilog_lexer.l"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "4afd72b734b2aadebaf75d86683e8928f29b87e4",
      "name": "verilog_parser.y"
    }
  ]
}