)]}'
{
  "commit": "4f426c2ac48bbb5ae9e92ca046aa20af35d75a52",
  "tree": "f3a646aa0fba1dfa89a336cace906a37b75648e8",
  "parents": [
    "be0eaf3a9abd410d9ea2962a186b104d8ed0cc04"
  ],
  "author": {
    "name": "whitequark",
    "email": "whitequark@whitequark.org",
    "time": "Sun Sep 22 16:52:06 2019 +0000"
  },
  "committer": {
    "name": "whitequark",
    "email": "whitequark@whitequark.org",
    "time": "Sun Sep 22 16:52:06 2019 +0000"
  },
  "message": "write_verilog: do not print (*init*) attributes on regs.\n\nIf an init value is emitted for a reg, an (*init*) attribute is never\nnecessary, since it is exactly equivalent. On the other hand, some\ntools that consume Verilog (ISE, Vivado, Quartus) complain about\n(*init*) attributes because their interpretation differs from Yosys.\n\nAll (*init*) attributes that would not become reg init values anyway\nare emitted as before.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "7b1db4776fc15aeb7f93a59ef5dd54b6658ca1e3",
      "old_mode": 33188,
      "old_path": "backends/verilog/verilog_backend.cc",
      "new_id": "24e397bda272bb676af82e663aef5acc62d400be",
      "new_mode": 33188,
      "new_path": "backends/verilog/verilog_backend.cc"
    }
  ]
}