)]}'
{
  "id": "e9ca6114e01a98f890f166b7d425c5591a586791",
  "repo": "third_party/yosys",
  "revision": "5501d9090aaf2d508b2f082f8453effe7fce08df",
  "path": "manual/CHAPTER_Verilog.tex"
}