Merge pull request #1540 from YosysHQ/mwk/xilinx-bufpll
xilinx: Add missing blackbox cell for BUFPLL.
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 46890b0..6271333 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -153,11 +153,6 @@
if (wire->port_input)
sigmap.add(wire);
- // promote output wires
- for (auto wire : module->wires())
- if (wire->port_output)
- sigmap.add(wire);
-
for (auto wire : module->wires())
{
bool keep = wire->attributes.count("\\keep");
@@ -173,7 +168,7 @@
}
if (keep)
- keep_bits.insert(bit);
+ keep_bits.insert(wirebit);
if (wire->port_input || keep) {
if (bit != wirebit)
@@ -824,7 +819,7 @@
log(" write ASCII version of AIGER format\n");
log("\n");
log(" -map <filename>\n");
- log(" write an extra file with port and latch symbols\n");
+ log(" write an extra file with port and box symbols\n");
log("\n");
log(" -vmap <filename>\n");
log(" like -map, but more verbose\n");
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index 6acbce6..9dcb3f0 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -218,6 +218,10 @@
mem->setPort("\\RD_DATA", sig_rd_data);
mem->setPort("\\RD_EN", sig_rd_en);
+ // Copy attributes from RTLIL memory to $mem
+ for (auto attr : memory->attributes)
+ mem->attributes[attr.first] = attr.second;
+
for (auto c : memcells)
module->remove(c);
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index 2c45670..f59f978 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -83,7 +83,9 @@
bool operator==(const ExtSigSpec &other) const { return is_signed == other.is_signed && sign == other.sign && sig == other.sig && semantics == other.semantics; }
};
-#define BITWISE_OPS ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($and), ID($or), ID($xor), ID($xnor)
+#define FINE_BITWISE_OPS ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)
+
+#define BITWISE_OPS FINE_BITWISE_OPS, ID($and), ID($or), ID($xor), ID($xnor)
#define REDUCTION_OPS ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($reduce_nand)
@@ -250,14 +252,19 @@
shared_op->setPort(ID(CO), alu_co.extract(0, conn_width));
}
- shared_op->setParam(ID(Y_WIDTH), conn_width);
+ bool is_fine = shared_op->type.in(FINE_BITWISE_OPS);
+
+ if (!is_fine)
+ shared_op->setParam(ID(Y_WIDTH), conn_width);
if (decode_port(shared_op, ID::A, &assign_map) == operand) {
shared_op->setPort(ID::B, mux_to_oper);
- shared_op->setParam(ID(B_WIDTH), max_width);
+ if (!is_fine)
+ shared_op->setParam(ID(B_WIDTH), max_width);
} else {
shared_op->setPort(ID::A, mux_to_oper);
- shared_op->setParam(ID(A_WIDTH), max_width);
+ if (!is_fine)
+ shared_op->setParam(ID(A_WIDTH), max_width);
}
}
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 0ba5290..5d3b9c2 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -347,9 +347,9 @@
index <SigBit> port(postAdd, AB)[0] === sigP[0]
filter GetSize(port(postAdd, AB)) >= GetSize(sigP)
filter port(postAdd, AB).extract(0, GetSize(sigP)) == sigP
- // Check that remainder of AB is a sign-extension
- define <bool> AB_SIGNED (param(postAdd, AB == \A ? \A_SIGNED : \B_SIGNED).as_bool())
- filter port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(AB_SIGNED ? sigP[GetSize(sigP)-1] : State::S0, GetSize(port(postAdd, AB))-GetSize(sigP))
+ // Check that remainder of AB is a sign- or zero-extension
+ filter port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(sigP[GetSize(sigP)-1], GetSize(port(postAdd, AB))-GetSize(sigP)) || port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(State::S0, GetSize(port(postAdd, AB))-GetSize(sigP))
+
set postAddAB AB
optional
endmatch
diff --git a/tests/arch/xilinx/dsp_fastfir.ys b/tests/arch/xilinx/dsp_fastfir.ys
new file mode 100644
index 0000000..0067a82
--- /dev/null
+++ b/tests/arch/xilinx/dsp_fastfir.ys
@@ -0,0 +1,69 @@
+read_verilog <<EOT
+// Citation https://github.com/ZipCPU/dspfilters/blob/master/rtl/fastfir.v
+module fastfir_dynamictaps(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_result);
+ wire [30:0] _00_;
+ wire [23:0] _01_;
+ wire [11:0] _02_;
+ wire [30:0] _03_;
+ wire [23:0] _04_;
+ wire [30:0] _05_;
+ wire [23:0] _06_;
+ wire [30:0] _07_;
+ wire [23:0] _08_;
+ wire [11:0] _09_;
+ wire [30:0] _10_;
+ wire [23:0] _11_;
+ wire [30:0] _12_;
+ wire [23:0] _13_;
+ wire [11:0] \fir.FILTER[0].tapk.delayed_sample ;
+ reg [30:0] \fir.FILTER[0].tapk.o_acc = 31'h00000000;
+ wire [11:0] \fir.FILTER[0].tapk.o_sample ;
+ reg [23:0] \fir.FILTER[0].tapk.product ;
+ reg [11:0] \fir.FILTER[0].tapk.tap = 12'h000;
+ wire [11:0] \fir.FILTER[1].tapk.delayed_sample ;
+ wire [30:0] \fir.FILTER[1].tapk.o_acc ;
+ wire [11:0] \fir.FILTER[1].tapk.o_sample ;
+ reg [23:0] \fir.FILTER[1].tapk.product ;
+ reg [11:0] \fir.FILTER[1].tapk.tap = 12'h000;
+ input i_ce;
+ input i_clk;
+ input i_reset;
+ input [11:0] i_sample;
+ input [11:0] i_tap;
+ input i_tap_wr;
+ output [30:0] o_result;
+ reg [30:0] o_result;
+ assign _03_ = 31'h00000000 + { \fir.FILTER[0].tapk.product [23], \fir.FILTER[0].tapk.product [23], \fir.FILTER[0].tapk.product [23], \fir.FILTER[0].tapk.product [23], \fir.FILTER[0].tapk.product [23], \fir.FILTER[0].tapk.product [23], \fir.FILTER[0].tapk.product [23], \fir.FILTER[0].tapk.product };
+ assign _04_ = $signed(\fir.FILTER[0].tapk.tap ) * $signed(i_sample);
+ always @(posedge i_clk)
+ \fir.FILTER[0].tapk.tap <= _02_;
+ always @(posedge i_clk)
+ \fir.FILTER[0].tapk.o_acc <= _00_;
+ always @(posedge i_clk)
+ \fir.FILTER[0].tapk.product <= _01_;
+ assign _02_ = i_tap_wr ? i_tap : \fir.FILTER[0].tapk.tap ;
+ assign _05_ = i_ce ? _03_ : \fir.FILTER[0].tapk.o_acc ;
+ assign _00_ = i_reset ? 31'h00000000 : _05_;
+ assign _06_ = i_ce ? _04_ : \fir.FILTER[0].tapk.product ;
+ assign _01_ = i_reset ? 24'h000000 : _06_;
+ assign _10_ = \fir.FILTER[0].tapk.o_acc + { \fir.FILTER[1].tapk.product [23], \fir.FILTER[1].tapk.product [23], \fir.FILTER[1].tapk.product [23], \fir.FILTER[1].tapk.product [23], \fir.FILTER[1].tapk.product [23], \fir.FILTER[1].tapk.product [23], \fir.FILTER[1].tapk.product [23], \fir.FILTER[1].tapk.product };
+ assign _11_ = $signed(\fir.FILTER[1].tapk.tap ) * $signed(i_sample);
+ always @(posedge i_clk)
+ \fir.FILTER[1].tapk.tap <= _09_;
+ always @(posedge i_clk)
+ o_result <= _07_;
+ always @(posedge i_clk)
+ \fir.FILTER[1].tapk.product <= _08_;
+ assign _09_ = i_tap_wr ? \fir.FILTER[0].tapk.tap : \fir.FILTER[1].tapk.tap ;
+ assign _12_ = i_ce ? _10_ : o_result;
+ assign _07_ = i_reset ? 31'h00000000 : _12_;
+ assign _13_ = i_ce ? _11_ : \fir.FILTER[1].tapk.product ;
+ assign _08_ = i_reset ? 24'h000000 : _13_;
+ assign \fir.FILTER[1].tapk.o_acc = o_result;
+endmodule
+EOT
+
+synth_xilinx
+cd fastfir_dynamictaps
+select -assert-count 2 t:DSP48E1
+select -assert-none t:* t:DSP48E1 %d t:BUFG %d
diff --git a/tests/opt/bug1525.ys b/tests/opt/bug1525.ys
new file mode 100644
index 0000000..972bc0a
--- /dev/null
+++ b/tests/opt/bug1525.ys
@@ -0,0 +1,13 @@
+read_verilog << EOF
+module top(...);
+input A1, A2, B, S;
+output O;
+
+assign O = S ? (A1 & B) : (A2 & B);
+
+endmodule
+EOF
+
+simplemap
+opt_share
+dump
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index 64b625e..4d5879e 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -218,12 +218,6 @@
endmodule
// Citation: https://github.com/alexforencich/verilog-ethernet
-// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test022" abc9.v -q
-// returns before b4321a31
-// Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [7] is used but has no
-// driver.
-// Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [3] is used but has no
-// driver.
module abc9_test022
(
input wire clk,
@@ -237,9 +231,6 @@
endmodule
// Citation: https://github.com/riscv/riscv-bitmanip
-// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test023" abc9.v -q
-// returns before 14233843
-// Warning: Wire abc9_test023.\dout [1] is used but has no driver.
module abc9_test023 #(
parameter integer N = 2,
parameter integer M = 2
