Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd
xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 46890b0..a77949b 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -153,11 +153,6 @@
if (wire->port_input)
sigmap.add(wire);
- // promote output wires
- for (auto wire : module->wires())
- if (wire->port_output)
- sigmap.add(wire);
-
for (auto wire : module->wires())
{
bool keep = wire->attributes.count("\\keep");
@@ -173,12 +168,13 @@
}
if (keep)
- keep_bits.insert(bit);
+ keep_bits.insert(wirebit);
if (wire->port_input || keep) {
if (bit != wirebit)
alias_map[bit] = wirebit;
input_bits.insert(wirebit);
+ undriven_bits.erase(bit);
}
if (wire->port_output || keep) {
@@ -186,6 +182,8 @@
if (bit != wirebit)
alias_map[wirebit] = bit;
output_bits.insert(wirebit);
+ if (!wire->port_input)
+ unused_bits.erase(bit);
}
else
log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit));
@@ -193,12 +191,6 @@
}
}
- for (auto bit : input_bits)
- undriven_bits.erase(sigmap(bit));
- for (auto bit : output_bits)
- if (!bit.wire->port_input)
- unused_bits.erase(bit);
-
// TODO: Speed up toposort -- ultimately we care about
// box ordering, but not individual AIG cells
dict<SigBit, pool<IdString>> bit_drivers, bit_users;
@@ -824,7 +816,7 @@
log(" write ASCII version of AIGER format\n");
log("\n");
log(" -map <filename>\n");
- log(" write an extra file with port and latch symbols\n");
+ log(" write an extra file with port and box symbols\n");
log("\n");
log(" -vmap <filename>\n");
log(" like -map, but more verbose\n");
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index 6acbce6..9dcb3f0 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -218,6 +218,10 @@
mem->setPort("\\RD_DATA", sig_rd_data);
mem->setPort("\\RD_EN", sig_rd_en);
+ // Copy attributes from RTLIL memory to $mem
+ for (auto attr : memory->attributes)
+ mem->attributes[attr.first] = attr.second;
+
for (auto c : memcells)
module->remove(c);
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index 2c45670..f59f978 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -83,7 +83,9 @@
bool operator==(const ExtSigSpec &other) const { return is_signed == other.is_signed && sign == other.sign && sig == other.sig && semantics == other.semantics; }
};
-#define BITWISE_OPS ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($and), ID($or), ID($xor), ID($xnor)
+#define FINE_BITWISE_OPS ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)
+
+#define BITWISE_OPS FINE_BITWISE_OPS, ID($and), ID($or), ID($xor), ID($xnor)
#define REDUCTION_OPS ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($reduce_nand)
@@ -250,14 +252,19 @@
shared_op->setPort(ID(CO), alu_co.extract(0, conn_width));
}
- shared_op->setParam(ID(Y_WIDTH), conn_width);
+ bool is_fine = shared_op->type.in(FINE_BITWISE_OPS);
+
+ if (!is_fine)
+ shared_op->setParam(ID(Y_WIDTH), conn_width);
if (decode_port(shared_op, ID::A, &assign_map) == operand) {
shared_op->setPort(ID::B, mux_to_oper);
- shared_op->setParam(ID(B_WIDTH), max_width);
+ if (!is_fine)
+ shared_op->setParam(ID(B_WIDTH), max_width);
} else {
shared_op->setPort(ID::A, mux_to_oper);
- shared_op->setParam(ID(A_WIDTH), max_width);
+ if (!is_fine)
+ shared_op->setParam(ID(A_WIDTH), max_width);
}
}
diff --git a/tests/opt/bug1525.ys b/tests/opt/bug1525.ys
new file mode 100644
index 0000000..972bc0a
--- /dev/null
+++ b/tests/opt/bug1525.ys
@@ -0,0 +1,13 @@
+read_verilog << EOF
+module top(...);
+input A1, A2, B, S;
+output O;
+
+assign O = S ? (A1 & B) : (A2 & B);
+
+endmodule
+EOF
+
+simplemap
+opt_share
+dump
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index 64b625e..4d5879e 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -218,12 +218,6 @@
endmodule
// Citation: https://github.com/alexforencich/verilog-ethernet
-// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test022" abc9.v -q
-// returns before b4321a31
-// Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [7] is used but has no
-// driver.
-// Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [3] is used but has no
-// driver.
module abc9_test022
(
input wire clk,
@@ -237,9 +231,6 @@
endmodule
// Citation: https://github.com/riscv/riscv-bitmanip
-// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test023" abc9.v -q
-// returns before 14233843
-// Warning: Wire abc9_test023.\dout [1] is used but has no driver.
module abc9_test023 #(
parameter integer N = 2,
parameter integer M = 2
