read_verilog ../common/adffs.v
design -save read

hierarchy -top adff
proc
equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:DFFC
select -assert-count 3 t:IBUF
select -assert-count 1 t:OBUF

select -assert-none t:DFFC t:IBUF t:OBUF %% t:* %D


design -load read
hierarchy -top adffn
proc
equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adffn # Constrain all select calls below inside the top module
select -assert-count 1 t:DFFC
select -assert-count 1 t:LUT1
select -assert-count 3 t:IBUF
select -assert-count 1 t:OBUF

select -assert-none t:DFFC t:IBUF t:OBUF t:LUT1 %% t:* %D


design -load read
hierarchy -top dffs
proc
equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module
select -assert-count 1 t:DFFS
select -assert-count 4 t:IBUF
select -assert-count 1 t:OBUF

select -assert-none t:DFFS t:IBUF t:OBUF %% t:* %D


design -load read
hierarchy -top ndffnr
proc
equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module
select -assert-count 1 t:DFFNR
select -assert-count 1 t:LUT1
select -assert-count 4 t:IBUF
select -assert-count 1 t:OBUF

select -assert-none t:DFFNR t:IBUF t:OBUF t:LUT1 %% t:* %D