hierarchy: Correct handling of wildcard port connections with default values
Signed-off-by: David Shah <dave@ds0.me>
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 0704c26..c298a66 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -983,6 +983,15 @@
}
}
+ // Determine default values
+ dict<IdString, dict<IdString, Const>> defaults_db;
+ if (!nodefaults)
+ {
+ for (auto module : design->modules())
+ for (auto wire : module->wires())
+ if (wire->port_input && wire->attributes.count("\\defaultvalue"))
+ defaults_db[module->name][wire->name] = wire->attributes.at("\\defaultvalue");
+ }
// Process SV implicit port connections
std::set<Module*> blackbox_derivatives;
std::vector<Module*> design_modules = design->modules();
@@ -1019,6 +1028,11 @@
continue;
// Make sure a wire of correct name exists in the parent
Wire* parent_wire = find_implicit_port_wire(module, cell, wire->name.str());
+
+ // Missing wires are OK when a default value is set
+ if (!nodefaults && parent_wire == nullptr && defaults_db.count(cell->type) && defaults_db.at(cell->type).count(wire->name))
+ continue;
+
if (parent_wire == nullptr)
log_error("No matching wire for implicit port connection `%s' of cell %s.%s (%s).\n",
RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
@@ -1034,13 +1048,6 @@
if (!nodefaults)
{
- dict<IdString, dict<IdString, Const>> defaults_db;
-
- for (auto module : design->modules())
- for (auto wire : module->wires())
- if (wire->port_input && wire->attributes.count("\\defaultvalue"))
- defaults_db[module->name][wire->name] = wire->attributes.at("\\defaultvalue");
-
for (auto module : design->modules())
for (auto cell : module->cells())
{
diff --git a/tests/various/sv_implicit_ports.sh b/tests/various/sv_implicit_ports.sh
index 13d39cf..2faac2e 100755
--- a/tests/various/sv_implicit_ports.sh
+++ b/tests/various/sv_implicit_ports.sh
@@ -54,3 +54,14 @@
endmodule
EOT
) 2>&1 | grep -F "ERROR: Width mismatch between wire (7 bits) and port (8 bits) for implicit port connection \`b' of cell top.add_i (add)." > /dev/null
+
+# Defaults
+../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
+module add(input [7:0] a = 8'd00, input [7:0] b = 8'd01, output [7:0] q);
+assign q = a + b;
+endmodule
+
+module top(input [7:0] a, output [7:0] q);
+ add add_i(.*);
+endmodule
+EOT
