)]}'
{
  "id": "e9ca6114e01a98f890f166b7d425c5591a586791",
  "repo": "third_party/yosys",
  "revision": "7a6dec1cef9c6a44dafe83d884abaf06dc77ab07",
  "path": "manual/CHAPTER_Verilog.tex"
}