tree f637930db9d29efaeb4609017f07761f012b6d99
parent 84982b308343315c889d3d00116db820a51cad78
parent 4f426c2ac48bbb5ae9e92ca046aa20af35d75a52
author Clifford Wolf <clifford@clifford.at> 1572168301 +0100
committer GitHub <noreply@github.com> 1572168301 +0100
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Merge pull request #1393 from whitequark/write_verilog-avoid-init

write_verilog: do not print (*init*) attributes on regs