)]}'
{
  "commit": "84982b308343315c889d3d00116db820a51cad78",
  "tree": "9eabe561c9a24e57bddff83886e996c015bd3e3c",
  "parents": [
    "34dadd9ab20494057c1ac7dae443b48eee0c2c30"
  ],
  "author": {
    "name": "Clifford Wolf",
    "email": "clifford@clifford.at",
    "time": "Thu Oct 24 12:13:37 2019 +0200"
  },
  "committer": {
    "name": "Clifford Wolf",
    "email": "clifford@clifford.at",
    "time": "Thu Oct 24 12:13:50 2019 +0200"
  },
  "message": "Improve naming scheme for (VHDL) modules imported from Verific\n\nSigned-off-by: Clifford Wolf \u003cclifford@clifford.at\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "c6839041813f5f189c6d9bdd95dffc9fe273a7c3",
      "old_mode": 33188,
      "old_path": "frontends/verific/verific.cc",
      "new_id": "a5c4aa26a75c677d08f4d128e37a53a5a61786c1",
      "new_mode": 33188,
      "new_path": "frontends/verific/verific.cc"
    }
  ]
}