diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index 0fe2c8c..cc1ac48 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -302,6 +302,12 @@
 	assign O = I;
 endmodule
 
+module TBUF (O, I, OEN);
+  input I, OEN;
+  output O;
+  assign O = OEN ? I : 1'bz;
+endmodule
+
 module GSR (input GSRI);
 	wire GSRO = GSRI;
 endmodule
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index e9b2ccd..d541edd 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -174,7 +174,7 @@
 			run("synth -run coarse");
 		}
 		
-                if (!nobram && check_label("bram", "(skip if -nobram)"))
+		if (!nobram && check_label("bram", "(skip if -nobram)"))
 		{
 			run("memory_bram -rules +/gowin/bram.txt");
 			run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v");
@@ -230,7 +230,7 @@
 			run("techmap -map +/gowin/cells_map.v");
 			run("setundef -undriven -params -zero");
 			run("hilomap -singleton -hicell VCC V -locell GND G");
-			run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)");
+			run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O, -toutpad TBUF OEN:I:O", "(unless -noiopads)");
 			run("dffinit  -ff DFF Q INIT");
 			run("clean");
 
diff --git a/tests/arch/gowin/tribuf.ys b/tests/arch/gowin/tribuf.ys
new file mode 100644
index 0000000..5855b9d
--- /dev/null
+++ b/tests/arch/gowin/tribuf.ys
@@ -0,0 +1,13 @@
+read_verilog ../common/tribuf.v
+hierarchy -top tristate
+proc
+tribuf
+flatten
+synth
+equiv_opt -assert -map +/gowin/cells_sim.v -map +/simcells.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd tristate # Constrain all select calls below inside the top module
+#Internal cell type used. Need support it.
+select -assert-count 1 t:TBUF
+select -assert-count 2 t:IBUF
+select -assert-none t:TBUF t:IBUF %% t:* %D