)]}'
{
  "id": "0ecdf61942245810f0663fc674da99ad96e44713",
  "repo": "third_party/yosys",
  "revision": "907c8aeaef4a0a06beda9126b23aae3bfcd53b65",
  "path": "manual/APPNOTE_010_Verilog_to_BLIF.tex"
}